Abstract: A semiconductor device, for example an IC, having conductor tracks (3) of a metal (3) exhibiting a better conductance than aluminium, such as copper, silver, gold or an alloy thereof. The tracks are situated on an insulating layer (2) and are connected to a semiconductor region (1A) or to an aluminium conductor track by means of a metal plug (5), for example of tungsten, which is situated in an aperture (4) in the insulating layer (2). The bottom and walls of the aperture (4) are provided with an electroconductive material (6), such as titanium nitride, which forms a diffusion barrier for the metal (3). In accordance with the invention, the insulating layer (2) comprises a sub-layer (2A), which forms a diffusion barrier for the metal (3) and which extends, outside the aperture (4), throughout the surface of the semiconductor body (10). As a result, the conductor tracks (3) no longer have to be provided with a sheath serving as a diffusion barrier for the metal (3).

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures placed in series with oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a supply terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate involving providing a metal wafer; forming a low melting point oxide layer over the metal wafer; forming a first insulation layer over the low melting point oxide layer to provide a first structure; providing a second structure comprising a silicon layer and a second insulation layer; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer forming a buried insulation layer; and removing a portion of the silicon layer thereby providing the silicon-on-insulator substrate comprising a silicon device layer, the buried insulation layer, the low melting point oxide layer, and the metal wafer.

Abstract: An integrated circuit including a substrate having a memory area and a non-memory area. An embedded memory is fabricated on the substrate within the memory area. First and second semiconductor cells are fabricated on the substrate within the non-memory area. An electromagnetic shield covers substantially memory area. A routing layer is fabricated over the memory and non-memory areas and over the electromagnetic shield. A signal wire is electrically coupled between the first and second semiconductor cells and has a conductive segment which is routed within the routing layer and extends over the memory area.

Abstract: A semiconductor device according to the present invention includes insulating branches which are formed as an interlayer insulating film on a semiconductor substrate. The interlayer insulating film has holes (voids) between the branches to thereby reduce electrostatic capacitance between stacked layers within a semiconductor device.

Abstract: An integrated circuit (IC) is provided. The IC includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer and metal layer form a die active area. The IC further includes a guard ring, enclosing the die active area. The guard ring has zig-zag shaped portions at corners thereof.

Abstract: HSQ is employed as a dielectric layer in manufacturing a high density, multi-metal layer semiconductor device. The degradation of deposited HSQ layers during formation of the semiconductor device, as from photoresist stripping using an O.sub.2 -containing plasma, is avoided by forming first and second dielectric layers on the HSQ layer, forming a photoresist mask on the second dielectric layer and etching to form an opening in the second dielectric layer leaving the first dielectric layer exposed. The first dielectric layer protects the HSQ from degradation during subsequent stripping.

Abstract: A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up device replacing standard PMOS pull-up loads used in connection with static memory cells, thereby increasing the cell density of a static memory array.

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Abstract: A totally self-aligned transistor with shallow trench isolation. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. Channel dopant deposited in the gate area is also self-aligned to the gate of the transistor.

Abstract: A polycrystalline silicon coated nitride-lined shallow trench technique for isolating active regions on an integrated circuit involves reducing the oxide encroachment and the "bird's beak" structure. The technique involves forming an isolation trench, or recess, in the substrate. This recess is then lined with a layer of silicon dioxide layer, and then a layer of silicon nitride. Subsequently, a polycrystalline silicon material is deposited in the recess and is then oxidized to form a field oxide and planarized. Since the recess is nitride-lined, which prevents oxidizing species from reaching the oxide layer beneath the nitride layer, and the polycrystalline silicon is oxidized, the result is zero oxide encroachment resulting in the elimination of the "bird's beak" structure.

Abstract: Prevents deterioration of the element characteristics of the gate voltage tolerance and the like which is caused by the metallic contaminants that are sealed in the element forming region at the time of applying a trench separator in a SOI substrate. Polysilicon 12 is formed on the side walls of the trench 5, and the metallic contaminants within the element forming region are collected in this polysilicon 12.

Abstract: The invention provides a structure of a bonding pad, which comprising: a substrate; a dielectric layer formed over the substrate; a first metal layer formed in the dielectric layer; a second metal layer formed in the dielectric layer and above the first metal layer; a plurality of first plugs formed between the first metal layer and the second metal layer, wherein the plugs are used for connecting the first metal layer with the second metal layer; a third metal layer formed over the dielectric layer; and a plurality of second plugs, formed between the second metal layer and the third metal layer, wherein the second plugs are used for connecting the second metal layer with the third metal layer.

Abstract: A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures placed in series with oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a supply terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surface of the semiconductor wafer on the dielectric layer to form a composite structure. A portion of the semiconductor wafer from a second surface which is opposite the first surface is removed and the second surface of the semiconductor wafer is processed. Processing of the second surface optionally includes the formation of isolation trenches electrically isolating the laterally distributed semiconductor devices.

Abstract: In a semiconductor employing shall trench isolation, a subtrench conductive layer formed before the isolation dielectric is present by implanting dopants into the floor and sidewalls of the shallow trench using a large tilt angle (LTA) implant. The subtrench conductive layer is advantageously used to interconnect what would normally be isolated devices. In lieu of metal or polysilicon interconnects which reside over the isolation dielectric, the subtrench conductive layer is formed entirely within the silicon substrate, and resides beneath and laterally adjacent the isolation dielectric. The conductive layer is formed by implanting ions into the floor and sidewalls of a shallow trench prior to filling the trench with the isolation dielectric. The implantation at specified dosages presents a layer of dopant within the exterior surfaces of the trench sidewalls and floor. Implantation or diffusion of source/drain regions occur after the conductive layer is formed and the isolation dielectric is formed.

Abstract: A semiconductor integrated circuit (IC) device has a silicon-on-insulator substrate having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a silicon layer formed on the insulating film. The semiconductor IC device includes at least one semiconductor device formed on the semiconductor substrate, and at least one semiconductor device formed on the silicon layer and operated with a power-supply voltage different from a power-supply voltage for the semiconductor device formed on the semiconductor substrate.

Abstract: In a power microwave hybrid integrated circuit, a depth of recesses (2) in a metal base (1) is selected so that a face surface of chips (3) and a metal base (1) are coplanar, a dielectric board (5) has a shield ground metallization (10) on its back side at the places adjoining the metal base (1), the metal base (1) is sealingly joined and electrically connected to the shield grounding metallization (10) of the board (5), and interconnecting holes (7) of the board (5) are filled with an electrically conducting material (9), the spacing between the side surfaces of the chips (3) and the side surfaces of the recesses (2) in the base (1) being of 0.001 to 0.2 mm.

Abstract: In order to avoid any concentration of an electric field to gate edges of a two-layered structure and to improve an accumulation performance of charge, a semiconductor device includes a semiconductor substrate; an element isolation region formed to define an element formation region in the semiconductor substrate; a first gate insulating layer formed in a part of a surface of the element formation region; a first gate electrode formed on the first gate insulating layer; an insulating layer for surrounding the first gate electrode with a top surface of the insulating layer being substantially in the same plane as that of a top surface of the first electrode; a second gate insulating layer formed on the first gate electrode; and a second gate electrode formed on the second gate insulating layer. Also, a method therefor is provided.

Abstract: An isolator having a driver circuit which responsive to an input signal drives appropriate signals into one or more coils which are magnetically coupled to one or more corresponding MR or GMR elements whose resistance is variable in response to the magnetic field applied by the coil(s), and an output circuit that converts the resistance changes to an output signal corresponding to the input signal. A Faraday shield is interposed between the coil(s) and the MR or GMR elements. Common mode transients applied to the driver are capacitively coupled from the coil(s) into the Faraday shield and therethrough to ground, instead of into the MR elements. A second Faraday shield may be disposed in spaced relationship with the first Faraday shield and referenced to the potential of the MR elements for even greater common mode rejection. The entire structure may be formed monolithically as an integrated circuit on a single substrate, for low cost, small size, and low power consumption.

Abstract: A semiconductor device composed of analog circuits operated by multiple power supplies is provided with a structure which enables to reduce cross talk sufficiently. In the present semiconductor device, first and second transistors formed on the p-type silicon substrate are surrounded by third and fourth high concentration n-type buried layers extending beyond two trenches provided so as to separately surround the first and second transistors. An n-type layer is formed on these high concentration n-type layers, and first and second electrodes are formed on the n-type layer. Electric potentials of the third and fourth high concentration n-type layers are stabilized at a fixed value by the supply of power through the electrodes mounted on the these layers in order to prevent cross talk.

Abstract: A multi-level integrated circuit metalization system having a composite dielectric layer comprising a layer 22 of diamond or sapphire. A plurality of patterned metalization layers is disposed over a semiconductor substrate 10. A composite dielectric layer is disposed between a pair of the metalization layers. The composite dielectric layer 22 comprises a layer of diamond or sapphire. The diamond or sapphire layer has disposed on a surface thereof one of the patterned metalization layers. A conductive via 34 passes through the composite layer. One end of the conductive via is in contact with diamond or sapphire layer. The diamond or sapphire layer conducts heat laterally along from the metalization layer disposed thereon to a heat sink provided by the conductive via. The patterned diamond or sapphire layer provides a mask during the second metalization deposition.

Abstract: A silicon-on-insulator structure (10) having a thick buried multi-layer (14) is disclosed herein. The thick buried multi-layer (14) comprises a thermal expansion coefficient matching layer (14b) between two insulator layers (14a,14c). The thermal expansion co-efficient matching layer (14b) comprises a material that more closely matches the thermal expansion co-efficient of the silicon substrate (12). Examples include polysilicon and nitridized oxide.

Abstract: A semiconductor device array having silicon device islands isolated from the substrate by an insulator. High array density is achieved by forming source and drain interconnects in the space between the islands. Also disclosed are processes for forming and programming such arrays.

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region of a semiconductor substrate. A doped polysilicon electrode having a first end and a second end. The doped polysilicon electrode is defined in the shallow trench isolation region and the first end is configured to be in electrical contact with the semiconductor substrate. The diode structure further includes a polysilicon gate that has an underlying gate oxide. The polysilicon gate is defined over the active region and extends over part of the shallow trench isolation region so as to make electrical interconnection between the polysilicon gate and the second end of the doped polysilicon electrode.

Abstract: A semiconductor device having the base region surrounded by at least two continuous slots. The collector region is surrounded by at least one continuous slot formed as a continuation of one of the at least two continuous slots surrounding the base region. The portions of the slots that are over the buried layer extends beyond the surface of the buried layer and the portions of the slots not over the buried layer extends beyond the interface between the epitaxial layer and the substrate. The slots are filled with either polysilicon or tungsten. The base region terminates on the surface of the innermost slot surrounding the base region. The boundary of the base region terminates substantially perpendicular to the surface of the surrounding slot.

Abstract: A method for maintaining a high field threshold voltage in a plurality of transistors of reduced size in a periphery region of a Flash EPROM semiconductor circuit includes forming a first polysilicon layer as a floating poly in a predetermined number of transistors of the plurality of transistors in the periphery region, and forming a second polysilicon layer as a common gate line in the plurality of transistors, wherein the predetermined number of transistors prevent breakdown of the plurality of transistors below a predetermined field threshold voltage. In one aspect, the field oxide layer has a thickness of about 2500 angstroms.

Abstract: Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates by advantageously tapering the sidewalls of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the suicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

Abstract: A semiconductor device and a method of making the semiconductor device, the semiconductor device having a base region wherein the base region is surrounded by a slot. The sideways depletion region of the collector-base junction terminates on the slot thus reducing the sideways spreading of the collector-base depletion region.

Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract: A contact region for a trench in a semiconductor device and a method for electrically contacting the conductive material in a trench that is too narrow for conventional electrical contacts may include a contact region in which the trench is divided into two or more trench sections, each section having the same narrow width as the undivided trench. The two or more trench sections are separated by one or more islands that are isolated from the semiconductor device. An aperture through the material above the contact region provides access for electrically contacting the conductive material in the trench sections.

Abstract: The non-volatile semiconductor device includes a sub control gate in addition to the conventional structure having a control gate and a floating gate. When writing or erasing is performed, by applying various to the control gate and the sub control gate, the potential of the floating gate which is capacitively connected to the control and sub control gates is determined. Accordingly, the floating gate voltage is maintained at lower control voltage compared to conventional one by selecting larger coupling ratio. The sub control gate covering a part where charge concentration apt to occur avoids charge concentration and deterioration of the tunnel oxide film.

Abstract: On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and source.cndot.drain is formed. An insulating layer is formed on the surface of the semiconductor substrate. In an opening of the insulating layer above the source.cndot.drain, a tungsten plug is formed. At a dicing line portion, the insulating layer has a trench portion. The trench portion is formed to surround the device forming region. A tungsten street having a top surface continuous to the top surface of the insulating layer is formed in the trench. By this semiconductor device, short-circuit between bonding pads and the like can be prevented, and the reliability can be improved.

Abstract: A power IC having an SOI structure including at least a supporting substrate as a bottom layer, a substrate insulating film, an SOI conductive film, an SOI insulating film, and an Si film. The Si film serving as a top layer of the SOI structure is divided into a plurality of active layers by element isolation dielectric regions, and a desired semiconductor element is formed in each active layer. A total capacitance between each active layer and the supporting substrate is small and an inversion layer formed at a bottom of the active layer in the conventional SOI substrate is prevented from being induced. The power IC is constituted at least by an element A in a first active layer and an element B in a second active layer operating in association with the element A. The first active layer is electrically connected to the SOI conductive film just under the first and second active layers.

Abstract: Formed on a grounded semiconductor substrate, via an insulation layer, is a semiconductor layer of the same conductive type as that of the substrate. Formed on the semiconductor layer are source and drain regions of the different conductive type from that of the substrate. The drain region is formed so that its portion reaches the insulation layer. A gate insulation film is formed on the semiconductor layer and a gate electrode is formed on the gate insulation film and between the source and drain regions. A conductive member is embedded in a through hole formed from a portion of the semiconductor layer to the semiconductor substrate via the insulation layer. A source electrode is formed so that the conductive member in the through hole and the source region are connected to each other by means of the source electrode. A drain electrode is connected to the drain region.

Abstract: Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.

Abstract: A semiconductor device includes a semiconductor element, such as a field effect transistor, and an adjacent connection region including a via hole. A simple structure prevents leakage current from flowing from a p-type buffer layer to a source electrode of the field effect transistor through a backside electrode and a via hole upper electrode, avoiding degradation in the gate-source dielectric resistance. A groove having a depth extending from a surface of an n-type semiconductor layer through a n-type semiconductor layer and a p-type buffer layer isolates a field effect transistor from a via hole that extends from the surface of an n-type semiconductor layer to a second surface of a compound semiconductor substrate. The groove prevents leakage current from flowing in a backside electrode in the via hole.

Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device comprises: a semiconductor substrate; an impurity injection layer formed in a surface of the semiconductor substrate; and a trench formed in the impurity injection layer for defining a plurality of element formation regions isolated one another by the trench, wherein the impurity injection layer extends to a depth inside the semiconductor substrate deeper at a first area below the trench than at a second area below each of the element formation regions.

Abstract: A semiconductor device, which can realize a high speed operation of a transistor with a small leakage current whenever such operation is required, is disclosed. A SOI layer is formed on a monocrystalline silicon substrate through a silicon oxide film, and C-MOS circuits (inverter circuits) are configured with P-channel type MOSFETs and N-channel type MOSFETs on the layer. A bias electrode for P-channel is disposed within the silicon oxide film facing the P-channel type MOSFETs, while a bias electrode for N-channel is disposed within the silicon oxide film facing the N-channel type MOSFETs.

Abstract: A semiconductor device with a base region that terminates on the surface of a slot that surrounds the base region. The base region terminates substantially perpendicular to the surface of the slot. The collector-base junction has substantially no cylindrical or spherical curvature.

Abstract: In a semiconductor assembly with a solder material layer and a method for soldering the semiconductor assembly, a silicon semiconductor body with a diffusion barrier layer is provided with a solder material layer, preferably a tin layer. The semiconductor body is then applied to a metal carrier plate and is directly soldered to the carrier plate by heating to temperatures to above 250.degree. C., i.e. without further additions.

Abstract: A buried silicide layer 111 in a bonded wafer 105 makes ohmic contact to a heavily doped buried layer 125. A dopant rapidly diffuses through the silicide layer and into the adjacent semiconductor to form the buried layer.

Abstract: A cross-talk source isolator is provided in an integrated circuit which has an impurity diffused substrate of low resistance on which a silicon region is developed. A digital and analog circuits are formed on the silicon region. A trench is formed in the silicon region, in a direction substantially normal to a major surface of the substrate, in a manner to separate said digital and analog circuits. The trench has a bottom portion reaching the substrate and having an inner wall covered with a dielectric material. The trench includes therewithin an electrically conductive member which has a first end portion electrically connected to the substrate. Further, the electrically conductive member has a second end portion, opposite to the first end portion, coupled to an electrode which leads to a reference voltage source such as ground.

Abstract: A semiconductor device having a bonded wafer structure capable of reducing crystal defect in a power element forming region thereof is disclosed. A recess is formed in a control circuit element forming region of a first n- silicon substrate, then filled with a silicon oxide film and subjected to grinding and polishing to provide a mirror-surface. An n- epitaxial layer is formed on the surface of a second n+ silicon substrate, then the surface of the epitaxial layer is coupled to the surfaces of the silicon oxide film and second circuit region of the first substrate and heat-treated to be bonded thereto.

Abstract: A structured dielectric layer and fabrication process for separating wiring levels and wires within a level on a semiconductor chip is described incorporating a lower dielectric layer having narrow air gaps to form dielectric pillars or lines and an upper dielectric layer formed over the pillars or fine lines wherein the air gaps function to substantially reduce the effective dielectric constant of the structured layer. The invention overcomes the problem of solid dielectric layers which would have the higher dielectric constant of the solid material used.

Abstract: An LSI semiconductor device having a device isolation structure and a method of fabricating the isolation structure are presented. The device is a buried-type field-shielding device which is fabricated in non-active regions of the LSI circuit, and includes field-shield insulator film formed on the interior walls of trench cavities formed on the substrate and the field-shield electrodes buried within the trench cavity. Unlike the conventional buried-type isolation devices, the top surface of present isolation structure is level with the upper surface of the substrate. Therefore, this device structure utilizes the interior space of the substrate rather than the surface area of the substrate as in the conventional field-shield isolation structure.

Abstract: An integrated semiconductor circuit, such as an A/D converter, includes a first zone having capacitors disposed therein. The capacitors have capacitor plates being formed of a first conductive layer and a second conductive layer. A second zone has circuit elements disposed therein. A planarizing layer and a cover layer insulate the first and second conductive layers from one another in the second zone, except for a possible peripheral region. A dielectric is formed only of the cover layer between the capacitor plates in the first zone, except for a possible peripheral region.

Abstract: A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surface of the semiconductor wafer on the dielectric layer to form a composite structure. A portion of the semiconductor wafer from a second surface which is opposite the first surface is removed and the second surface of the semiconductor wafer is processed. Processing of the second surface optionally includes the formation of isolation trenches electrically isolating the laterally distributed semiconductor devices.