Abstract: An energy relieving, redundant crack stop and the method of producing the same is disclosed. The redundant pattern allows the crack propagating energy that is not absorbed by the first ring of metallization to be absorbed by a second area of metallization and also provides a greater surface area over which the crack producing energy may be spread. The redundant crack stop is produced during the metallization process along with the rest of the wiring of the chip surface and, therefore, no additional production steps are necessary to form the structure.

Abstract: A method for suppressing an electromagnetic wave in a semiconductor manufacturing process contemplates diffusion of a material into a region where active elements for processing a high speed digital signal are massed. During a wafer manufacturing process, high temperature particles of the material is diffused to shield the active elements of the integrated circuit from electromagnetic waves, and the integrated circuit is packaged in a circuit interlocking a wafer chip and external electrical conducting pins emanating from the integrated circuit are wrapped with a material exhibiting a resistance varying directly with the frequency of a high frequency components of electromagnetic interference. Since a main portion is surrounded by a material for shielding an electromagnetic wave in a wafer manufacturing process and a package manufacturing process for the manufactured wafer chip, electromagnetic shielding is obtained relative to other circuits on the chip.

Abstract: An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is electrically connected to the substrate, by buried contact if desired, and can further be electrically connected to a source region formed within the active area. The polycrystalline silicon layer and substrate are connected to ground potential, thus preventing current flow between active areas.

Abstract: In a semiconductor integrated circuit, the wiring capacitance of the bus line region is reduced, so that the operation speed can be increased, the power consumption can be decreased, and the chip size can be reduced. On the upper surface of the field oxide film (4) formed on the semiconductor substrate (8), a non-conductive insulating oxide film (12) is formed by oxidizing the poly silicon layer (9). Further, the bus lines (3A) are formed on the oxide film (12) via the interlayer insulating film (6). Therefore, a distance between the bus lines (3A) and the substrate (8) can be increased to decrease the capacitance of the bus lines (3A).

Abstract: In an integrated circuit, capacitively coupled interference (digital-switching or analog cross-talk) is prevented by constructing shielded coaxial conductors for the analog signals. The coaxial configuration comprises a primary conductor for the analog signal surrounded by a secondary conductor that is electrically isolated from the primary one and that is connected to a clean power bus such as GND or Vdd. The outer secondary conductor shunts the digital noise energy to the power bus, preventing it from injecting noise into the analog primary conductor. A similar coaxial configuration is provided with a bootstrap follower to reduce the effects of parasitic capacitance for high-speed and small analog signals.

Abstract: An integrated high-performance decoupling capacitor, formed on a semiconductor chip, using the substrate of the chip itself in conjunction with a metallic deposit formed on the presently unused chip back surface and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor in close proximity to the active circuit on the chip requiring such decoupling capacitance.Specifically the present invention achieves this desirable result by providing a dielectric layer on the unused backside of the chip and forming a metal deposit on the formed backside dielectric layer and an electrical connection, between the metallic deposit and the active chip circuit via a through hole in the chip.

Abstract: In order to avoid any concentration of an electric field to gate edges of a two-layered structure and to improve an accumulation performance of charge, a semiconductor device includes a semiconductor substrate; an element isolation region formed to define an element formation region in the semiconductor substrate; a first gate insulating layer formed in a part of a surface of the element formation region; a first gate electrode formed on the first gate insulating layer; an insulating layer for surrounding the first gate electrode with a top surface of the insulating layer being substantially in the same plane as that of a top surface of the first electrode; a second gate insulating layer formed on the first gate electrode; and a second gate electrode formed on the second gate insulating layer. Also, a method therefor is provided.

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and nonsacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer.

Abstract: A method for fabricating a semiconductor device comprising fabricating a sacrificial wafer having a substrate wafer which includes a diffused layer and one or two epi layers. The sacrificial wafer is fusion bonded to a separately fabricated carrier/handle wafer having a layer of oxide on its surface, to form a composite wafer. Selective regions of the composite wafer are anodized and oxidized to form a plurality of wells separated from each other by a dielectric insulating layer. Next, N- epi regions above P+ epi regions are removed or alternatively, P+ diffused layers are removed from above an N- epi layer in selected regions. Finally, P- or N- single crystal silicon is grown back to the removed regions, depending on how the regions were removed. If N- single crystal is grown back to the removed regions, a high temperature drive-in is employed to finish the processing. The final structure contains N and P regions which are dielectrically isolated from each other and from the substrate.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors.

Abstract: An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap.

Abstract: Disclosed are an improved semiconductor memory cell suitable for high integration and a novel method of fabricating the same. The memory cell has a large capacitance and a small area. The memory cell also has a plurality of bit-lines buried in an isolation region in a semiconductor substrate. The bit-line has a very small width and thickness thereby reducing a parasitic capacity between the bit-line and the semiconductor substrate. The memory cell may further be provided with a noise shielding line. Further, disclosed is a novel memory cell array of a semiconductor memory. The buried bit-line is coupled with a bit-line connecting sub-arrays and both are separated by a insulation film. A plurality of pairs of the bit-lines are arranged in rows. A word-line is coupled with a sub-word line and both are separated by a insulation film. A plurality of pairs of the word-lines are arranged in columns. The memory cells are arranged at the intersections of the buried bit-lines and the word-lines.

Abstract: A planar inductor structure with improved Q compatible with typical integrated circuit fabrication. The structure includes a spiral inductor with a conductive plane between the resistive substrate of the integrated circuit and the spiral inductor which reduces the power loss of the inductor. A pattern of segments may be formed in the conductive material of conductive plane to prevent eddy currents from flowing through the conductive plane and reducing the inductance of the spiral inductor. The Q of the inductor can be enhanced by optimizing the pattern in which the segmented conductive plane is formed. The segmented conductive plane may be fabricated out of metal, polysilicon or a heavily-doped region of the substrate.

Abstract: A monolithic integrated circuit utilizing areas associated with unused devices for wiring signal lines, thereby implementing effective wiring and improving high frequency characteristics. A common substrate consisting of a semiconductor substrate, and active devices, capacitor electrodes and resistors formed on the semiconductor substrate, is followed by a dielectric film, a ground metal, a dielectric film whose thickness is equal to or greater than 1 .mu.m, and signal lines. A desired circuit is formed by connecting the signal lines with electrodes of the active devices and other elements via, holes in the dielectric films, and windows of the ground metal. The windows of the ground metal are formed over portions of active devices which are used as components of the circuit.

Abstract: A semiconductor device comprising: a semiconductor substrate; a diffused region extending from the surface and to the inside of the semiconductor substrate; a first insulating layer formed on the semiconductor substrate and having a contact hole located through which the diffused region is exposed; a first conductor layer formed on a portion of the first insulating layer and connected so the diffused region through the first contact hole; and an insulator section made of an oxide of the substance of the first conductor layer and formed on another portion of the first insulating layer to surround the first conductor layer.

Abstract: A signal isolation and decoupling structure fabricated in an integrated circuit device for providing signal isolation and decoupling for signal carrying conductors of the integrated circuit device, wherein one of the conductors is embedded in dielectric material and enclosed within an isolation structure of an electrically conductive material which is formed in the integrated circuit device and extends substantially the length of the conductor, the isolation structure including top and bottom walls of electrically conductive material and first and side walls, also of an electrically conductive material, which electrically interconnect the top and bottom walls, forming an enclosure around the conductor. Also described is a method for fabricating the isolation structure in the integrated circuit device.

Abstract: In a semiconductor device and a method for manufacturing the semiconductor device, a width of an element isolation region is reduced by a field-shield. A silicon oxide film of a side wall of a polycrystal silicon film is fabricated by thermally oxidizing a side wall of the polycrystal silicon film, while using a silicon nitride film as an antioxidation film. A width of a field-shield electrode made of the polycrystal silicon film is made smaller than a limit value of the very fine processing.

Abstract: The opening width of an element isolating trench is Wa'. The opening width of a substrate potential setting trench is Wb'. When the maximum film thickness of a polysilicon film lying on the side wall of each of the trenches is set to t, the opening width Wa' of the element isolating trench and the opening width Wb' of the substrate potential setting trench satisfies a condition that (Wa'-2t)<(Wb'-2t) and Wa'>2t. A silicon oxide film covers the entire portion of the internal surface of the element isolating trench and covers the internal surface of the substrate potential setting trench except the bottom portion thereof. Therefore, the polysilicon film in the element isolating trench is set in the electrically floating state and the polysilicon film in the substrate potential setting trench is connected to the semiconductor substrate.

Abstract: A MOSFET includes a first SiC semiconductor contact layer, a SiC semiconductor channel layer supported by the first SiC contact layer, and a second SiC semiconductor contact layer supported by the channel layer. The second contact and channel layers are patterned to form a plurality of gate region grooves therethrough. Each of the gate region grooves includes a base surface and side surfaces which are covered with groove oxide material. A plurality of metal gate layers are provided, each being supported in a respective one of the plurality of grooves. A plurality of deposited oxide layers are provided, each in a respective one of the grooves so as to be supported by a respective one of the plurality of metal gate layers. A first metal contact layer is applied to the surface of the first SiC contact layer, and a second metal contact layer is applied to a portion of the surface of the second SiC contact layer.

Abstract: A semiconductor device with air gaps 22 between metal leads 16, comprising metal leads 16 formed on a substrate 12, air gaps 22 between metal leads 16, a 10-50% porous dielectric layer 20 on the metal leads 16 and over the air gaps 22, and a non-porous dielectric layer 24 on the porous dielectric layer 20. Optional features include a patterned oxide 28 over the metal leads 16 and a passivation layer 26 over the metal leads 16 and patterned oxide 28. The porous dielectric layer 20 may comprise an aerogel or xerogel.

Abstract: A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut.

Abstract: A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a plurality of spaced field-shield isolation structures formed on a surface of the substrate and extending parallelly in a first direction to provide element-forming regions at spaces between every adjacent two of the field-shield element isolation layers, a pair of impurity diffusion layers of a second conductivity type different from the first conductivity type formed in the surface of the substrate at portions adjacent opposite sides of each of the element-forming regions, a plurality of spaced lateral regions defined on the surface of the substrate and extending parallelly in a second direction intersecting with the first direction; and a plurality of discrete gate electrodes formed on the surface of the substrate at portions corresponding to intersections of the lateral and element-forming regions, respectively, in electrically insulated relationship with the substrate, the gate electrodes being aligned along the late

Abstract: A lateral semiconductor device with enhanced breakdown characteristics includes a semiconductor substrate composite of first and second semiconductor substrates bonded to one another via an oxide film. An insulation film is buried in a separation trench which extends from a major surface of the first semiconductor substrate to the oxide film. An element region of 10 .mu.m or more in thickness is isolated by the separation trench from other element regions. First and second diffusion regions of opposite conductivity type are formed on the element region. The potential of the second substrate is fixed at one-third of the designed maximum breakdown voltage of the lateral semiconductor device. Alternatively, if the element region is 10 .mu.m or less in thickness, the potential of the second substrate is fixed at one-half of the designed maximum breakdown voltage of the lateral semiconductor device.

Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.

Abstract: A first interlayer insulating layer is formed on a main surface of a substrate. A semiconductor layer is formed on the first interlayer insulating layer. A gate electrode (word line) of a switch MOS transistor is formed under the semiconductor layer. A bit line and a capacitor are formed on the semiconductor layer. The semiconductor layer has a substantially flat upper surface, and an interlayer insulating layer and a second interlayer insulating layer having substantially flat upper surfaces are formed on the semiconductor layer. A capacitor is formed on the second interlayer insulating layer, and the capacitor and the second interlayer insulating layer are covered with a third interlayer insulating layer. Thereby, a level difference between a memory cell array and a peripheral circuitry can be reduced in a semiconductor memory device.

Abstract: An insulating film having a through hole aligned with an electrode on a first semiconductor element is formed on a first semiconductor substrate and a metal is disposed in the through hole. A second semiconductor element on a second semiconductor substrate is placed on the insulating film in such a way that an electrode of the second semiconductor element contacts the metal. Thus, a plurality of transistors having different performance characteristics and functions can be easily disposed adjacent to each other for improved integration.

Abstract: Undercutting of conductive lines in a dense array on a dielectric layer containing an open field is prevented by providing one or more non-functional components, such as one or more non-functional conductive lines, in the dielectric layer under the dense array of conductive lines.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: In a wiring and contact structure of a semiconductor device, a contact hole is formed to pass trough an interlayer insulating film and a gate oxide film and the contact hole is filled with a conductive material layer which projects from the interlayer insulating film. A first wiring layer is formed on the conductive material layer so as to partially overlap the contact hole, and an first insulating film is formed between the conductive material layer and the first wiring layer. A second insulating film having the same pattern as that of the first wiring layer is formed on the first wiring layer, and a third insulating film is formed as a side wall covering a side surface of the first wiring layer.

Abstract: A semiconductor substrate comprises a foundation, a semiconductor monocrystalline film formed on the foundation, and a high-melting-point metal film or a high-melting-point metal alloy film disposed in at least part of a region between the semiconductor monocrystalline film and the foundation. The high-melting-point metal film disposed below the semiconductor monocrystalline film can be utilized as a conductor in a semiconductor device.

Abstract: A semiconductor device with bipolar transistors formed in respective island regions in which collector regions of the bipolar transistors do not need to be pulled up to the top of the corresponding island regions and do not need to be contacted with a collector electrode on the top of the corresponding island regions. First and second semiconductor island regions are formed to be buried in a second insulator formed on a first insulator. First and second bipolar transistors are provided in the first and second island regions, respectively. An interconnection conductor for electrically interconnecting collector regions of the first and second transistors is formed in the second insulator and in contact with the collector regions of the first and second transistors. A common collector electrode formed on a third insulator covering the first and second island regions is electrically connected with the collector regions of the first and second transistors through the interconnection conductor, respectively.

Abstract: A process for making a crackstop on a semiconductor device is disclosed. The process involves creating and metallizing a groove surrounding the active region on a chip at the same time as other functional metallization is occurring, and then selectively etching out the metal in the groove after final passivation. In various embodiments the groove passes through the surface dielectric or the semiconductor substrate. In one embodiment the groove is replaced by hollow metal rings that can be stacked through multiple dielectric layers.

Abstract: A field shield isolating structure forms a structure for isolating elements of a semiconductor device. The field shield isolating structure includes a field shield gate insulating film and field shield electrode formed on the semiconductor substrate in separate processes to constitute a quasi-MOS transistor using impurity regions of adjacent MOS transistors. The film thickness of the field shield gate insulating film is set arbitrarily, the threshold voltage of the quasi-MOS transistor is set high, and then elements are insulated and isolated, so that the transistor is operated in the off state. The upper surface of the field shield electrode is also covered with the upper insulating film. The thicknesses of the upper insulating film and of the field shield gate insulating film is adjusted to have such values that prevent turning ON of the MOS transistor by the capacitance divided voltage. The voltage may be applied from upper conductive layers such as word lines formed above the upper insulating film.

Abstract: A semiconductor device and process for making the same with reduced capacitance between adjacent conductors on a connection layer. This technique works best at narrow conductor spacing (less than 1 micron), where the need for lower dielectric constant intralayer insulation materials accelerates. Directional deposition of a dielectric layer 14 at an acute angle relative to the plane of a semiconductor substrate 10 forms bridges between the tops of narrowly spaced conductors 12, resulting in the formation of one or more gas dielectric regions 18. The process is self-aligning, using the shadowing effect of the conductors themselves to mask deposition of dielectric material between them, and only bridges between conductors which are closely spaced. Subsequent deposition of an interlayer dielectric 20 completes a typical structure. The directional deposition method may, for instance, be electron beam evaporation of a material such as SiO.sub.2, Si.sub.3 N.sub.4, polyimide, or amorphous Teflon.

Abstract: A semiconductor device comprises a semiconductor substrate a field-shield electrode made of a thin film of at least one of polysilicon and amorphous silicon and formed on a surface of an element-isolation region of the substrate with an insulating film interposed therebetween for defining an active region in the substrate and a transistor having a gate electrode formed on a surface of the active region of the substrate with a gate insulating film interposed between the substrate and the gate electrode wherein the field-shield electrode is connected to a predetermined potential and the insulating film has a thickness of 5 nm-10 nm which is less than a thickness of the gate insulating film of the transistor.

Abstract: A semiconductor chip having an on-chip ground plane comprising a low resistivity semiconductor region in a plurality of non-device regions of the chip and reach-through regions electrically connected to the low resistivity semiconductor region. One or more front-side contacts are used to electrically connect the reach-through regions and the low resistivity semiconductor region to a ground potential to electrically ground the on-chip ground plane.

Abstract: A semiconductor circuit device includes a differential amplifier circuit having a first parasitic capacitor formed between the semiconductor substrate and a first resistor and a second parasitic capacitor formed between the semiconductor substrate and a second resistor. Each of the first and the second resistors is implemented by a wiring pattern over the substrate so that the first and the second parasitic capacitors are equivalent to each other.

Abstract: A trench capacitor memory cell having a semiconductor substrate, an active region having a transistor on a portion of the semiconductor substrate, a field region formed by removing portion of the semiconductor substrate except for portions of the active region to a certain depth below the surface of the semiconductor substrate, a capacitor trench region formed in contact with a part of the active region and within the field region, and a polysilicon plug formed within the field region except for the trench region, and insulated by being surrounded by an insulating layer.

Abstract: A semiconductor substrate comprises a foundation, a semiconductor monocrystalline film formed on the foundation, and a high-melting-point metal film or a high-melting-point metal alloy film disposed in at least part of a region between the semiconductor monocrystalline film and the foundation. The high-melting-point metal film disposed below the semiconductor monocrystalline film can be utilized as a conductor in a semiconductor device.

Abstract: In the solid-state image pickup device of the invention, a photodiode is formed on a semiconductor substrate, and a transfer channel is formed at a specific gap to the photodiode. On the semiconductor substrate, a transfer gate electrode formed through a gate dielectric film is provided, and an interlayer film is formed on the transfer gate electrode. Furthermore, a first light-shield film for shielding the transfer channel from light is formed on the interlayer film. On the first light-shield film, a second light-shield film is formed at least through an interlayer dielectric film. In this case, the interlayer dielectric film is composed of multiple layers of at least first interlayer dielectric film and second interlayer dielectric film, and in etching of the interlayer dielectric film, the second interlayer dielectric film is smaller in the etching rate to the first interlayer dielectric film, and the second interlayer dielectric film is formed beneath the first interlayer dielectric film.

Abstract: A monolithic high-Q inductor structure is formed with multiple metalization levels in a conventional integrated circuit technology in which inductor turns utilize these multiple levels to reduce the inductor resistance. Inductors with Q values above five can be integrated with this approach at radio and microwave frequencies.

Abstract: An SOI-type semiconductor device in which electrical elements formed on one semiconductor substrate are isolated from each other by an insulating film and a shield layer, to ensure a stable operation of the electrical elements against electrical noise etc., and at the same time, a stress relief film is formed between the insulating film and the shield layer to ensure that an SOI layer is stabilized by being free from crystal defects. A process for producing same is also disclosed.

Abstract: A method for forming a semiconductor on insulator device is provided that begins with an outer semiconductor layer (16). Trenches (12) of a predetermined depth are formed in outer semiconductor layer (16). An insulator layer (20) is formed outwardly from outer semiconductor layer (16). A mesa (18a) having a predetermined thickness is formed by removing portions of outer semiconductor layer (16) to expose a working surface such that mesa (18a) has a thickness substantially equal to the predetermined depth of the trenches (12) after the working surface is exposed.

Abstract: A light shield for a back-side thinned CCD has an aluminum reflective layer over the imaging surface of the CCD with a vanadium barrier layer between the aluminum reflective layer and the imaging surface. An optional oxide layer may be formed between the reflective and barrier layers.

Abstract: A method for fabricating a junction terminal extension structure for a high-voltage integrated circuit device. The method provides for the formation of two silicon oxide layers having a two-stage shaped final field region oxide in the proximity of the anode of a high-voltage integrated circuit device. A field region anode flat plate can be formed in the area of the two-stage shaped structure. The distance between the edge of the field region flat plate and the surface of the silicon substrate thus be increased to compared to prior art structures, and the electric field intensity therebetween can therefore be reduced, resulting in the increased breakdown voltage to increase the reliability of the integrated circuit device.

Abstract: At least one slit having a predetermined shape is formed around a contact region of a lower wiring layer formed on a substrate, and an insulating portion formed integrally with an insulating layer is embedded in this slit. This insulating layer is formed on the lower wiring layer and has a contact hole located at a position corresponding to the contact region. Since the insulating portion as a rectangular projecting portion projects into the slit downwardly from the rigid insulating layer, positional errors caused by thermal expansion of the lower wiring layer in annealing of the upper wiring layer can be suppressed, and an abnormal geometry such as a projection on the upper wiring layer can be prevented. In addition, a semiconductor device free from interwiring short-circuiting and excellent in flatness can be obtained.

Abstract: A semiconductor chip package wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that has a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.

Abstract: In a semiconductor memory device according to the present invention, a conductive layer is formed on a field oxide film in a boundary region on the main surface of a semiconductor substrate. A floating gate electrode, an interlayer insulating film, and a control gate electrode are formed on the semiconductor substrate in a memory cell array region with a gate insulating film interposed therebetween. A gate electrode is formed in a peripheral circuit region with the gate insulating film interposed therebetween. An interlayer insulating film is formed on the conductive layer, the gate electrode, and the control gate electrode. A contact hole is formed at a predetermined position of the interlayer insulating film. An interconnection layer is selectively formed on the interlayer insulating film including the inner surface of the contact hole. According to the present invention, it is possible to prevent formation of a concave portion on the surface of the field oxide film in the boundary region.

Abstract: A first semiconductor wafer having a semiconductor element such as a piezoresistive element or any integrated circuit located on a top surface thereof is bonded to a second semiconductor wafer so that the semiconductor element on the first wafer is received in a cavity sealed from the outside environment. The bottom surface of the second water is prepared by etching it about a mask pattern so that the pattern projects from the bottom surface, thereby forming the cavity and defining projecting surfaces which are bonded to corresponding projecting areas on the first wafer to create a hermetic seal therebetween. The second wafer is electrochemically etched to produce porous silicon with regions of non-porous monocrystalline silicon extending between the top and bottom surfaces. The porous areas are thermally oxidized to convert them to silicon dioxide while the non-porous regions bonded to bond pads of the resistive pattern on the first wafer act as extended contacts.