Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

Abstract: A semiconductor device includes a semiconductor body having a first surface. A first trench extends in a vertical direction into the semiconductor body. The semiconductor device also includes a first interlayer in the first trench and a first dopant source in the first trench. The first interlayer is arranged between the first dopant source and the semiconductor body, and the first dopant source includes a first dopant species. The semiconductor device also includes a semiconductor area doped with the first dopant species and which completely surrounds the first trench at least at a depth in the semiconductor body and adjoins the first trench.

Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body of the power semiconductor device; coupling a mask to the semiconductor body; and subjecting the semiconductor body to an ion implantation such that implantation ions traverse the mask prior to entering the semiconductor body.

Abstract: A pixel of an image sensor includes a well below a gate and containing a dopant at a first concentration, a shallow trench isolation (STI) configured to electrically isolate the well, and a channel stop adjacent to at least one border between the well and the STI and containing a dopant at a second concentration higher than the first concentration.

Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.

Abstract: A structure for picking up a collector region including a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, wherein a depth of the doped polysilicon layer is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the isolation regions.

Abstract: An organic light-emitting display device comprises a substrate, an anode electrode formed on the substrate, an organic layer formed on the anode electrode, a cathode electrode formed on the organic layer, and an organic capping layer formed on the cathode electrode and containing a capping organic material and a rare-earth material which has higher oxidizing power than the material which forms the cathode electrode.

Abstract: In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistor from being generated by the wall oxide film.

Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.

Abstract: A manufacturing method provides a semiconductor device with a substrate layer and an epitaxial layer adjoining the substrate layer. The epitaxial layer includes first columns and second columns of different conductivity types. The first and second columns extend along a main crystal direction along which channeling of implanted ions occurs from a first surface into the epitaxial layer. A vertical dopant profile of one of the first and second columns includes first portions separated by second portions. In the first portions a dopant concentration varies by at most 30%. In the second portions the dopant concentration is lower than in the first portions. The ratio of a total length of the first portions to the total length of the first and second portions is at least 50%. The uniform dopant profiles improve device characteristics.

Abstract: The present invention relates to a semiconductor device, comprising a semiconductor substrate (102) with a thickness of less than 100 micrometer and with a first substrate side and an opposite second substrate side. A plurality of at least four monolithically integrated Zener or avalanche diodes (164,166,168,170) with a reverse breakdown voltage of less than 20 V are defined in the semiconductor substrate and connected with each other in a series connection. The diodes are defined in a plurality of mutually isolated substrate islands (120,122,124,126) in the semiconductor substrate, at least one diode per substrate island. The substrate islands are laterally surrounded by through-substrate isolations extending from the first to the second substrate side and comprising a filling (128) that electrically isolates a respective substrate island from a respective laterally surrounding area of the semiconductor substrate.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.

Abstract: Conductive compositions which are useful as thermally conductive compositions and may also be useful as electrically conductive compositions are provided. The compositions include a conductive particle constituent in combination with a sintering aid which can, for example be a compound of the same metal in the nanometal, an organo-metallic, a metalorganic salt, mercaptan and/or resinate. In some embodiments the conductive particles include a small amount of nanoscale (<200 nm) particles. The compositions exhibit increased thermal conductivity.

Abstract: A photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel.

Abstract: A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.

Abstract: A semiconductor device and a method for manufacturing the same that reduces a process defect caused by pattern dependency in chemical mechanical polarization (CMP) or etching is excellent. The semiconductor device includes a device pattern formed on or in a substrate; and a plurality of dummy patterns having different longitudinal-sectional areas formed at one side of the device pattern. The dummy patterns, which have the same planar size but have different longitudinal-sectional areas from the three-dimensional structural point of view, include first dummy pattern having a first thickness and second dummy pattern having a second thickness larger than the first thickness.

Abstract: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

Abstract: A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same time, an annular projection is formed around the recess to thereby ensure the rigidity of the wafer. Accordingly, handling in shifting the wafer from the back side recess forming step to a subsequent step of forming a back side rewiring layer can be performed safely and easily.

Abstract: A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plurality of recess channels formed in the substrate between the first junction region and the second junction region.

Abstract: In a method of fabricating a flash memory device, a semiconductor substrate includes a tunnel insulating layer and a charge storage layer formed in an active region and a trench formed in an isolation region. A first insulating layer is formed to fill a part of the trench. A second insulating layer is formed on the first insulating layer so that the trench is filled. The first and second insulating layers are removed such that the first and second insulating layers remain on sidewalls of the charge storage layer and on a part of the trench. A third insulating layer is formed on the first and second insulating layers so that a space defined by the charge storage layer is filled. The third insulating layer is removed so that a height of the third insulating layer is lowered.

Abstract: A CMOS image sensor and a method for fabricating the same are disclosed, in which the boundary between an active region and a field region is not damaged by ion implantation. The method for fabricating a CMOS image sensor includes forming a trench in a first conductive type semiconductor substrate, forming a first conductive type heavily doped impurity ion region in the semiconductor substrate at both sides of the trench, forming a device isolation film by interposing an insulating film between the trench and the device isolation, sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate, and forming a second conductive type impurity ion region for a photodiode in the semiconductor substrate between the gate electrode and the device isolation film.

Abstract: A method for securing a semiconductor device component to another element is provided. An adhesive material includes a pressure-sensitive component and a curable component is used to at least temporarily secure the semiconductor device component and the other element to each other. The pressure-sensitive component of the adhesive material temporarily secures the semiconductor device component and the other element to one another. When the semiconductor device component and the other element are properly aligned, the curable component of the adhesive material may be cured to more permanently secure them to one another. For example, when a thermoset material is used as the curable component, it may be cured by heating, such as at a temperature of lower than about 200° C. and as low as about 120° C. or less.

Abstract: A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjacent the active region and comprises an insulating material. The active region and isolation region form a surface having a step therein. The semiconductor further comprises a dielectric material formed over the step. The dielectric material has a dielectric constant greater than about 8.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: A semiconductor device includes an isolation region which is formed in a semiconductor layer, and a resistance conductive layer which is in a sidewall shape. According to this semiconductor device, the resistance conductive layer having a high resistance can be obtained with a very small area. Thus, a novel semiconductor device including a resistance element can be provided.

Abstract: A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a substrate-bias variable transistor and a DTMOS. Field effect transistors (223) are formed on a P-type shallow well region (212). The depth of a shallow device isolation region (214) on the P-type shallow well region (212) is less than the depth of the junction between an N-type deep well region (227) and the P-type shallow well region (212). Therefore the field effect transistors (223) share the P-type shallow well region (212). The P-type shallow well regions (212) independently of each other are easily formed since they are isolated from each other by a deep device isolation region (226) and the N-type deep well region (227).

Abstract: Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. Methods of forming such integrated circuit devices are also provided.

Abstract: A semiconductor device includes a transistor junction formed in a substrate adjacent to an isolation region. A region between the transistor junction and the isolation region includes an area susceptible to hot carrier effects. The transistor junction extends from a surface of the substrate to a first depth. A buried conductive channel layer is formed within the transistor junction between the surface of the substrate and the first depth. The buried conductive channel layer has a peak conduction depth, which is different from a depth of the area susceptible to hot carrier effects.

Abstract: A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

Abstract: A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.

Abstract: A semiconductor device may include a first wiring layer 30, an interlayer dielectric layer 40 formed above the first wiring layer 30, a second wiring layer 50 formed above the interlayer dielectric layer 40, a through hole 60 formed in the second wiring layer 50 and the interlayer dielectric layer 40, and a contact layer 70 that is formed in the through hole 60 and electrically connects the first wiring layer 30 and the second wiring layer 50.

Abstract: In a method for producing a semiconductor configuration that includes at least two semiconductor elements, at least two differently doped surface regions are embodied on the top side of a semiconductor substrate. After that, an active layer structure including a plurality of layers is constructed on each of the surface regions, and each layer structure is associated with one of the semiconductor elements. Whichever are the lowermost electrically conductive layers toward the substrate in the active layer structures are electrically separated from one another.

Abstract: A semiconductor transistor formed between trench device isolation regions comprises; a gate electrode formed on a device formation region with the intervention of a gate insulating film and extended over the trench device isolation regions, a distance from an interface between the gate electrode and the gate insulating film to the surface of the device formation region and a distance from said interface to the trench device isolation region being the same, and a gate electrode wiring formed in self-alignment with the gate electrode to have the same length as the length of the gate electrode and connected on the gate electrode on the device formation region.

Abstract: Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. Methods of forming such integrated circuit devices are also provided.

Abstract: A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.

Abstract: In order that the yield can be enhanced, the method of manufacturing a semiconductor device comprises the steps of: forming first holes 101a not penetrating a support side silicon wafer 101; forming a ground insulating film 102; forming primary connection plugs 105a by charging copper into the first holes 101a; forming a semiconductor film 108 on one face side of the support side silicon wafer 101 through an intermediate insulating film 109; forming elements on the semiconductor film 108; exposing bottom faces of the primary connection plugs 105a by polishing the other face of the support side silicon wafer 101; forming second holes 111 extending from an element forming face of the semiconductor film 108 to the primary connection plugs 105; and forming auxiliary connection plugs 112a for electrically connecting the elements with the primary connection plugs 105a by charging copper into the second holes 111.

Abstract: Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An “emitter window” is masked directly over the polysilicon trench fill. Heavily doped single emitter poly is deposited and masked over the entire active region. The standard emitter drive then diffuses dopant through the emitter window into the undoped trench poly fill to provide an ohmic contact between the emitter poly and the trench poly fill. Contact to the emitter poly is made from overlying metal.

Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Abstract: A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.

Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.

Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

Abstract: An image sensor capable of preventing the degradation of pinned photodiodes and the generation of leakage current between neighboring pinned photodiodes is provided. The disclosed image sensor contains a plurality of pixel units, each pixel unit having a photodiode region. The image sensor includes a semiconductor substrate of a first conductivity type; a device isolation layer formed in the semiconductor substrate; a field stop layer formed beneath the device isolation layer; a trench formed in the semiconductor substrate, wherein the trench surrounds the photodiode region; a first doping region of the first conductivity type formed beneath the surface of the semiconductor substrate and beneath the surfaces of the trench; an insulating member filling the trench; and a second doping region of a second conductivity type formed in the semiconductor substrate under the first doping region.

Abstract: A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection. Source and drain regions are formed in the side surfaces of the semiconductor projection on opposite sides of the gate electrode. First and second device isolation insulating films are formed on the semiconductor substrate on opposite sides of the semiconductor projection. A first impurity region is formed in the semiconductor substrate below the first device isolation insulating film. A second impurity region is formed in the semiconductor substrate below the second device isolation insulating film. The first and second impurity regions are in contact with each other in the semiconductor substrate below the semiconductor projection.

Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

Abstract: An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.

Abstract: A process of fabricating a field effect transistor (FET) device uses the simultaneous implantation of the well species at the edge of the device and at the bottom of the shallow trench isolation (STI). This not only simplifies the process by defining the region for implantation at the device edge and at the bottom of the isolation with a single photo masking level, it also avoids the dual problems of corner Vt degradation and leakage across the bottom of the isolation trench. By implantation of the well species into the corner of the device region, the degradation of the corner Vt is mitigated by the additional channel doping in the edge of the device. The leakage across the bottom of the STI is eliminated by the simultaneous implantation of the well species at the interface thus raising the dopant level of the parasitic channel.

Abstract: A compensation component includes a drift path formed of p-conducting and n-conducting layers which are led around or along a trench. A process for producing the compensation component is also provided.

Abstract: The power MOSFET has a semiconductor layer formed on a highly doped semiconductor substrate of a first conductivity type. The semiconductor layer is itself of the other conductivity type and a highly doped source zone of the other conductivity type and a highly doped drain zone of the other conductivity type are formed in the semiconductor layer. The power MOSFET also has a gate electrode. A metallically conductive connection runs between the source zone and the semiconductor substrate, so that the power MOSFET is in the form of a source-down MOSFET, and the heat can be dissipated via the semiconductor substrate or a cooling fin fitted there.

Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure.

Abstract: A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of a gate structure formed on the microelectronic substrate. Spacers are formed around the gate structures, although little or no spacer forms around the isolation pad.