Vertical Walled Groove Patents (Class 257/513)
  • Patent number: 10818669
    Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 27, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel, Quentin Hubert, Thomas Cabout
  • Patent number: 10541202
    Abstract: An antifuse is provided that is embedded in a semiconductor substrate. The antifuse has a large contact area, and a reduced breakdown voltage. After blowing the antifuse, the antifuse has a low resistance. The antifuse may have a single breakdown point or multiple breakdown points. The antifuse includes a metal or metal alloy structure that is separated from a doped semiconductor material portion of the semiconductor substrate by an antifuse dielectric material liner. The metal or metal alloy structure and the antifuse dielectric material liner have topmost surfaces that are coplanar with each other as well as being coplanar with a topmost surface of the semiconductor substrate.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10535819
    Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: January 14, 2020
    Assignee: SK HYNIX INC.
    Inventors: Hyo June Kim, Chi Ho Kim, Sang Hoon Cho, Eung Rim Hwang
  • Patent number: 10522541
    Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
  • Patent number: 10490445
    Abstract: When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 26, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takao Kamoshima, Kojiro Horita, Shuji Matsuo
  • Patent number: 10453951
    Abstract: A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 22, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yutaka Fukui, Yasuhiro Kagawa, Kensuke Taguchi, Nobuo Fujiwara, Katsutoshi Sugawara, Rina Tanaka
  • Patent number: 10381458
    Abstract: A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew M. Greene, Balasubramanian P. Haran, Injo Ok, Charan V. Surisetty
  • Patent number: 10141472
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
  • Patent number: 10050171
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
  • Patent number: 10020305
    Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 10, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi Morii, Yoshitaka Otsu
  • Patent number: 9978638
    Abstract: A metal trench de-noise structure includes a trench disposed in a substrate, an insulating layer deposited on the sidewall of the trench, an Inter-Layer Dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the Inter-Layer Dielectric layer to fill up the trench. The metal layer may be grounded or floating.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: May 22, 2018
    Assignee: Realtek Semiconductor Corp.
    Inventor: Ta-Hsun Yeh
  • Patent number: 9881918
    Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
  • Patent number: 9716175
    Abstract: A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions (110) on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: July 25, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Qingqing Liang, Haizhou Yin, Zhijiong Luo
  • Patent number: 9614076
    Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.
    Type: Grant
    Filed: August 10, 2014
    Date of Patent: April 4, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi Morii, Yoshitaka Otsu
  • Patent number: 9590091
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: March 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Adrian Finney, Paolo Del Croce, Luca Petruzzi, Norbert Krischke
  • Patent number: 9564352
    Abstract: A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench and a second oxide layer formed over the first oxide layer, wherein the first oxide layer and the second oxide layer have a same composition.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: February 7, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jae-Soo Kim, Hyung-Kyun Kim
  • Patent number: 9484431
    Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Sanjay C. Mehta, Tenko Yamashita
  • Patent number: 9478457
    Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 25, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Ming-Shing Chen, Yu-Ting Wang, Ming-Hui Chang
  • Patent number: 9406548
    Abstract: Embodiments of present invention provide a method of making well isolations. The method includes forming a hard-mask layer on top of said substrate; forming a first resist-mask on top of a first portion of the hard-mask layer and applying the first resist-mask in forming a first type of wells in a first region of the substrate; forming a second resist-mask on top of a second portion of the hard-mask layer and applying the second resist-mask in forming a second type of wells in a second region of the substrate; applying the first and second resist-masks in transforming the hard-mask layer into a hard-mask, the hard-mask having openings aligned to areas overlapped by the first and second regions of the substrate; etching at least the areas of the substrate in creating deep trenches that separate the first and second types of wells; and filling the deep trenches with insulating materials.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Shom Ponoth, Theodorus Standaert, Tenko Yamashita
  • Patent number: 9263556
    Abstract: A device includes a semiconductor substrate including an active region. The active region includes a first sidewall. An isolation region extends from a top surface of the semiconductor substrate into the semiconductor substrate. The isolation region has a second sidewall, wherein a lower portion of the first sidewall joins a lower portion of the second sidewall to form an interface. A dielectric spacer is disposed on an upper portion of the first sidewall. A silicide region is over and contacting the active region. A sidewall of the silicide region contacts the dielectric spacer, and the dielectric spacer has a top surface substantially lower than a top surface of the silicide region.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Pang Hsieh, Chih-Ming Lee, Yu-Jen Chen
  • Patent number: 9159735
    Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yong-Shiuan Tsair, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Tsun-Kai Tsao, Ming-Huei Shen
  • Patent number: 9136347
    Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 15, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young Rak Park, Sang Choon Ko, Woojin Chang, Jae Kyoung Mun, Sung-Bum Bae
  • Patent number: 9006786
    Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material having the first lattice constant; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and a pair of notches extending into opposite sides of the middle portion; and an isolation structure surrounding the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the pair of notches.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H. Diaz, Jean-Pierre Colinge
  • Patent number: 8994144
    Abstract: A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench and a second oxide layer formed over the first oxide layer, wherein the first oxide layer and the second oxide layer have a same composition.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jae-Soo Kim, Hyung-Kyun Kim
  • Patent number: 8963281
    Abstract: Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer contact trench are simultaneously formed in a substrate. The substrate includes an insulating layer that defines a trench bottom of the handle wafer contact trench. A handle wafer is bonded to a bottom surface of the substrate. An oxide insulating layer is deposited in the isolation trench and the handle wafer contact trench. The oxide insulating layer is then etched so that the oxide insulating layer covering the trench bottom is at least partially removed. The trench bottom is then etched so that a top surface of the handle wafer is at least partially exposed. The handle wafer contact trench may then be at least partially filled with an electrical conductive material.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Christopher S. Blair
  • Patent number: 8866255
    Abstract: A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Stephan Voss, Markus Zundel
  • Patent number: 8823104
    Abstract: Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Tze-Liang Lee, Pang-Yen Tsai
  • Patent number: 8796106
    Abstract: A method is for the formation of at least one filled isolation trench having a protective cap in a semiconductor layer, and a semiconductor device with at least one filled isolation trench having a protective cap. The method allows obtaining, in an easy way, filled isolation trenches exhibiting excellent functional and morphological properties. The method therefore allows the obtainment of effective filled isolation trenches which help provide elevated, reliable and stable isolation properties.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Daniele Merlini, Domenico Giusti, Fabrizio Fausto Renzo Toia, Federica Ronchi
  • Patent number: 8759943
    Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Tseng, Da-Wen Lin, Chien-Tai Chan, Chia-Pin Lin, Li-Wen Weng, An-Shen Chang, Chung-Cheng Wu
  • Publication number: 20140159193
    Abstract: A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench and a second oxide layer formed over the first oxide layer, wherein the first oxide layer and the second oxide layer have a same composition.
    Type: Application
    Filed: March 14, 2013
    Publication date: June 12, 2014
    Applicant: SK hynix Inc.
    Inventors: Jae-Soo KIM, Hyung-Kyun KIM
  • Patent number: 8735228
    Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 27, 2014
    Assignee: PFC Device Corp.
    Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
  • Patent number: 8728907
    Abstract: A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 20, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ronald Kakoschke, Franz Schuler
  • Patent number: 8723289
    Abstract: A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; and forming storage node contact lines which fill the second damascene trenches.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: May 13, 2014
    Assignee: SK hynix Inc.
    Inventor: Chun Soo Kang
  • Patent number: 8698235
    Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 15, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8692353
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Ko, Jyh-Huei Chen, Ming-Jie Huang
  • Patent number: 8624349
    Abstract: Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer contact trench are simultaneously formed in a substrate. The substrate includes an insulating layer that defines a trench bottom of the handle wafer contact trench. A handle wafer is bonded to a bottom surface of the substrate. An oxide insulating layer is deposited in the isolation trench and the handle wafer contact trench. The oxide insulating layer is then etched so that the oxide insulating layer covering the trench bottom is at least partially removed. The trench bottom is then etched so that a top surface of the handle wafer is at least partially exposed. The handle wafer contact trench may then be at least partially filled with an electrical conductive material.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: January 7, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Christopher S Blair
  • Patent number: 8624295
    Abstract: A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Hung-Chih Tsai, Kong-Beng Thei, Mong-Song Liang
  • Patent number: 8575716
    Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: November 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
  • Patent number: 8525273
    Abstract: An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oh-kyum Kwon, Tae-jung Lee, Sun-hyun Kim
  • Publication number: 20130207229
    Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
    Type: Application
    Filed: March 13, 2013
    Publication date: August 15, 2013
    Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
  • Patent number: 8508018
    Abstract: Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: August 13, 2013
    Assignee: Intel Corporation
    Inventors: Rohan N. Akolkar, Sridhar Balakrishnan, James S. Clarke, Christopher J. Jezewski, Philip Yashar
  • Patent number: 8502308
    Abstract: A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: August 6, 2013
    Assignee: AMS AG
    Inventors: Martin Schrems, Jong Mun Park
  • Patent number: 8476734
    Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: July 2, 2013
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
  • Patent number: 8455974
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 4, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 8436419
    Abstract: A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside electrode on a back side of the semiconductor layer. The element portion is configured as a vertical transistor that causes an electric current to flow in a thickness direction of the semiconductor layer between the first wiring and the backside electrode. The backside electrode is elongated to the wiring portion. The wiring portion has a second wiring on the front side of the semiconductor layer. The wiring portion and the backside electrode provide a pulling wire that allows the electric current to flow to the second wiring.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: May 7, 2013
    Assignee: DENSO CORPORATION
    Inventors: Akira Yamada, Nozomu Akagi
  • Patent number: 8415739
    Abstract: A semiconductor component that includes an edge termination structure and a method of manufacturing the semiconductor component. A semiconductor material has a semiconductor device region and an edge termination region. One or more device trenches may be formed in the semiconductor device region and one or more termination trenches is formed in the edge termination region. A source electrode is formed in a portion of a termination trench adjacent its floor and a floating electrode termination structure is formed in the portion of the termination trench adjacent its mouth. A second termination trench may be formed in the edge termination region and a non-floating electrode may be formed in the second termination trench. Alternatively, the second termination trench may be omitted and a trench-less non-floating electrode may be formed in the edge termination region.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: April 9, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Zia Hossain
  • Patent number: 8410554
    Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8390028
    Abstract: A semiconductor device according to one embodiment includes an element isolation insulating film formed on a substrate, an element region and a dummy pattern region demarcated by the element isolation insulating film on the substrate, a first epitaxial crystal layer formed on the substrate within the element region, and a second epitaxial crystal layer formed on the substrate within the dummy pattern region. The first epitaxial crystal layer is made up of crystals that have a different lattice constant from that of the crystals that constitute the substrate. The second epitaxial crystal layer is made up of the same crystals as the first epitaxial crystal layer. The (111) plane of the substrate that includes any points on the interface between the second epitaxial crystal layer and the substrate is surrounded by the element isolation insulating film in a deeper region than the second epitaxial crystal layer.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Fujii
  • Patent number: 8372716
    Abstract: In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: February 12, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Peter J. Zdebel
  • Patent number: RE45633
    Abstract: Isolation methods and devices for isolating regions of a semiconductor device are disclosed. The isolation methods and structures include forming an isolating trench among pixels or other active areas of a semiconductor device. The trench extends through the substrate to the base layer, wherein a liner may be deposited on the side walls of the trench. A conductive material is deposited into the trench to block electrons from passing through.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 28, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Chandra Mouli