Abstract: A method for fabricating an integrated semiconductor configuration includes generating a polycrystalline layer at a surface of a base layer and doping the polycrystalline layer. An oxide layer is generated at the polycrystalline layer by rapid thermal oxidation so that the polycrystalline layer can be precisely structured. The method further includes structuring the main layer and performing the thermal oxidation at temperatures above 900° C. for less than 65 seconds. The method also includes carrying out the thermal oxidation as an initial processing step (after generating the main layer) at a temperature of at least substantially equal to the temperature for generating the main layer. A related semiconductor configuration and memory unit are also provided.

Abstract: An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.

Abstract: A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in regions directly below the isolation trench after partially filling the trench with the dielectric material. The dielectric along the sidewalls of the trenches can serve as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. The dielectric along the sidewalls of the trenches serves as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. After the ions are implanted in the substrate below the trenches, the remainder of the trench can be filled with the same or another dielectric material.

Abstract: A method of forming an isolation layer in semiconductor devices is disclosed. The method includes forming the isolating film by means of a method in which a method of forming a V-type trench at the isolation region, implanting ions capable of accelerating oxidization action into the center portion of the V-type trench, implementing an oxidization process to form an insulating film consisting of an oxide film at the isolation region, and then completely burying the trench with an insulating material, using the LOCOS method, and a method of forming a trench type isolation layer, are applied together. Therefore, as the top corner of the trench is formed with an inclination, and a concentration of the electric field and a formation of a moat can be simultaneously prevented.

Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.

Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.

Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

Abstract: An inventive method for fabricating a semiconductor device includes the steps of: a) forming trenches in an actual element region and a dummy pattern region of a substrate by using a mask; b) depositing an insulator over the substrate, thereby forming an insulating film that fills at least the trenches; and c) removing a portion of the insulating film protruded from the trenches, thereby forming, in the trenches within the actual element region, a first embedded insulating film for isolation, and forming a second embedded insulating film in the trenches within the dummy pattern region. The dummy pattern region has dummy patterns in which no trenches are formed, and the widthwise size of each dummy pattern is four times or less of the depth of a portion of each trench provided in the substrate.

Abstract: A semiconductor device for reducing junction leakage current and mitigating the narrow width effect, and a fabrication method thereof, are provided. The semiconductor device includes a semiconductor substrate in which an active region and an isolation region including a trench are formed, a spacer which is formed on both sidewalls of the trench, a channel stop impurity region which is self-aligned by the spacer and locally formed only at the lower portion of the isolation region, an isolation insulating layer in which the trench is buried, and a gate pattern which is formed on the isolation insulating layer and the active region. When the channel stop impurity region is formed only at the lower portion of the isolation region, isolation characteristics between unit cells can be improved, and also, a junction leakage current can be reduced.

Abstract: Disclosed is a semiconductor device including a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region formed between the source and drain regions, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein a punch-through stopper layer formed in a lower portion of the channel region has an impurity concentration higher than that of the channel region, and the source-drain diffusion layers do not extend to overlap with edge portion of insulating films for the element isolation.

Abstract: A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.

Abstract: A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection. Source and drain regions are formed in the side surfaces of the semiconductor projection on opposite sides of the gate electrode. First and second device isolation insulating films are formed on the semiconductor substrate on opposite sides of the semiconductor projection. A first impurity region is formed in the semiconductor substrate below the first device isolation insulating film. A second impurity region is formed in the semiconductor substrate below the second device isolation insulating film. The first and second impurity regions are in contact with each other in the semiconductor substrate below the semiconductor projection.

Abstract: A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage current. A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the semiconductor substrate with the gate insulation film therebetween. The dielectric constant of the gate insulation film is not uniform in the surface.

Abstract: The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Abstract: To provide a semiconductor apparatus that secures high ESD protection capability and yet reduces leak current. Cut sections 64-1 and 64-2 are provided in end sections of a second edge 62 of a drain region 22. When a distance between a first edge 60 of a source region 20 and the second edge 62 in an intermediate area is defined as L1, a distance between the first edge 60 and end edges 52-1 and 52-2 of a channel stopper non-implanted region 50 is defined as L1, a relation of L2? L1 is established. By providing the channel stopper non-implanted region 50, the ESD protection capability is improved. Also, by providing the cut sections 64-1 and 64-2 in a manner to satisfy the relation that is L2 is not less than L1, leak current is reduced. The source region 20 may also be provided with a cut section.

Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.

Abstract: A semiconductor configuration includes a substrate having a first conduction type. A transistor configuration is disposed at the substrate and is formed from at least one field-effect transistor having at least two doped regions embedded in the substrate and at least one gate electrode. The regions have a second conduction type, are disposed between the transistor configuration and the substrate edge, and extend from the substrate surface into the substrate and surround the transistor configuration. At least two adjacent insulating trench regions are disposed between the regions and extend from the substrate surface into the substrate for isolating the doped regions from one another. The trenches may have a smaller depth than the doped regions. A method for fabricating a semiconductor configuration includes providing a substrate having a first conduction type and producing regions in the substrate by introducing a dopant. The regions have a second conduction type.

Abstract: A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a buried oxide film is deposited on a buried oxide film formed in a substrate while an oxide film is formed on the surface of the substrate. An ion decelerator layer of an appropriate material with a specified thickness is selectively disposed only on part of the substrate overlying the well boundary region; then, first ion implantation and second ion implantation steps are carried out. Accordingly, as compared to those regions other than the well boundary region, the resultant well profile in the well boundary region is shifted in position or “offset” towards a shallower part.

Abstract: A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor with low body effect, the field implant blocking mask having appropriate openings so that the field implant occurs at the edges of the channel, thereby reducing leakage.

Abstract: A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.

Abstract: A semiconductor device is disclosed, together with a fabricating method therefor. The semiconductor device has an etch barrier structure, made with SiN or SiON, which is formed on an element-isolating region alongside an active region. Although there is an alignment error which causes the element-isolating region to be exposed, the etch barrier structure protects the element-isolating region from being etched when carrying out the etching processes for contact holes in a semiconductor memory cell. Thus, while preventing the deterioration of element-isolation properties, the etch barrier structure can affords a larger allowable alignment error in the etching processes for contact holes, so it is possible to make a small active region and thus, highly integrate semiconductor devices.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: A method for fabricating a high-bias device is provided. The method contains forming an N-type epitaxial silicon layer over a P-type substrate. At least a first stacked double well is formed in the epitaxial silicon layer at a region, where a field oxide (FOX) structure is to be formed. A second stacked double well is formed in the epitaxial silicon layer at a region, where a source region is to be formed inside. A FOX structure is formed on the first stacked double well. A gate oxide layer is formed on the epitaxial silicon layer. A conductive gate layer is formed over the substrate to cover a region extending from a portion of the FOX structure to a portion of the second stacked double well. A source region is formed in the second stacked double well with the second-type dopant. A drain region is formed in the epitaxial silicon layer at the opposite side of the FOX layer.

Abstract: A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

Abstract: A semiconductor structure includes a substrate, a microelectronic device formed on the substrate, and a dielectric layer including silicon dioxide formed over the microelectronic device. The silicon dioxide layer is doped with phosphorous in the form of approximately 96% SiO.sub.2 and 4% phosphorous (PH.sub.3) by weight, and has high etch selectivity, polish rate and gettering capability as well as excellent step coverage. The present process also improves uniformity and process control because phosphine is a gas and does not have to be vaporized prior to deposition.

Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces.

Abstract: A semiconductor device formed on an epitaxial substrate includes a high-resistance region in the vicinity of an interface between a doped semiconductor substrate and an epitaxial layer thereon. The high-resistance region is advantageously formed by an ion implantation process of a dopant opposite to a dopant contained in the doped semiconductor substrate such that there is formed a depletion of carriers in the vicinity of the foregoing interface.

Abstract: A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.

Abstract: An insulating trench isolation structure is formed in a semiconductor substrate with a spacer overlying the trench edge to prevent oxide loss during subsequent etching, thereby preventing junction leakage, particulary upon silicidation. Embodiments include providing a step in the trench fill and forming the nitride spacer during gate electrode sidewall spacer formation. The protective nitride spacer etches more slowly than oxide and, hence, remains after subsequent oxide etching and cleaning.

Abstract: A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.

Abstract: A highly integrated flash memory device having a stable cell is provided.

Abstract: An integrated circuit comprises a plurality of interconnected semiconductor devices, at least one the interconnected devices being dielectrically isolated from the substrate, and at least one other of the interconnected devices being junction isolated from the substrate. In a preferred embodiment, at least one of the junction isolated devices comprises an ESD protection circuit. The ESD protection circuit, which preferably includes a zener diode and more preferably further includes a bipolar transistor, a diode, and a resistor, is formed in a trench-isolated island comprising a semiconductor layer of a conductivity type opposite to that of the substrate. A heavily doped buried semiconductor region of the same conductivity type as the substrate is formed in the island semiconductor layer adjacent to the substrate.

Abstract: Element isolation technique for LSIs having a fine pattern of sub-micron class or finer. A high strained region doped with impurities at a high concentration is formed under, and remote from, a buried insulating material (dielectrics) layer for element isolation. With this buried dielectrics element isolation (BDEI) structure, since the high strained layer exists just under the buried dielectrics layer, crystal defects generated near the buried dielectrics layer due to strain caused by a difference of thermal expansion coefficient between a semiconductor layer and the buried dielectrics layer, are moved toward the high strained layer. Accordingly, the crystal defects do not reach an active region where active elements are formed, so that leakage current in the p-n junction formed in the active layer can be advantageously reduced.

Abstract: A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

Abstract: A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.

Abstract: A semiconductor device has a semiconductor substrate having a groove, and a semiconductor element formed in a surface region of the semiconductor substrate. A substance having a thermal expansion coefficient different from the semiconductor substrate is embedded in at least a portion of the groove, a crystal defect is generated from the region near the bottom of the groove in the semiconductor substrate, thereby alleviating stress and strain in other regions of the semiconductor substrate, such that such regions cannot generate crystal defects in a region necessary for a circuit operation of the semiconductor element of the surface region.

Abstract: A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide.

Abstract: Disclosed is an integrated circuit having at least two active components, such as transistors, having the following features:a highly conductive substrate is provided which is connected to one pole of a voltage supply source,a semiconductor layer, which is electrically isolated from the substrate and divided into individual sections by lateral isolation regions, is disposed on a main surface of the substrate,placed in each section is at least one active component, e.g., a transistor of any type performance, andlateral deep diffusion regions which are accommodated in the semiconductor layer create a conductive connection between the highly conductive substrate and the corresponding regions of the active components.

Abstract: The plurality of functioning circuits are formed in a plurality of P-type well regions formed on a remaining part of said low concentration N-type layer, by isolating from each other. According to the present invention, the photoelectric current from the PIN photodiode can be processed in the functioning circuits formed in the P-type well regions by isolating from each other, so that the interference between the functioning circuits can be prevented and also the shift of the current flowing in each functioning circuit due to the impossibility of the high concentration N-type semiconductor layer to be grounded can be prevented. Therefore, the malfunction of the integrated PIN photodiode sensor can be prevented, and the PIN photodiode sensor can operate with high speed because the distributed resistance between the functioning circuits is decreased.

Abstract: A semiconductor device, e.g., a DRAM, having vertical conduction transistors and cylindrical cell gates, which includes a plurality of spaced-apart trench isolation regions formed in a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a silicon pillar formed on each bit line, a gate insulating layer and gate line formed on each silicon pillar in surrounding relationship thereto, a planarizing layer formed in recesses in the gate lines, an insulating layer formed on the upper surfaces of the gate line and planarizing layer, a plurality of contact holes provided in vertically aligned portions of the insulating layer, the gate line, and the gate insulating layer located above respective ones of the silicon pillars, and, a storage node of a capacitor formed with the contact holes and adjacent surface portions of the insulating layer, in contact with the source region of respective ones of the silicon pillars.

Abstract: Dielectrically isolated semiconductor devices such as DMOS and ZGBT devices comprise a substrate having upper and lower surfaces. Source, drain and channel regions are disposed along the upper surface. The drain region extends downwardly to the lower surface of the substrate and laterally beneath the source and channel region. The drain merges with an underlying region of high conductivity. The underlying region is generally flat except for an upwardly extending portion thereof laterally disposed from the source region and providing a lower resistance path for current through the drain region. The DMOS devices can be included within an integrated circuit chip containing other types of semiconductor devices.

Abstract: A semiconductor device in which ability for isolating elements from each other can be improved and increase in substrate constant and junction capacitance can be suppressed, is disclosed. An impurity layer for improving the ability for isolating elements is positioned only immediately below an isolating insulating film. An impurity layer for adjusting substrate constant and junction capacitance is formed through independent steps from the impurity layer for improving the isolating ability.

Abstract: It is an object of the present invention to provide a semiconductor device which has a high electrical isolation capability and an enhanced electrical reliability for avoiding short circuit of individual conductive layers, and the present invention also provides a method of manufacturing such a semiconductor device. An n.sup.+ buried layer and an n.sup.- epitaxial growth layer are formed on a p.sup.- silicon substrate. An element isolation oxide film having a through hole is formed on the surface of n.sup.- epitaxial growth layer. A trench which penetrates through n.sup.- epitaxial growth layer and n.sup.+ buried layer to reach a predetermined depth of p.sup.- silicon substrate is formed under through hole. A first insulating layer covers the internal wall of trench. A covering layer covers the sidewall of through hole. A filling layer is formed to fill trench so that the top surface thereof is located within through hole. A second insulating layer is formed on filling layer.

Abstract: A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.

Abstract: A semiconductor device has a nobel configuration. The device includes a semiconductor substrate, element isolation regions formed on the main surface of the semiconductor substrate and at least one element region formed on the main surface of the semiconductor substrate and enclosed by the element isolation regions. In the device, the depth of each trench from the main surface to the bottom of the semiconductor substrate is shallow at a region where the trench width is less than a specified length, and it is deep at a region where the trench width is larger than the specified length.

Abstract: A new planarized device isolation structure within a semiconductor substrate is described. The device isolation structure comprises narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide, wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein the shallow trench is filled with a field oxide. The top surface of the narrow and wide device isolation regions and the semiconductor substrate is planarized.

Abstract: A non-volatile semiconductor memory device includes NAND type memory cells arranged in a matrix pattern over a semiconductor substrate and channel stopper layers, provided on the substrate, for separating adjacent NAND type memory cells. Each NAND type memory cell includes memory cell transistors having drains and sources mutually connected in series, a source side select transistor connected to a source of one end transistor of the memory cell transistors, and a drain side select transistor connected to a drain of the other end transistor of the memory cell transistors. Each channel stopper layer has a first layer portion for separating the source side select transistors and a second layer portion for separating the memory cell transistors. Impurity concentration of the first layer portion is lower than that of the second layer portion.

Abstract: An integrated circuit chip has both digital and analog circuit functions, with one or more islands for isolating the analog functions from noise caused by the digital functions. An island is defined by a surrounding heavily-doped region in the face of the chip. The voltage supplies for an analog island are isolated from the digital supply voltage for high frequencies by using resistive decoupling in series along with capacitive coupling to ground. Similarly, series resistive decoupling and capacitive coupling to ground are employed for the analog input signal lines going to the island. Analog signals generated within the island are coupled to the area outside the island on the chip face by either converting to digital in an A-to-D converter, or by a differential arrangement which accounts for differences that may exist between digital and analog supply voltages.

Abstract: A semiconductor structure of merged isolation and node trench construction is presented, along with a method of fabrication, wherein an isolation implant layer is formed at the intersection of the storage node, isolation trench and field isolation region. The isolation implant layer has higher concentration of implant species than the adjacent field isolation region and is positioned to prevent a parasitic leakage mechanism between the source/drain diffusion of the storage node and an adjacent bit line contact diffusion. Implantation occurs during memory structure fabrication through the deep trench sidewall near the upper surface of the substrate.