Abstract: A device isolation area structure in a semiconductor device is composed of two layers of a first device isolation film formed by selectively oxidizing a surface of a silicon substrate, and a second device isolation region formed in a single crystal silicon film covering the first device isolation film. A guard band region may be formed within the semiconductor substrate and immediately below the first device isolation film so as to be in contact with the first device isolation film. The device isolation area structure is suitable to high integration of the semiconductor device and provides less possibilities of occurrence of crystal defects.

Abstract: A device-isolating trench having a taper at its upper portion is formed in a silicon semiconductor substrate. Then, a silicon oxide film is formed on the inner wall of the trench and the surface of the semiconductor substrate near the trench by an oxidizing method, and polycrystalline silicon is buried in the trench.

Abstract: A P-type substrate is immersed in a solution of potassium hydroxide (KOH) which etches exposed portions of the substrate to form trenches with sidewalls at an angle of 54.7 degrees with respect to the top surface of the substrate. A vertical boron implant is then conducted which implants boron ions into the angled sidewalls of the trenches. A layer of oxide is then deposited over the substrate surface to fill the trenches approximately flush with the surface of the substrate. NMOS transistors may then be formed in the islands surrounded by the trenches so as to be isolated from other NMOS devices. The boron doping of the sidewalls prevents the inversion of the sidewalls due to any charged contaminants in the deposited oxide. This avoids parasitic leakage currents between the N-type source and drain regions of the NMOS transistors which abut the sidewalls of the trenches.

Abstract: A LOCOS oxide film is provided in a main surface of a semiconductor substrate for isolating an element region from another element region. A channel cut layer formed of a P-type impurity is provided under the element region. A P.sup.+ impurity region having a concentration thicker than that of P-type impurity of channel cut layer is formed directly under a bird's beak portion of LOCOS oxide film in the main surface of semiconductor substrate. Therefore, an isolation breakdown voltage of an N-channel transistor region is increased.

Abstract: A CMOS memory cell array, and a process for making it, that avoids problems caused by LOCOS isolation of cells. Moats are formed by etching away columns of a thick field oxide layer. The moats have two-tiered sidewalls, such that an upper tier is sloped, and a lower tier is more vertical. This approach provides the advantages of sloped sidewalls, but avoids filament problems. After the moats are formed, subsequent fabrication steps may be in accordance with conventional fabrication techniques for CMOS arrays.

Abstract: A dielectrically isolated photodiode having an increased p-n junction size with improved photo-carrier collection efficiency. The photodiode comprises a first layer of semiconductor material formed on the bottom and the walls of an isolation region; a second layer of semiconductor material formed on the first layer. The second layer forming a first p-n junction with the first layer and having opposite conductivity type compared to that of the first layer. The photodiode also comprises a third layer of semiconductor material formed on the second layer and electrically coupled to the first layer. The third layer having the same conductivity type as the first layer and forming a second p-n junction with the second layer. During operation, the first p-n junction functions to collect photo-generated carriers that extend to the bottom and walls of the isolation region, thereby increasing the active collecting p-n junction area per isolation region area to improve efficiency of the photodiode.

Abstract: The occupation area and thickness of dielectrically isolated island-resident transistor structures, which employ a buried subcollector for providing low collector resistance at the bottom of the island, are reduced by tailoring the impurity concentration of a reduced thickness island region to provide a low resistance current path from an island location directly beneath the base region to the collector contact. The support substrate is biased at a voltage which is less than the collector voltage, so that the portion of the collector (island) directly beneath the emitter projection onto the base is depleted of carriers prior to the electric field at that location reaching BCVEO, so as not to effectively reduce BVCEO.

Abstract: A power MOSFET device formed in a face of a semiconductor layer of a first conductivity type is provided. A first, second and third source region of a second conductivity type are formed in the face of the semiconductor layer within a moat and adjacent to its edges. A source conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first, second and third source regions at a plurality of locations. A first and second drain region of a second conductivity type is also formed in the face of the semiconductor layer disposed spaced from and between the first and second source regions and the second and third source regions, respectively. A drain conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first and second drain regions at a plurality of locations.

Abstract: A semiconductor device wherein a bipolar transistor and a junction type field effect transistor which has a high voltage resisting property and a high mutual conductance are formed into a single chip to reduce the cost. A bipolar transistor formation region is separated from a junction type field effect transistor formation region by a transistor separating region. In the former region, a collector diffused layer is formed on the semiconductor substrate on which an epitaxial layer is formed, and a base diffused layer and a collector lead diffused layer are formed in the epitaxial layer with an element separating region interposed therebetween and connect to the collector diffused layer. Further, an emitter diffused layer is formed on the base diffused layer. In the latter region, a bottom gate diffused layer is formed on the semiconductor substrate, and a channel formation region is formed in the epitaxial layer and connects to the bottom gate diffused layer.

Abstract: A method for dielectrically isolating a semiconductor integrated circuit is provided. Each integrated circuit is substantially surrounded by silicon oxide sidewalls which have been appropriately doped to be of an opposite conductivity type as the surrounding substrate. The doped silicon oxide sidewalls are formed prior to the growth of epitaxial silicon within the sidewalls. Upon deposition of the epitaxial silicon the dopant within the oxide sidewalls diffuses into the adjacent epitaxial silicon, thereby resulting in a heavily doped, low resistivity region of epitaxial silicon adjacent to and along the entire length of the oxide sidewall. This heavily doped region results in the substantial elimination of charge-depleting parasitic currents along the sidewalls during use of the integrated circuit. In addition, the heavily doped, low resistivity epitaxial region provides an electrically conductive contact to a buried layer within an integrated circuit having such a buried layer.

Abstract: A channel stop is self-aligned with a trench sidewall of a trench-isolated semiconductor architecture, so that there is no alignment tolerance between the stop and the trench wall. An initial masking layer, through which the trench pattern is to be formed in a semiconductor island layer, is used as a doping mask for introducing a channel stop dopant into a surface portion of the semiconductor layer where the trench is to be formed. The lateral diffusion of the dopant beneath the oxide and adjacent to the trench aperture defines the eventual size of the channel stop. The semiconductor layer is then anisotropically etched to form a trench to a prescribed depth, usually intersecting the underlying semiconductor substrate. Because the etch goes through only a portion of the channel stop diffusion, leaving that portion which has laterally diffused beneath the oxide mask, the channel stop is self-aligned with the sidewall of the trench.

Abstract: A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.

Abstract: A semiconductor device composed of a substrate provided with a groove filled with insulating material to define an element isolating region. The groove corners are rounded and the substrate contains impurity material below the groove and in a region adjacent the groove. The impurity material is introduced to have essentially the same impurity density profile below the bottom of the groove and below the substrate surface in the region adjacent the groove.The device may additionally be provided, if the region below and adjacent the groove is of P-type conductivity, with a buried P-type layer which opposes penetration of .alpha. particle radiation into the substrate.

Abstract: This invention relates to a semiconductor integrated circuit device wherein guardring regions are formed between a first element region and a second element region so as to surround the first element region, wherein gate electrodes are provided to cross the guardring regions, wherein the guardring regions are continuously formed even directly below the gate electrodes, and wherein an insulator film directly below the gate electrodes is relatively thick.

Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the wall from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.