Abstract: The present invention sets forth a process of making, and a device comprising, a capacitor with a damascene tungsten lower electrode. The capacitor is manufactured by first depositing an insulating nitride layer on a field oxide layer, followed by deposition of a layer of oxide on the nitride layer. A gap is etched into both the nitride and oxide layers, wherein a lower electrode comprising a damascene tungsten stud is deposited following deposition of a Ti/TiN liner for the stud. An oxide layer is next formed over the stud having a conducting tungsten channel with another Ti/TiN liner disposed therethrough and connecting with the stud. Then, a metal layer is deposited and etched to form both a contact for the stud via connection to the channel, and an upper electrode insulated from the contact.

Abstract: An integrated circuit having a voltage source and a plurality of conductive power bus tiers extending across the integrated circuit. Each of the power bus tiers are electrically coupled in parallel to the voltage source. The integrated circuit includes a filter capacitor having a first plate and a second plate that are separated by a capacitor dielectric. The first plate forms a bus strap coupling to each of the plurality of power bus tiers.

Abstract: The present invention reduces parasitic capacitance in a capacitive element distribution system by running unit electrode lead lines and common electrode lead lines in different directions so that the conductor lines may be sufficiently separated to suppress parasitic capacitance.

Abstract: An asymmetric snubber resistor in accordance with the present invention includes a cathode, an N+ region, an N- region, a plurality of P+ regions, and an anode. The N+ region is disposed over the cathode, the N- region is disposed over the N+ region, the plurality of P+ regions are disposed over the N- region, and the anode is disposed over the plurality of P+ regions and exposed portions of the N- region. The asymmetric snubber may also include N regions between the P+ regions. The asymmetric snubber resistor replaces the snubber diode and the snubber resistor in a typical snubber circuit.

Abstract: A balanced frequency responsive circuit comprising circuit components formed in a semiconductor chip having first and second on-chip contact terminals which connect to first and second off-chip contact terminals, respectively, and a balanced parallel resonator circuit coupled to the contact terminals. The resonator circuit comprises a capacitance portion and an inductance portion. Part of the capacitance portion is on-chip connected between the first and second on-chip contact terminals. Another part of the capacitance portion and the inductance portion are off-chip series connected between the first and second off-chip contact terminals such that the contact terminals are comprised in a single resonant loop, essentially producing no spurious resonance signals.

Abstract: An iridium layer (16) is formed on an inter-layer insulation film (12) and in an opening (14). The iridium layer (16) is constituted with a part to be a lower electrode (16a) of a capacitor and a part to be a wiring (16b) for coming into contact with a drain zone (6). On part of the lower electrode (16a) of the iridium layer (16) is formed a ferroelectric layer (18) made of PZT on which is further formed an iridium layer (20) as an upper electrode. Since the melting point of iridium is higher than that of aluminum, there is no possibility of iridium melting even if heat treatment is carried out after forming the iridium layer (16). Since reactivity between iridium and silicon is low, unnecessary silicon compound is not produced on the interface to provide favorable contact.

Abstract: In a capacitor, one capacitor electrode is formed on first principal face of a ceramic dielectric substrate. An area of a first capacitor electrode is smaller than an area of the first principal face. A second capacitor electrode is formed on a second principal face of the ceramic dielectric substrate, and connected to a lead electrode which is formed at the periphery of the first principal face of the ceramic dielectric substrate so as to be separated from the one capacitor electrode by a gap and to surround the first capacitor electrode. The ceramic capacitor is mounted on a semiconductor element through an insulating layer. The capacitor electrodes and lead electrode of the ceramic capacitor are connected to terminals of the semiconductor element by a wire bonding.

Abstract: A method for making a metal-to-metal capacitor for an integrated circuit includes forming a layer of titanium/titanium nitride on a polysilicon which has been patterned with interlevel dielectrics. A capacitor dielectric is then deposited, followed by patterning with photoresist to delineate the capacitor, etching to remove extraneous dielectric, deposition of aluminum, further patterning and etching to define the capacitor and access area, and removal of photoresist.

Abstract: A method of forming a dielectric layer includes, a) chemical vapor depositing a dielectric layer of Ta.sub.2 O.sub.5 atop a substrate; and b) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node; c) chemical vapor depositing a capacitor dielectric layer of Ta.sub.2 O.sub.5 over the first electrically conductive capacitor plate; and d) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A capacitor construction is also disclosed. The preferred amorphous diffusion barrier layer is electrically conductive and constitutes a metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.5, and "z" is in the range of from 0 to 0.

Abstract: Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum.

Abstract: An integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

Abstract: A semiconductor device which has a resistor, a capacitor, a Schottky diode, and an ESD protection device all formed on a single semiconductor substrate. The resistor and the capacitor are coupled together in series. The Schottky diode and the ESD protection device are coupled in parallel to the series connection of the resistor and capacitor.

Abstract: An integrated circuit structure including dielectric barrier layer compatible with perovskite ferroelectric materials and comprising zirconium titanium oxide, ZrTiO.sub.4, and a method of formation of the dielectric barrier layer by sol gel process is described. The amorphous, mixed oxide barrier layer has excellent dielectric properties up to GHz frequencies, and crystallizes above 800.degree. C., facilitating device processing. In particular, the barrier layer is compatible with lead containing perovskites, including PZT and PLZT ferroelectric dielectrics for example for application in non-volatile memory cells, and high value capacitors for integrated circuits, using silicon or GaAs integrated circuit technologies.

Abstract: A semiconductor device comprises a substrate such as a semiconductor wafer having a major surface, a first conductive layer formed over the major surface, and a second conductive layer formed over the first conductive layer with the first and second conductive layers having a capacitance therebetween. A semiconductor layer is formed over the first and second conductive layer, the semiconductor layer having a diffusion region such as a transistor source, drain, and/or channel. An inventive method for forming the inventive structure comprises the steps of forming a first conductive layer over a substrate and forming a second conductive layer over the first conductive layer. Next, a semiconductor layer is formed over the second conductive layer and a transistor diffusion region, such as a source, drain, and/or channel is formed in the semiconductor layer.

Abstract: A dynamic random access memory device having a ferroelectric thin film perovskite (Ba.sub.1-x Sr.sub.x)TiO.sub.3 layer sandwiched by top and bottom (Ba.sub.1-x Sr.sub.x)RuO.sub.3 electrodes. The memory device is made by a MOCVD process including the steps of providing a semiconductor substrate, heating the substrate, exposing the substrate to precursors including at least Ru(C.sub.5 H.sub.5).sub.2, thereafter exposing the substrate to precursors including at least TiO(C.sub.2 H.sub.5).sub.4 and thereafter exposing the substrate to precursors including at least Ru (C.sub.5 H.sub.5).sub.2.

Abstract: A semiconductor device in which an SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 um) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.

Abstract: An integrated circuit with a capacitor includes a conductive substrate, a layer of field dielectric formed on the conductive substrate, a layer of conductive metal or conductive polycrystalline silicon formed on the field dielectric, and first and second laterally spaced apart layers of conductive material formed on the conductive metal or polycrystalline silicon. Each spaced apart layer preferably includes a layer of titanium nitride disposed over a layer of titanium. A layer of capacitor dielectric is deposited on the first of the spaced apart layers, and metal is deposited over the capacitor dielectric and the second layer of conductive material.

Abstract: An integrated circuit capacitor and method for making the same utilizes a ferroelectric dielectric, such as lead-zirconate-titanate ("PZT"), to produce a high value peripheral capacitor for integration on a common substrate with a ferroelectric memory array also utilizing ferroelectric memory cell capacitors as non-volatile storage elements. The peripheral capacitor is linearly operated in a single direction and may be readily integrated to provide capacitance values on the order of 1-10 nF or more utilizing the same processing steps as are utilized to produce the alternately polarizable memory cell capacitors. The high value peripheral capacitor has application, for example, as a filter capacitor associated with the on-board power supply of a passive radio frequency ("RF") identification ("ID") transponder.

Abstract: A method for creating a MOS-type capacitor structure in function blocks or integrated circuits. Each block or cell is provided with capacitors for decoupling purposes under the board metal supply lines without requiring any extra silicon surface. The buried capacitors can be designed under any board conductor path or on a chip made of a semiconductor material.

Abstract: A thin and flat integrated circuit assembly (10, 40) may be achieved by using a thin carrier (20) with shallow cavities (22, 24) for holding the integrated circuits (16) and/or discrete circuit components (14). The integrated circuits (16) and/or circuit components (14) may be friction fitted in the cavities (22, 24) or they may be secured therein by the use of adhesives and/or solder. Electrical connection between the integrated circuits (16) and circuit components (14) may be done with wire bonding, ribbon bonding, tape-automated bonding, lead frames, flip chip bonding, and/or conductive gluing of leads. The circuit assembly may then be accommodated into a credit card-sized packaging with standard dimensions set by the International Standards Organization.

Abstract: In a dynamic random access memory device including an SOI substrate and a field shield isolation region, a p type impurity region is formed between an n type source/drain region of a transistor coupled to a storage node in a dynamic memory cell and an n type impurity region below a field shield electrode. A reverse bias voltage is supplied respectively between the p and n type impurity regions, and between the n type source/drain region of the transistor and the p type body region. As a result, leakage current from the n type source/drain region to the p type body region is compensated for by the leakage current from the n type impurity region to the p type impurity region.

Abstract: An integrated circuit having a monolithic device such as an inductor suspended over a pit in the substrate to reduce parasitic capacitances and enhance the self-resonant frequency of the inductor.

Abstract: An integrated circuit metal-oxide-metal capacitor and method of making it which involves a support layer; a first conductive electrode on the support layer; a dielectric film on the first conductive electrode; a second conductive electrode disposed on the dielectric film and formed from the first level metallization interconnect layer of the integrated circuit; an interlevel dielectric layer; a first contact via extending through the interlevel dielectric layer and the dielectric film to the first conductive electrode; a second contact via extending through the interlevel dielectric layer to the second conductive electrode; and first and second terminals formed from the second level metallization interconnect layer of the integrated circuit contacting the first and second vias, respectively.

Abstract: A semiconductor memory includes a laminated structure including a first word line in a p-type silicon substrate, a first silicon oxide film on the word line, a bit line, a tunnel oxide film, a storage node of polycrystalline silicon containing impurities, a second silicon oxide film, and a second word line of polycrystalline silicon, wherein the dielectric constant or area of the tunnel oxide film is smaller than the dielectric constant or area of the first silicon oxide film and smaller than the dielectric constant or the area of the second silicon oxide film. With this arrangement, the memory cell structure can be extremely simple. It is possible to reduce the number of production steps and, therefore, it is also possible to improve production yield. The present invention provides a high-density, high-performance, and low cost semiconductor memory.

Abstract: Integrated circuit devices, chips and methods of making and operating them are disclosed. The devices are specially adapted for high frequency operation e.g. at or above 1 GHz. Inductive noise caused by switching at these frequencies--and which can interfere with switching--is inhibited by using a large bypass capacitor connected between power and ground connections outside the chip, and a small bypass capacitor connected between the same power and ground connections but formed inside the chip. The smaller capacitor cuts noise attributable to the wiring between the larger capacitor and the chip. The chip can have many of the smaller capacitors, even one or more per gate. In the preferred embodiments, the small capacitors from power and ground bonding pads are formed at the front surface of the chip substrate. Tantalum pentoxide, and other suitable dielectrics having relative dielectric constant of 10 or more at 1 GHz, are used to form the capacitors.

Abstract: A semiconductor device having a capacitor of a large capacitance in spite of its small area, is composed of a first insulating film formed on a semiconductor substrate, a first polysilicon film, a second insulating film and a second polysilicon film which are formed in that order on the first insulating film. The second polysilicon film is connected to the semiconductor substrate by means of a metal film to function as one electrode while the first polysilicon film functions as the other electrode. The first and second insulating film are each made of a dielectric material.

Abstract: An integrated circuit is formed from a first layer of conductive material (30) which is separated from a second layer of conductive material (39) by a layer of dielectric material (36). The first layer of conductive material (30) is patterned to form a first plate (32, 59) of a capacitor (22, 50, 62, 72). An electrical interconnect (33, 63) is formed within the first plate (32, 59), respectively. A via (37) is formed in the layer of dielectric material (36). A second layer of conductive material (39) is patterned to form a second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72) and a planar spiral inductor (21, 51, 61, 71). The planar spiral inductor (21, 51, 61, 71) is surrounded by the second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72).

Abstract: A semiconductor device comprising a MIS structure comprising a first electrically conductive film formed on an oxide film, a second electrically conductive film formed on at least a part of said first electrically conductive film, an insulator film formed on said second electrically conductive film, and a third electrically conductive film formed on said insulator film; and at least one electrode contact portion formed on said first electrically conductive film. A semiconductor device comprising a MIS capacitor having a diffusion layer inside the semiconductor substrate as a lower electrode with a first electrically conductive type being isolated using another diffusion layer having the opposite conductive type, and said another diffusion layer having the opposite conductive type being further isolated using a diffusion layer for isolation having the first conductive type and which is earthed.

Abstract: On a first conductor layer of a capacitor element of an IC and in contact with a dielectric film made of a particular dielectric material, a first barrier metal film is made of platinum, palladium, tantalum, or titanium nitride. A second barrier metal film is made of a similar material in contact with the dielectric film and on a second conductor layer. The particular dielectric material is either tantalum oxide or a perovskite oxide, such as strontium titanate or a composite of lead zirconate and lead titanate. In cooperation with such a dielectric film, the first and the second barrier metal films make it possible to provide a compact capacitor having a great and reliable capacitance. The capacitor element is manufactured like a conventional one except for use of the particular dielectric material and for manufacturing steps of forming the first and the second barrier metal films and may be an MOS, MIS, or MIM capacitor or a multilayer wired capacitor.

Abstract: A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension.

Abstract: An MIS capacitor for bipolar integrated circuits includes an island region of one conductivity type, a first semiconductor layer of one conductivity type formed in the island region, an insulating layer provided on the first semiconductor layer, a capacitor electrode provided on the insulating layer to provide an MIS capacitor element, and a second semiconductor layer of an opposite conductivity type for providing a PN junction with the first semiconductor layer. When the MIS capacitor element is reverse biased, majority carriers of the second semiconductor layer are supplied to a depletion layer generated in the first semiconductor layer, thereby providing an MIS capacitor having an approximately constant capacitance even if it is biased in a forward or reverse direction.

Abstract: A semiconductor device which has a resistor, a capacitor, and a Schottky diode all formed on a single semiconductor substrate. The capacitor comprises a dielectric region between two metal regions. The resistor comprises an N.sup.+ -type well. The Schottky diode comprises an N-type tub, a metal region in contact with the tub, and an N.sup.+ -type region formed in the N-type tub. The resistor and capacitor are coupled by a metal region which contacts one of the metal regions of the capacitor and the N.sup.+ -type well of the resistor. The resistor and Schottky diode are coupled by a metal region which contacts the N.sup.+ -type well of the resistor and the N.sup.+ -type well of the Schottky diode.

Abstract: A capacitive micro-sensor includes a sandwich of three silicon plates, each surface of the frame region of the central plate being assembled to the opposing surface of each external plate through a thin layer forming an insulating stripe. At least one of the external plates forms a first electrode, and at least one central portion of the central plate forms a variable capacity with at least one of the external plates. The frame region of the central plate is electrically disconnected from the central portion. First contact means are coupled to the frame portion. Second contact means are coupled to the central portion and form a second electrode of the variable capacity.

Abstract: Depletion layer depth and semiconductor real estate occupation area shortcomings of conventional MOS capacitor architectures that are formed on lightly doped semiconductor material are obviated by augmenting the MOS capacitor structure with a pair of opposite conductivity type, high impurity concentration regions, both of which are directly contiguous with the lightly doped lower plate layer that underlies the capacitor's dielectric layer, and connecting both of these auxiliary heavily doped regions to a common capacitor electrode terminal for the lower plate of the capacitor. If a high negative charge is applied to the upper plate overlying the thin dielectric layer, holes are readily supplied by the auxiliary P+ region. Conversely, if a high positive charge be applied to the upper plate, electrons are readily supplied by the auxiliary N+ region. By connecting both the auxiliary N+ and P+ regions together, a deep depletion condition is prevented for either polarity of the applied voltage.

Abstract: A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100). It is possible to form the element areas according to designs, and it is also possible to flatten the surface without wire cutting in the conductive layer.

Abstract: According to the present invention, a lower electrode is formed on a semiconductor substrate and overgrows upward to form one electrode of a capacitor having a mushroom-shaped section. An insulation film is formed so as to at least cover the lower electrode. An upper electrode is formed so as to oppose the lower electrode and to cover at least the insulation film.

Abstract: The invention provides an improved BiCMOS device and a method of fabricating such a BiCMOS device which requires fewer process steps than known fabrication methods. In one embodiment, the invention provides a method of forming an interpoly capacitor in a BiCMOS device which maintains the thickness of the interpoly dielectric in the capacitor while a window is etched for the emitter in a bipolar transistor. The method includes the use of a thin polysilicon layer overlying the oxide layer, which protects the oxide from etching while the emitter window is etched.

Abstract: A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension.

Abstract: A MOS capacitor, with the polysilicon gate level as one plate, the gate oxide as the insulator, and the underlying semiconductor tub region as the other plate, is used to increase electrostatic discharge (ESD) protection. In an illustrative embodiment, wherein the substrate is n-type and the tub is p-type, the polysilicon level is connected to the negative power supply voltage conductor (V.sub.SS), and the underlying semiconductor region is connected to the positive power supply conductor (V.sub.DD). Since the tub region is p-type, an accumulation-type capacitor is formed. Surprisingly, the thin gate oxide is sufficient to withstand the high ESD voltages, with the protection increasing in one design from less than 1000 volts without the capacitor to 2000 volts with the capacitor.

Abstract: A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.

Abstract: Each memory cell of a dynamic random access memory comprises a semiconductor layer of a first conductivity type, one and the other impurity regions of a second conductivity type, a gate electrode, a capacitor impurity region of the first conductivity type, and a capacitor electrode. The semiconductor layer of the first conductivity type comprises a first surface and a second surface located opposite to the first surface. One and the other impurity regions are formed spaced apart from each other in the semiconductor layer so as to define a channel region with a channel surface being a part of the first surface of the semiconductor layer. The gate electrode is formed on the channel surface through a gate insulating film. The capacitor impurity region is formed opposing to the channel region, near the second surface of the semiconductor layer and having a concentration higher than that of the semiconductor layer. The capacitor electrode is formed on the capacitor impurity region through a dielectric film.

Abstract: A method of forming an electrically conductive polysilicon capacitor plate on a semiconductor substrate includes: a) providing a first layer of conductively doped polysilicon atop a semiconductor substrate to a first selected thickness; b) providing a thin layer of oxide atop the first polysilicon layer to a thickness of from about 2 Angstroms to about 30 Angstroms, the thin oxide layer having an outwardly exposed surface; and c) providing a second layer of conductively doped polysilicon having an outer exposed surface over the outwardly exposed thin oxide surface, the first polysilicon layer being electrically conductive with the second polysilicon layer through the thin layer of oxide, the second polysilicon layer having a second thickness from about 500 Angstroms to about 700 Angstroms, the thin oxide layer reducing silicon atom mobility during polysilicon deposition to induce roughness into the outer exposed polysilicon surface.

Abstract: A semiconductor structure having a high precision analog polysilicon capacitor with a self-aligned extrinsic base region of a bipolar transistor is disclosed. The structure is formed by simultaneously forming the dielectric layer of the capacitor with the formation of the base region of the bipolar transistor. A final oxidation step in the formation of the capacitor causes the base region to diffuse to form a self-aligned extrinsic base diffusion region.

Abstract: Liquid cleaning preparations for hard surfaces containing(a) 0.5 to 40% by weight, preferably 5 to 20% by weight, of a surfactant or a surfactant mixture;(b) 0.01 to 1% by weight, preferably 0.05 to 0.5% by weight, of cleaning enhancer;(c) 0 to 6% by weight, preferably 1.0 to 6% by weight, of at least one organic and/or inorganic builder;and up to a total of 100% by wiehgt, based on the total weight, of water, and optionally, one or more of solubilizers (solvents, hydrotropes), preservatives, antimicrobial agents, viscosity regulators, pH regulators, perfumes, and dyes. Component (b) is a mixture of (i) at least one polyacrylamide and (ii) at least one highly polyethoxylated monofunctional or polyfunctional alkanol.