Both Terminals Of Capacitor Isolated From Substrate Patents (Class 257/535)
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Patent number: 7781863Abstract: The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.Type: GrantFiled: January 7, 2008Date of Patent: August 24, 2010Assignee: ROHM Co., Ltd.Inventors: Ryotaro Yagi, Yuichi Nakao, Isamu Nishimura
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Patent number: 7768099Abstract: This invention provides for the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. The method includes forming a damascene interconnect structure and a MIM capacitor damascene structure wherein a diffusion barrier material forms the capacitor electrodes. The method includes forming a MIM capacitor damascene structure through an interlevel dielectric layer and terminating on a diffusion barrier material instead of a conventional dielectric etch stop layer. In alternative embodiments, the integrated damascene MIM capacitor makes up part of semiconductor device such as DRAM memory, CMOS, or a high frequency device.Type: GrantFiled: September 21, 2006Date of Patent: August 3, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Anthony Oates, Carlos H. Diaz
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Patent number: 7755166Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.Type: GrantFiled: March 10, 2009Date of Patent: July 13, 2010Assignee: Ibiden Co., Ltd.Inventor: Takashi Kariya
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Patent number: 7750436Abstract: An electronic device (ICD) comprises an integrated circuit (AIC) and a capacitance element (PIC). The integrated circuit (AIC) is provided with a plurality of circuit contact pairs (CI). The capacitance element (PIC) is provided with a plurality of capacitance contact pairs (CC). A capacitance is present between each of at least part of the capacitance contact pairs (CC). The plurality of capacitance contact pairs (CC) faces the plurality of circuit contact pairs (CI). At least a part of the capacitance contact pairs (CC) is electrically coupled in a pair-by-pair manner to at least a part of the circuit contact pairs (CI).Type: GrantFiled: July 7, 2005Date of Patent: July 6, 2010Assignee: NXP B.V.Inventor: Joop Van Lammeren
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Patent number: 7745869Abstract: A thin film capacitance element composition, wherein a bismuth layer compound having a c-axis oriented vertically with respect to a substrate surface is expressed by a composition formula of (Bi2O2)2+(Am?1BmO3m+1)2? or Bi2Am?1BmO3m+3, wherein “m” is an even number, “A” is at least one element selected from Na, K, Pb, Ba, Sr, Ca and Bi, and “B” is at least one element selected from Fe, Co, Cr, Ga, Ti, Nb, Ta, Sb, V, Mo and W; and Bi in the bismuth layer compound is excessively included with respect to the composition formula of (Bi2O2)2+(Am?1BmO3m+1)2? or Bi2Am?1BmO3m+3, and the excessive content of Bi is in a range of 0<Bi<0.5×m mol in of Bi.Type: GrantFiled: January 16, 2004Date of Patent: June 29, 2010Assignee: TDK CorporationInventor: Yukio Sakashita
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Patent number: 7738226Abstract: Integrated snubber device on a semiconductor basis for wiring an electric network for absorbing electric energy from an electric energy store, of an electric network, including at least two terminals for being connected to the electric network to be wired, an electric resistor structure, and a reactance structure, which are connected between the terminals.Type: GrantFiled: April 3, 2007Date of Patent: June 15, 2010Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.Inventors: Sven Berberich, Martin Maerz
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Patent number: 7737536Abstract: Structures, in various embodiments, are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. In an embodiment, a transmission line is disposed on a first layer of insulating material, where the first layer of insulating has a thickness equal to or less than 1.0 micrometer. The transmission line may be structured with a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is disposed on the transmission line.Type: GrantFiled: July 18, 2006Date of Patent: June 15, 2010Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7732889Abstract: A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.Type: GrantFiled: May 24, 2007Date of Patent: June 8, 2010Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, Sajol Ghoshal
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Patent number: 7700984Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.Type: GrantFiled: May 1, 2006Date of Patent: April 20, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventor: Mikio Yukawa
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Patent number: 7692267Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.Type: GrantFiled: March 10, 2009Date of Patent: April 6, 2010Assignee: Ibiden Co., Ltd.Inventor: Takashi Kariya
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Patent number: 7687885Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.Type: GrantFiled: May 30, 2007Date of Patent: March 30, 2010Assignee: Renesas Technology Corp.Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
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Patent number: 7687867Abstract: A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode.Type: GrantFiled: August 28, 2007Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, William J. Murphy, Vidhya Ramachandran
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Publication number: 20100052099Abstract: This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be directly fabricated on a wafer with low temperature processes so as to be integrated with active devices formed on the wafer. This invention also forms vertical conducting lines in the capacitor devices using the through-silicon-via technology to facilitate the three-dimensional stacking of the capacitor devices.Type: ApplicationFiled: February 3, 2009Publication date: March 4, 2010Applicant: Industrial Technology Research InstituteInventors: Shu-Ming Chang, Chia-Wen Chiang
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Patent number: 7667279Abstract: Disclosed is a semiconductor device which has a circuit-forming region. The semiconductor device has a semiconductor substrate, a plurality of insulating interlayer films, a guard ring, and a first MIM capacitor. The insulating interlayer films, which are stacked one upon another, are provided over the semiconductor substrate. The guard ring is formed in the plurality of insulating interlayer films and surrounds the circuit-forming region. The guard ring is separated from an insulating interlayer film including a topmost interconnect. The MIM capacitor is provided between the guard ring and the insulating interlayer film including the topmost interconnect.Type: GrantFiled: February 1, 2008Date of Patent: February 23, 2010Assignee: NEC Electronics CorporationInventor: Yasutaka Nakashiba
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Patent number: 7659602Abstract: A structure and method of forming a capacitor is described. In one embodiment, the capacitor includes a cylindrical first electrode having an inner portion bounded by a bottom surface and an inner sidewall surface, the first electrode further having an outer sidewall, the first electrode being formed from a conductive material. An insulating fill material is disposed within the inner portion of the first electrode. A capacitor dielectric is disposed adjacent at least a portion of the outer sidewall of the first electrode. A second electrode is disposed adjacent the outer sidewall of the first electrode and separated therefrom by the capacitor dielectric. The second electrode is not formed within the inner portion of the first electrode.Type: GrantFiled: June 2, 2008Date of Patent: February 9, 2010Assignee: Qimonda AGInventors: Stefan Tegen, Klaus Muemmler, Peter Baars, Odo Wunnicke
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Patent number: 7651908Abstract: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode.Type: GrantFiled: February 15, 2007Date of Patent: January 26, 2010Assignee: Samsung Electronic Co., Ltd.Inventors: Gil-Sang Yoo, Byung-Jun Park
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Patent number: 7633138Abstract: The semiconductor device 1 includes an insulating interlayer 10, interconnects 12a to 12c, an insulating interlayer 20, and a capacitor element 30. On the insulating interlayer 10 and the interconnects 12a to 12d, the insulating interlayer 20 is provided via a diffusion barrier 40. On the insulating interlayer 20, the capacitor element 30 is provided. The capacitor element 30 is a MIM type capacitor element, and includes a lower electrode 32 provided on the insulating interlayer 20, a capacitor insulating layer 34 provided on the lower electrode 32, and an upper electrode 36 provided on the capacitor insulating layer 34. The interface S1 between the insulating interlayer 20 and the capacitor element 30 is generally flat. The lower face S2 of the insulating interlayer 20 includes an uneven portion at a position corresponding to the capacitor insulating layer 34.Type: GrantFiled: August 11, 2006Date of Patent: December 15, 2009Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Takeshi Toda
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Publication number: 20090294907Abstract: A structure and method of forming a capacitor is described. In one embodiment, the capacitor includes a cylindrical first electrode having an inner portion bounded by a bottom surface and an inner sidewall surface, the first electrode further having an outer sidewall, the first electrode being formed from a conductive material. An insulating fill material is disposed within the inner portion of the first electrode. A capacitor dielectric is disposed adjacent at least a portion of the outer sidewall of the first electrode. A second electrode is disposed adjacent the outer sidewall of the first electrode and separated therefrom by the capacitor dielectric. The second electrode is not formed within the inner portion of the first electrode.Type: ApplicationFiled: June 2, 2008Publication date: December 3, 2009Inventors: Stefan Tegen, Klaus Muemmler, Peter Baars, Odo Wunnicke
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Patent number: 7619298Abstract: A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.Type: GrantFiled: March 31, 2005Date of Patent: November 17, 2009Assignee: Xilinx, Inc.Inventors: Firas N. Abughazaleh, Brian T. Brunn
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Patent number: 7615423Abstract: An amorphous semiconductor film is etched so that a width of a narrowest portion thereof is 100 ?m or less, thereby forming island semiconductor regions. By irradiating an intense light such as a laser into the island semiconductor regions, photo-annealing is performed to crystallize it. Then, of end portions (peripheral portions) of the island semiconductor regions, at least a portion used to form a channel of a thin film transistor (TFT), or a portion that a gate electrode crosses is etched, so that a region that the distortion is accumulated is removed. By using such semiconductor regions, a TFT is produced.Type: GrantFiled: March 6, 2006Date of Patent: November 10, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Naoto Kusumoto, Shunpei Yamazaki
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Publication number: 20090267187Abstract: An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than the surface area of the insulating material and the surface area of the insulating material is greater than the surface area of the top electrode. The top electrode and the insulating layer have edges that are laterally within and spaced apart from edges of the bottom electrode. A protective layer covers the top electrode, the edges of the top electrode, and the portions of the insulating layer that are uncovered by the top electrode. The protective layer serves as an etch mask during the formation of the bottom electrode.Type: ApplicationFiled: April 23, 2008Publication date: October 29, 2009Inventors: Sallie Hose, Derryl Allman, Peter A. Burke, Ponce Saopraseuth
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Patent number: 7605007Abstract: An upper electrode film includes a first conductive oxidation layer made of an oxide expressed by a chemical formula M1Ox2, a second conductive oxidation layer made of an oxide expressed by a chemical formula M2Oy2 and a third conductive oxidation layer. Here, the second conductive oxidation layer is formed to have a degree of oxidation higher than the first conductive oxidation layer and the third conductive oxidation layer, and among the composition parameters x1, x2, y1, y2, z1 and z2, there are the following relations, y2/y1>x2/x1, y2/y1>z2/z1, and z2/z1?x2/x1.Type: GrantFiled: February 29, 2008Date of Patent: October 20, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Wensheng Wang
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Publication number: 20090256239Abstract: A capacitor is described which includes a substrate with a doped area of the substrate forming a first electrode of a first capacitor. A plurality of trenches is arranged in the doped area of the substrate, the plurality of trenches forming a second electrode of the capacitor. An electrically insulating layer is arranged between each of the plurality of the trenches and the doped area for electrically insulating the trenches from the doped area. At least one substrate contact structure electrically connects the doped area, wherein the doped area comprises first open areas and at least one second open area arranged between neighboring trenches of the plurality of trenches, wherein the at least one open area is arranged below the at least one substrate contact. A shortest first distance between neighboring trenches is separated by the first open areas and is shorter than a shortest second distance between neighboring trenches separated by the at least one second open area.Type: ApplicationFiled: April 14, 2008Publication date: October 15, 2009Inventor: Stefan Pompl
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Patent number: 7602043Abstract: A coupling capacitor and a semiconductor memory device using the same are provided. In an embodiment, each memory cell of the semiconductor memory device includes a coupling capacitor so that a storage capacitor can store at least 2 bits of data. The coupling capacitor has a capacitance having a predetermined ratio with respect to the capacitance of the storage capacitor. For this, the coupling capacitor is formed by substantially the same fabrication process as the storage capacitor. The predetermined ratio is obtained by choosing an appropriate number of individual capacitors, each with the same capacitance of the storage capacitor, to comprise the coupling capacitor. Also, the coupling capacitor is disposed on an interlayer insulating layer that buries a bit line in a cell region and a sense amplifier in a sense amplifier region.Type: GrantFiled: July 31, 2006Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Cheol Lee, Won-Suk Yang, Jin-Woo Lee, Tae-Young Chung
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Patent number: 7589394Abstract: An interposer is constructed with a substrate body having first and second through-holes, a capacitor formed by a laminating dielectric layer and a second electrode portion on a first electrode portion, which is structured on inner surfaces of first and second through-holes and on the first surface of the substrate body. An insulation layer is formed by filling insulation material in the space within the first through-hole surrounded by second electrode portion, and a first post passes through the insulation layer, one end being electrically connected to the first electrode portion, while the first post is electrically insulated from the second electrode portion. Furthermore, a second post is formed in the second through-hole, and is connected to the second electrode portion at its peripheral surface while being electrically insulated from the first electrode portion.Type: GrantFiled: January 4, 2008Date of Patent: September 15, 2009Assignee: Ibiden Co., Ltd.Inventor: Shuichi Kawano
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Patent number: 7573112Abstract: A magnetic sensor comprises a plurality of layers including a substrate having circuitry, at least one conductive layer to interconnect the circuitry, and an insulator layer to electrically insulate the at least one conductive layer. First and second conductive layers are disposed above the substrate with a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor. A first terminal is electrically connected to the first conductive layer and a second terminal is electrically connected to the second conductive layer.Type: GrantFiled: April 14, 2006Date of Patent: August 11, 2009Assignee: Allegro Microsystems, Inc.Inventor: William P. Taylor
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Patent number: 7573086Abstract: A capacitor is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor generally comprises a top conductive plate, a capacitor dielectric and a bottom conductive plate that respectively comprise a patterned layer of tantalum nitride TaN, a layer of a nitride based material and a layer of patterned polysilicon.Type: GrantFiled: August 26, 2005Date of Patent: August 11, 2009Assignee: Texas Instruments IncorporatedInventors: Michael LeRoy Huber, Gregory Lee Hendy, Evelyn Anne Lafferty, George Nicholas Harakas, Salvatore Frank Pavone, Blake Ryan Pasker, Courtney Michael Hazelton, James Wayne Klawinsky
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Patent number: 7564116Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.Type: GrantFiled: January 18, 2008Date of Patent: July 21, 2009Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jin Yong Ahn, Cheol Seong Hwang, Sung Kun Kim, Chang Sup Ryu, Suk-Hyeon Cho, Ho Sik Jeon
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Patent number: 7560796Abstract: In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.Type: GrantFiled: December 6, 2006Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Seok Shin, Hee-Cheol Choi, Seung-Hoon Lee, Kyung-Hoon Lee, Young-Jae Cho
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Patent number: 7557426Abstract: A semiconductor component including an integrated capacitor structure having at least two groups of at least partly electrically conductive planes and which is patterned in such a way that in at least each group of planes at least one plane has a plurality of strip elements, first strip elements including a first polarity of the capacitor structure and second strip elements including a second polarity of the capacitor structure, the first strip elements together with second strip elements being at least partly interlinked in one another and strip elements of the same polarity at least partly overlapping in at least two planes, the first group of planes being electrically conductively connected by way of vertical connections (vias) to strip elements of the same polarity of the second group of planes, the strip elements of the same polarity of the second group of planes being interconnected with lateral connecting elements.Type: GrantFiled: September 29, 2006Date of Patent: July 7, 2009Assignee: Infineon Technologies AGInventors: Peter Baumgartner, Phillip Riess
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Patent number: 7557427Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: GrantFiled: August 27, 2007Date of Patent: July 7, 2009Assignees: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Publication number: 20090146257Abstract: A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and a fourth electrode, at least one first contact pad on a side of the first electrode, and a wiring structure connecting the at least one first contact pad and the fourth electrode.Type: ApplicationFiled: December 5, 2008Publication date: June 11, 2009Inventor: Kwan-Young Yun
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Patent number: 7535080Abstract: A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.Type: GrantFiled: June 30, 2005Date of Patent: May 19, 2009Assignee: Intel CorporationInventors: Xiang Yin Zeng, Jiangqi He, BaoShu Xu
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Patent number: 7525175Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.Type: GrantFiled: January 30, 2006Date of Patent: April 28, 2009Assignee: Ibiden Co., Ltd.Inventor: Takashi Kariya
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Patent number: 7521330Abstract: A method for forming a capacitor includes forming a dielectric layer over a substrate. A conductive layer is formed over the dielectric layer. Dopants are implanted through at least one of the dielectric layer and the conductive layer after forming the dielectric layer so as to form a conductive region under the dielectric layer, wherein the conductive layer is a top electrode of the capacitor and the conductive region is a bottom electrode of the capacitor.Type: GrantFiled: June 4, 2007Date of Patent: April 21, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun Chieh Wu, Chi-Feng Huang, Chun-Hung Chen, Chih-Ping Chao, John Chern
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Patent number: 7521745Abstract: A bottom electrode (52) made of Ir, an initial layer (53), a core layer (54) and a termination layer (55) of a PZT film, and a top electrode (56) made of IrO2, are formed on an underlining film (51). The initial layer (53) is formed in a low oxygen partial pressure with a thickness of 5 nm. The thickness of the core layer (54) is set to 120 nm. The termination layer (55) is set to be an excess Zr layer. In other words, as for the composition of the termination layer (55), “Zr/(Zr+Ti)” is set to be larger than 0.5, and in the termination layer (55) Zr is contained more excessively than the morphotropic phase boundary composition.Type: GrantFiled: October 13, 2006Date of Patent: April 21, 2009Assignee: Fujitsu LimitedInventors: Shigeyoshi Umemiya, Osamu Matsuura
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Patent number: 7504706Abstract: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.Type: GrantFiled: August 31, 2006Date of Patent: March 17, 2009Assignee: E. I. Du Pont De NemoursInventors: Madhavan Swaminathan, Ege Engin, Lixi Wan, Prathap Muthana
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Patent number: 7485915Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.Type: GrantFiled: May 5, 2006Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hayato Nasu, Takamasa Usui, Hideki Shibata
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Publication number: 20090014835Abstract: A semiconductor device includes a first wiring layer which is provided above a semiconductor substrate and includes a first insulating film and a wiring buried in the first insulating film, a second insulating film provided above the first wiring layer, a third insulating film provided on the second insulating film, and a capacitor element provided on the third insulating film. The wiring includes an upper surface having a protruding portion. The capacitor element includes a lower electrode provided on the third insulating film, a capacitor insulating film provided on the lower electrode, and an upper electrode provided on the capacitor insulating film.Type: ApplicationFiled: July 8, 2008Publication date: January 15, 2009Applicant: NEC Electronics CorporationInventors: Masayuki Furumiya, Takeshi Toda
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Patent number: 7473652Abstract: Organic polymers for use in electronic devices, wherein the polymer includes repeat units of the formula: wherein: each R1 is independently H, an aryl group, Cl, Br, I, or an organic group that includes a crosslinkable group; each R2 is independently H, an aryl group or R4; each R3 is independently H or methyl; each R5 is independently an alkyl group, a halogen, or R4; each R4 is independently an organic group that includes at least one CN group and has a molecular weight of about 30 to about 200 per CN group; and n=0-3; with the proviso that at least one repeat unit in the polymer includes an R4. These polymers are useful in electronic devices such as organic thin film transistors.Type: GrantFiled: June 30, 2006Date of Patent: January 6, 2009Assignee: 3M Innovative Properties CompanyInventors: Feng Bai, Todd D. Jones, Kevin M. Lewandowski, Tzu-Chen Lee, Dawn V. Muyres, Tommie W. Kelley
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Patent number: 7473981Abstract: An electronic component includes a substrate, a capacitor, and a wiring. The capacitor has a multilayer structure including a first electrode film provided on the substrate, a second electrode film of 2 to 4 ?m in thickness disposed to face the first electrode film, and a dielectric film interposed between the first and the second electrode film. The wiring includes a joint portion connected to the second electrode film, on the opposite side of the dielectric film.Type: GrantFiled: October 18, 2006Date of Patent: January 6, 2009Assignee: Fujitsu LimitedInventors: Tsuyoshi Matsumoto, Yoshihiro Mizuno, Xiaoyu Mi, Hisao Okuda, Satoshi Ueda
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Patent number: 7473948Abstract: A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C1 corresponding to a peak of the impurity concentration in the first impurity region, a concentration C2 corresponding to a peak of the impurity concentration in the second impurity region and a concentration C3 corresponding to a peak of the impurity concentration in the third impurity region satisfy the following relationship: C2<C3<C1.Type: GrantFiled: November 16, 2007Date of Patent: January 6, 2009Assignee: Canon Kabushiki KaishaInventors: Hiroshi Yuzurihara, Ryuichi Mishima, Takanori Watanabe, Takeshi Ichikawa, Seiichi Tamura
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Patent number: 7456459Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.Type: GrantFiled: September 6, 2006Date of Patent: November 25, 2008Assignee: Georgia Tech Research CorporationInventor: Lixi Wan
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Patent number: 7446390Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: GrantFiled: August 27, 2007Date of Patent: November 4, 2008Assignees: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Publication number: 20080258196Abstract: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.Type: ApplicationFiled: January 28, 2008Publication date: October 23, 2008Applicant: AU OPTRONICS CORP.Inventor: Yu-Cheng Chen
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Publication number: 20080258262Abstract: A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above the semiconductor substrate and connected to the multilevel wiring structure. The pad electrode structure includes pad wiring patterns and pad via conductors interconnecting the pad wiring patterns, the uppermost pad wiring pattern includes a pad pattern and a sealing pattern surrounding the pad pattern in a loop shape. Another pad wiring pattern has continuous extended pad pattern of a size overlapping the sealing pattern. The pad via conductors include a plurality of columnar via conductors disposed in register with the pad pattern and a loop-shaped wall portion disposed in register with the sealing pattern.Type: ApplicationFiled: June 27, 2008Publication date: October 23, 2008Applicant: FUJITSU LIMITEDInventor: Kouichi Nagai
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Publication number: 20080217739Abstract: The present invention relates to a semiconductor packaging substrate structure with a capacitor embedded therein, which includes an inner circuit board, a patterned buffer layer, a high dielectric material layer, and a patterned metal layer. The buffer layer is disposed on at least one surface of the inner circuit board to expose the inner electrode layer of the internal board. The high dielectric material layer is located on the buffer layer and the inner electrode layer. The metal layer is placed on the high dielectric material layer including an outer circuit layer capable of electrical connection to the inner circuit layer, and an outer electrode layer corresponding to the inner electrode layer to form a capacitor. Owing to the assistance of the buffer layer, the structure can enhance the transmission and the quality of the products.Type: ApplicationFiled: May 19, 2008Publication date: September 11, 2008Applicant: Phoenix Precision Technology CorporationInventors: Chung-Cheng Lien, Chih-Kui Yang
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Publication number: 20080203531Abstract: In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.Type: ApplicationFiled: February 1, 2008Publication date: August 28, 2008Inventors: Toshinori Imai, Tsuyoshi Fujiwara, Hiroshi Ashihara, Akira Ootaguro, Yoshihiro Kawasaki
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Publication number: 20080185685Abstract: Disclosed is a semiconductor device which has a circuit-forming region. The semiconductor device has a semiconductor substrate, a plurality of insulating interlayer films, a guard ring, and a first MIM capacitor. The insulating interlayer films, which are stacked one upon another, are provided over the semiconductor substrate. The guard ring is formed in the plurality of insulating interlayer films and surrounds the circuit-forming region. The guard ring is separated from an insulating interlayer film including a topmost interconnect. The MIM capacitor is provided between the guard ring and the insulating interlayer film including the topmost interconnect.Type: ApplicationFiled: February 1, 2008Publication date: August 7, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Yasutaka NAKASHIBA
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Patent number: 7407897Abstract: In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.Type: GrantFiled: July 1, 2005Date of Patent: August 5, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-jun Won, Yong-kuk Jeong, Dae-jin Kwon, Min-woo Song, Weon-hong Kim