Abstract: A semiconductor body (100) has a first device region (20) of one conductivity type forming with a second device region (13) of the opposite conductivity type provided adjacent one major surface (11) of the semiconductor body (100) a first pn junction (40) which is reverse-biassed in at least one mode of operation. A floating further region (50) of the opposite conductivity type is provided within the first device region (20) remote from the major surfaces (11 and 12) of the semiconductor body (100) and spaced from the second device region (13) so that, in the one mode, the depletion region of the first pn junction (40) reaches the floating further region (50) before the first pn junction (40) breaks down.

Abstract: Buried layers of a second conductivity type are formed in a plurality of portions of a surface region of a semiconductor substrate of a first conductivity type, and an epitaxial layer of the first conductivity type is formed on the buried layers and the semiconductor substrate. A plurality of well regions of the second conductivity type are formed in the epitaxial layer in contact with the buried layers, and a region of the second conductivity type with a high impurity concentration is formed in one of the well regions in contact with the buried layers. A field insulating layer is formed on a surface region of the semiconductor substrate between the well regions. An impurity is ion-implanted in a portion substantially immediately below the field insulating film a plurality of times to form inversion preventing layers of the first conductivity type having a plurality of impurity concentration peaks. Active elements are formed in the epitaxial layer of the first conductivity type and the well regions.

Abstract: A process for fabricating a Bi-CMOS integrated circuit according to the present invention comprises the steps of growing a P-type epitaxial layer after formation of buried layers, forming N-type diffusion layers in the epitaxial layer for forming the P-channel MOS transistor, an NPN transistor and a PNP transistor.

Abstract: In one embodiment of the invention, a P buried region is formed in an N epitaxial layer and isolated from a P substrate by an N buried region. P+ emitters and P+ collectors are formed in the surface of the N epitaxial layer (acting as a base). The P buried region acts as a catch diffusion for minority hole carriers injected into the epitaxial layer by the surface emitters that escape collection by the surface P+ collectors and which would otherwise be injected into the substrate. The N buried region effectively isolates the P buried region from the P substrate and further blocks any minority carriers from being injected into the substrate. The P buried region also prevents the formation of a parasitic PNP transistor to the substrate of the integrated device. This further reduces substrate current and thus further reduces the possibility of noise and latchup.