With Contacts Of Refractory Material (e.g., Polysilicon, Silicide Of Refractory Or Platinum Group Metal) Patents (Class 257/576)
  • Patent number: 10446516
    Abstract: A semiconductor package structure is disclosed. The semiconductor package structure comprises a plurality of layered structures, a plurality of wires, and a first ring structure. The wires are connected to each of the layered structures. The first ring structure is coupled to at least one of the layered structures and positioned between the wires.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: October 15, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ping-Yuan Deng, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 8916952
    Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, David L. Harame, Russell T. Herrin, Qizhi Liu
  • Patent number: 8907453
    Abstract: A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 9, 2014
    Assignee: Shanghai Hua Nec Electronics Co., Ltd.
    Inventors: Fan Chen, Xiongbin Chen, Kai Xue, Keran Xue, Jia Pan, Hao Li, Ying Cai, Xi Chen
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Patent number: 8901626
    Abstract: A field effect transistor device includes a gate stack disposed on a substrate a first contact portion disposed on a first distal end of the gate stack, a second contact portion disposed on a second distal end of the gate stack, the first contact portion disposed a distance (d) from the second contact portion, and a third contact portion having a width (w) disposed in a source region of the device, the distance (d) is greater than the width (w).
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Wilfried E. Haensch, Xinhui Wang, Keith Kwong Hon Wong
  • Patent number: 8890163
    Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Jong-Ki Jung
  • Patent number: 8786027
    Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 22, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 8754483
    Abstract: Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang
  • Patent number: 8685809
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Patent number: 8642421
    Abstract: A light-emitting diode (LED) structure fabricated with a SixNy layer responsible for providing increased light extraction out of a surface of the LED is provided. Such LED structures fabricated with a SixNy layer may have increased luminous efficiency when compared to conventional LED structures fabricated without a SixNy layer. Methods for creating such LED structures are also provided.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: February 4, 2014
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventor: Chuong Anh Tran
  • Patent number: 8513765
    Abstract: A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8513122
    Abstract: A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Viorel C. Ontalus, Ahmet S. Ozcan
  • Patent number: 8482076
    Abstract: A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Viorel C. Ontalus, Ahmet S. Ozcan
  • Patent number: 8466555
    Abstract: A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 18, 2013
    Assignee: Raytheon Company
    Inventors: Ram V. Chelakara, Thomas E. Kazior, Jeffrey R. LaRoche
  • Patent number: 8334574
    Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Se-Keun Park
  • Patent number: 8310027
    Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: November 13, 2012
    Assignee: Infineon Technologies AG
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Patent number: 8304819
    Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating layer connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Ki Jung
  • Patent number: 8299455
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Patent number: 8269313
    Abstract: A bipolar transistor at least includes a semiconductor substrate including an N? epitaxial growth layer and a P? silicon substrate, an N+ polysilicon layer, a tungsten layer, two silicide layers, a base electrode, an emitter electrode, and a collector electrode. The N+ polysilicon layer formed on the semiconductor substrate is covered with one of the silicide layers. The tungsten layer that is formed on the silicide layer is covered with the other silicide layer.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Akio Matsuoka
  • Patent number: 8039378
    Abstract: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. Subsequently, after removing the unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of the first thermal treatment is set to 10° C./s or more (for example, 30 to 250° C.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 8030779
    Abstract: A multi-layered metal interconnection includes a diffusion barrier directly formed on a conductive layer, an etching stop layer directly formed on the diffusion barrier, at least one dielectric layer formed over the etch stop layer, at least one of a via formed in the at least one dielectric layer and a trench formed in the at least one dielectric layer.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: October 4, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hyuk Park
  • Patent number: 7790580
    Abstract: The invention provides a method for forming thin film transistors including a polycrystalline semiconducting film. The method comprises depositing a first layer of amorphous semiconducting thin film on to a substrate; depositing a second layer of thin film on to the first layer of amorphous semiconducting thin film; patterning the second layer of thin film so that the first layer of amorphous semiconducting thin film is exposed at selected locations; exposing the first and second layers of thin film to a nickel containing compound in either a solution or a vapor phase; removing the second layer of thin film; and annealing the first layer of amorphous semiconducting thin film at an elevated temperature so the first layer of amorphous semiconducting thin film converts into a polycrystalline semiconducting thin film.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: September 7, 2010
    Assignee: Hong Kong University of Science and Technology
    Inventors: Hoi Sing Kwok, Man Wong, Zhiguo Meng, Shuyun Zhao, Chunya Wu
  • Patent number: 7737512
    Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-myeong Jang, Gyo-young Jin, Yong-chul Oh, Hyun-chang Kim
  • Patent number: 7719031
    Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: May 18, 2010
    Assignee: Panasonic Corporation
    Inventors: Tohru Saitoh, Takahiro Kawashima, Ken Idota, Yoshihiko Kanzawa, Teruhito Ohnishi
  • Patent number: 7679164
    Abstract: Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: March 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Francois Pagette, Christian Lavoie, Anna Topol
  • Patent number: 7666787
    Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Shom Ponoth
  • Patent number: 7629646
    Abstract: A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced trench gate. An epitaxial layer with a plurality of trenches is provided and a gate oxide layer is covered the sidewalls and bottoms of the trenches. A polysilicon layer is filled in the trenches, wherein the polysilicon layer is higher than the sidewalls of the trenches to be used as a gate of the MOSFET. A plurality of sources and bodies are formed in the epitaxial layer, and the bodies at both sides of the trenches. An insulating layer is covered on the substrate, wherein a plurality of metal contact windows are provided. Metal plugs are filled in the metal contact windows to form metal connections for the MOSFET.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: December 8, 2009
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7579285
    Abstract: The invention is related to an ALD method for depositing a layer including the steps of a) providing a semiconductor substrate in a reactor; b) providing a pulse of a first precursor gas into the reactor; c) providing a pulse of a second precursor gas into the reactor; d) providing an inert atmosphere in the reactor; and e) repeating step b) through step d), wherein at least once during step d) the semiconductor substrate is exposed to UV irradiation.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: August 25, 2009
    Assignee: IMEC
    Inventors: Paul Zimmerman, Matty Caymax, Stefan De Gendt, Annelies Delabie, Lars-Ake Ragnarsson
  • Patent number: 7569911
    Abstract: An ohmic electrode is formed by stacking a lower Ti layer, a diffusion preventing layer, an upper Ti layers and a metallic (Au) layer on a p-type GaAs layer. The diffusion preventing layer includes tantalum (Ta) or niobium (Nb). Thus, interdiffusion of Ga and As in the p-type GaAs layer and Au in the metallic layer can be prevented, and variation in resistivity of the ohmic electrode in a high-temperature, high-humidity environment can be suppressed.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: August 4, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiko Shiga, Hitoshi Nakamura, Junji Tanimura
  • Patent number: 7541249
    Abstract: A process for producing a base connection of a bipolar transistor is provided. The process includes the steps of providing a semiconductor structure that can include a three-dimensional sacrificial structure that is selectively removable with respect to adjacent regions. A first semiconductor layer and a second layer of dielectric material is deposited. The first semiconductor layer is partially exposed by partial removal of the second layer. A first reaction layer is deposited that, together with the first semiconductor layer forms reaction products, which are selectively removable with respect to adjacent regions. Remaining material of the first reaction layer that has not reacted with the material of the first semiconductor layer is removed. A second reaction layer is deposited that, with the first semiconductor layer, forms a low-resistivity compound. Remaining material of the second reaction layer that has not reacted with the material of the first semiconductor layer is removed.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: June 2, 2009
    Assignee: Atmel Germany GmbH
    Inventor: Christoph Bromberger
  • Patent number: 7459755
    Abstract: A scalable semiconductor device is formed using control gates formed on opposite sides of a semiconductor layer. A first control gate is formed electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, such that, when a first voltage is applied on the first control gate, a first depletion region is formed in the semiconductor layer opposite the first control gate. A second control gate and a third control gate are also formed, each isolated from the semiconductor region by a second dielectric layer formed on a second surface of the semiconductor layer opposite the first surface.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: December 2, 2008
    Inventor: Andrew J. Walker
  • Patent number: 7239009
    Abstract: A lead frame structure includes: at least a die pad for mounting a semiconductor chip thereon; a plurality of suspension members mechanically connected with the die pad; and a plurality of supporting members. Each supporting member has a connection region mechanically connected with each of the plurality of suspension members for mechanically supporting the at least die pad via the plurality of suspension pins. The connection region of the supporting member has a penetrating opening portion which provides a mechanical flexibility to the connection region and which allows the connection region to be deformed toward the suspension member upon application of a tensile stress to the suspension member in a down-set process.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: July 3, 2007
    Assignee: NEC Corporation
    Inventor: Toshinori Kiyohara
  • Patent number: 7199038
    Abstract: According to an aspect of the invention, there is provided a method for fabricating a semiconductor device. The method may include forming at least one interconnection layer having a low dielectric constant insulating film and an interconnection buried in the low dielectric constant insulating film, forming a trench or a hole extending in the interconnection layer, performing heat treatment for the interconnection layer having the trench or the hole, and burying a material in the trench or the hole.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: April 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideshi Miyajima
  • Patent number: 7109567
    Abstract: The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a third connection conductor (4, 5, 6), while the bandgap of the base region (2) is lower than that of the collector region (3) or of the emitter region (1), for example owing to the use of a silicon-germanium alloy instead of pure silicon. Such a device is very fast, but its transistor shows a relatively low BVceo. In a device according to the invention, the emitter region (1) or the base region (2) comprises a sub-region (1B, 2B) with a reduced doping concentration, which sub-region (1B, 2B) is provided with a further connection conductor (4B, 5B) which forms a Schottky junction with the sub-region (1B, 2B). Such a device results in a transistor with a particularly high cut-off frequency fT but with no or hardly any reduction of the BVceo.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: September 19, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Raymond Josephus Engelbart Hueting, Jan Willem Slotboom, Leon Cornelis Maria Van Den Oever
  • Patent number: 7064417
    Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: June 20, 2006
    Assignee: Sony Corporation
    Inventor: Chihiro Arai
  • Patent number: 6979884
    Abstract: The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: David C. Ahlgren, Gregory G. Freeman, Marwan H. Khater, Richard P. Volant
  • Patent number: 6949806
    Abstract: The present disclosure provides a deep submicron electrostatic discharge (ESD) protection structure for a deep submicron integrated circuit (IC) and a method for forming such a structure. The structure includes at least two electrodes separated by a dielectric material, such as a thin gate oxide layer. In some examples, the thin gate oxide may be less than 25 ? thick. A source and drain are positioned proximate to and on opposite sides of one of the electrodes to form a channel. The drain is covered with a silicide layer that enhances the ESD protection provided by the structure. The source may also be covered with a silicide layer. In some examples, the drain may be floating.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: September 27, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsun Wu, Jian-Hsin Lee, Tongchern Ong
  • Patent number: 6919615
    Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: July 19, 2005
    Assignee: Sony Corporation
    Inventor: Hirokazu Ejiri
  • Patent number: 6897545
    Abstract: The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator area 20. An intrinsic collector region is situated in the bulk separator area 20 in contact with the extrinsic collector region. An intrinsic base region 100 is formed which is thinner laterally than vertically and in contact with the intrinsic collector region and in contact with the emitter region through bearing on a vertical flank of the first isolating well facing a vertical flank of the second isolating well. An extrinsic base region 60 is formed which is substantially perpendicular to the intrinsic base region in the top part of the bulk separator area, and contact terminals C, B, E respectively in contact with the extrinsic collector region, the extrinsic base region, and the emitter region.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: May 24, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Olivier Menut, Herve Jaouen
  • Patent number: 6787880
    Abstract: A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: September 7, 2004
    Assignee: Nano Silicon Pte. Ltd.
    Inventors: David Hu, Jun Cai
  • Patent number: 6744105
    Abstract: A core memory array having a plurality of charge trapping dielectric memory devices. The core memory array can include a substrate having a first semiconductor bit line and a second semiconductor bit line formed therein and a body region interposed between the first and the second bit lines. Over the body region can be formed a first dielectric layer disposed, a dielectric charge trapping layer and a second dielectric layer. At least one word line can be disposed over the second dielectric layer, which defines a channel within the body region. Each bit line can include a bit line contact assembly having a locally metalized portion of the bit line and a conductive via traversing a dielectric region.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: June 1, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Cinti Xiaohua Chen, Hiroyuki Kinoshita, Jeff P. Erhardt, Weidong Qian, Jean Yee-Mei Yang
  • Patent number: 6737710
    Abstract: A MOSFET includes a double silicided source/drain structure wherein the source/drain terminals include a silicided source/drain extension, a deep silicided source/drain region, and a doped semiconductor portion that surrounds a portion of the source/drain structure such that the suicides are isolated from the MOSFET body node. In a further aspect of the present invention, a barrier layer is formed around a gate electrode to prevent electrical shorts between a silicided source/drain extension and the gate electrode. A deep source/drain is then formed, self-aligned to sidewall spacers that are formed subsequent to the silicidation of the source/drain extension.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: May 18, 2004
    Assignee: Intel Corporation
    Inventors: Peng Cheng, Brian Doyle, Gang Bai
  • Patent number: 6594172
    Abstract: The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: July 15, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Todd Abbott, Jigish D. Trivedi, Mike Violette, Chuck Dennison
  • Patent number: 6589833
    Abstract: A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: July 8, 2003
    Assignee: Nano Silicon Pte Ltd.
    Inventors: David Hu, Jun Cai
  • Patent number: 6576973
    Abstract: A vertical Schottky diode including an N-type silicon carbide layer of low doping level formed by epitaxy on a silicon carbide substrate of high doping level. The periphery of the active area of the diode is coated with a P-type epitaxial silicon carbide layer. A trench crosses the P-type epitaxial layer and penetrates into at least a portion of the height of the N-type epitaxial layer beyond the periphery of the active area. The doping level of the P-type epitaxial layer is chosen so that, for the maximum voltage that the diode is likely to be subjected to, the equipotential surfaces corresponding to approximately ¼ to ¾ of the maximum voltage extend up to the trench.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: June 10, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Emmanuel Collard, André Lhorte
  • Patent number: 6570240
    Abstract: In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is formed by filling a trench reaching a buried oxide film in an SOI substrate with an electrically conductive film is utilized for an emitter and/or a collector, whereby a bipolar transistor is formed through a simple process.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: May 27, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takasumi Ohyanagi, Atsuo Watanabe
  • Patent number: 6495904
    Abstract: A bipolar transistor structure that includes a semiconductor material substrate that has a bottom substrate and base region of a first conductivity type and a buried layer, collector region and sink region of a second conductivity type. The substrate has an extrinsic base region of the first conductivity type and an emitter region of the second conductivity type, both of which extend from the substrate's upper surface into the base region. The bipolar transistor structure also includes a single patterned polysilicon layer with a first polysilicon portion of the first conductivity type in contact with the extrinsic base region and a second polysilicon portion of the second conductivity type in contact with the emitter region. The bipolar transistor structure is compact since contact to the extrinsic base region is made by the first polysilicon portion, which can be formed to a minimum dimension and self-aligned to the extrinsic base region.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: December 17, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Vassili Kitch
  • Patent number: 6476506
    Abstract: A semiconductor die has three rows or more of bond pads with minimum pitch. The die is mounted on a package substrate having three rows or more of bond fingers and/or conductive rings. The bond pads on the outermost part of the die (nearest the perimeter of the die) are connected by a relatively lower height wire achieved by reverse stitching to the innermost ring(s) or row (farthest from the perimeter of the package substrate) of bond fingers. The innermost row of bond pads is connected by a relatively higher height wire achieved by ball bond to wedge bond to the outermost row of the bond fingers. The intermediate row of bond pads is connected by relatively intermediate height wire by ball bond to wedge bond to the intermediate row of bond fingers. The varying height wire allows for tightly packed bond pads. The structure is adaptable for stacked die.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: November 5, 2002
    Assignee: Motorola, Inc.
    Inventors: Shawn M. O'Connor, Mark Allen Gerber, Jean Desiree Miller
  • Patent number: 6441462
    Abstract: A semiconductor bipolar transistor structure having improved electrostatic discharge (ESD) robustness is provided as well as a method of fabricating the same. Specifically, the inventive semiconductor structure a semiconductor structure comprises a bipolar transistor comprising a lightly doped intrinsic base; a heavily doped extrinsic base adjacent to said intrinsic base, a heavily doped/lightly doped base doping transition edge therebetween, said heavily doped/lightly doped base doping transition edge defined by an edge of a window; and a silicide region extending on said extrinsic base, wherein said silicide region is completely outside said window.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Louis D. Lanzerotti, Steven H. Voldman
  • Publication number: 20020109230
    Abstract: A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling ions such as carbon are implanted into all contacts of the substrate. High resistive contacts are temporarily covered with an oxide during processing to prevent silicide from forming due to interaction between a siliciding metal and the implanted mobility spoiling ions in the contacts. The resulting high resistance contacts have highly linear I-V curves, even at high voltages. Selective silicide formation converts some of the contacts back to low resistance contacts as a result of interaction between a siliciding metal and the implanted mobility spoiling ions in the low resistance contacts.
    Type: Application
    Filed: April 12, 2002
    Publication date: August 15, 2002
    Inventors: Dustin A. Woodbury, Joseph A. Czagas