Abstract: A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling ions such as carbon are implanted into all contacts of the substrate. High resistive contacts are temporarily covered with an oxide during processing to prevent silicide from forming due to interaction between a siliciding metal and the implanted mobility spoiling ions in the contacts. The resulting high resistance contacts have highly linear I-V curves, even at high voltages. Selective silicide formation converts some of the contacts back to low resistance contacts as a result of interaction between a siliciding metal and the implanted mobility spoiling ions in the low resistance contacts.

Abstract: A semiconductor circuit or a semiconductor device has the current-voltage characteristic that, in a blocking-state of the semiconductor circuit or the semiconductor device, a current gently flows for values of a voltage equal to or greater than a first voltage value but equal to or smaller than a second voltage value, whereas a current abruptly flows for values of a voltage greater than the second voltage value. Due to the current-voltage characteristic, energy accumulated in an inductance provided within the circuit is consumed by a differential resistance of the semiconductor circuit or a semiconductor, thereby preventing the occurrence of the electromagnetic noise and an excessively large voltage.

Abstract: A graded cap layer that reduces the overall height of a layer stack and provides for increased process control during subsequent patterning of the layer stack, is described with a method of making the same. The graded cap layer is configured to function as a cap layer to prevent an underlying silicide layer from lifting, a barrier layer to prevent the underlying silicide layer from being oxidized during subsequent processes, a stop layer to prevent over-etching during subsequent self-aligned source (SAS) patterning processes, and/or an anti-reflective coating (ARC) to improve the resolution of subsequent patterning processes. The graded cap layer is a relatively thin layer of silicon oxynitride with varying concentrations of nitrogen. The cap layer is deposited in a single chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) chamber.

Abstract: A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-type implantation is made on the entire substrate outside the N-type tub except in the region in which the zone extends.

Abstract: A semiconductor device with a reduced insulating capacitance between an emitter electrode and a base layer, and a manufacturing method thereof are disclosed. In the semiconductor device, at least first and second insulating layers are interposed between the emitter electrode and the base layer. Preferably, the first insulating layer, a semiconductor layer having insulation characteristics, and the second insulating layer are interposed between the emitter electrode and the base layer.

Abstract: A lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other NPN bipolar devices capable of being operated at high frequencies. The PNP device is incorporated to an electrically insulated multilayer structure which comprises a semiconductor substrate, doped for conductivity of the P-type, a first buried layer, doped for conductivity of the N-type to provide a base region, and a second layer, overlying the first and having conductivity of the N-type, to provide an active area distinguishable by a P-doped emitter region within the active area being located peripherally and oppositely from a P-doped collector region. The lateral PNP device can be operated at high frequencies with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.

Abstract: A first metal silicide film is formed on an exposed silicon region of a substrate on which the silicon region and an insulating region are exposed. A metal film is deposited over the whole surface of the substrate covering the first metal silicide film, the metal film capable of being silicidized. A silicon film is deposited on the surface of the metal film. The silicon film and metal film are patterned to form a lamination pattern of the silicon film and metal film continuously extending from a partial area of the exposed silicon region to a partial area of the insulating region. The lamination pattern is heated to establish a silicidation reaction and form a second metal silicide layer.

Abstract: An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ("FOX"), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN3 in the Figures illustrating the invention). Because both silicide and heavy implant p+ implant is present at the base contact point only, the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base implant close to the emitter of the upside down NPN transistor in the integrated logic device. The area of the base and the area of the collectors is decoupled, i.e.

Abstract: A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g.

Abstract: There is disclosed an active matrix liquid crystal display comprising pixels having an improved aperture ratio. A metallization layer makes contact with an active layer through openings. Inside the openings, the active layer is patterned into the same geometry as the metallization layer. That is, the active layer is patterned in a self-aligned manner according to the pattern of the metallization layer. This can enlarge the contact area. Also, the metallization layer does not required to be specially patterned for making contacts. A high aperture ratio can be obtained.

Abstract: A logic circuit is formed of an I.sup.2 L cell structure in which a difference of switching speeds at every collector in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constant current source transistor and a switch transistor is formed on a common semiconductor substrate, a first semiconductor layer (13) doped with a first conductivity type impurity and a second semiconductor layer (19) doped with a second conductivity impurity are electrically isolated from each other on a semiconductor substrate. A plurality of collector electrodes of the switch transistor and a plurality of collector regions (20) based on diffusion of impurity are formed by the second semiconductor layer (19). The first semiconductor layer (13) includes a base electrode deriving portion, and a direct contact portion which directly contacts with the semiconductor substrate between a plurality of collector regions (20).

Abstract: A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si substrate, the sheet resistance of the polycrystalline Si film forming the base outlet electrode of the npn transistor is decreased to two thirds of the sheet resistance of the polycrystalline Si film forming at least one electrode of at least one other device. The base outlet electrode can be made by first making the polycrystalline Si film on the entire surface of the substrate, then applying selective ion implantation of Si to a selective portion of the polycrystalline Si film for making the base outlet electrode to change it into an amorphous state, and then annealing the product to grow the polycrystalline Si film by solid-phase growth.

Abstract: A high-frequency bipolar transistor structure includes a base region of a first conductivity type formed in a silicon layer of a second conductivity type, the base region comprising an intrinsic base region surrounded by an extrinsic base region, an emitter region of the second conductivity type formed inside the intrinsic base region, the extrinsic base region and the emitter region being contacted by a first polysilicon layer and a second polysilicon layer respectively. The first and the second polysilicon layers are respectively contacted by a base metal electrode and an emitter metal electrode. Between the extrinsic base region and the first polysilicon layer, a silicide layer is provided to reduce the extrinsic base resistance of the bipolar transistor.

Abstract: In a semiconductor device including a silicon substrate, an insulating layer on the silicon substrate, a silicon layer on the insulating layer, the silicon layer being weakly doped with impurities of a first conduction type, a base region extending into the silicon layer from the free surface thereof, the base region being doped with impurities of a second conduction type, an emitter region extending into the base region from the free surface thereof, the emitter region being heavily doped with impurities of the first conduction type, and at least one collector region extending into the silicon layer from the free surface thereof at a lateral distance from the base region, the collector region being doped with impurities of the first conduction type, a floating collector region is provided in the silicon layer between the insulating layer and the base region at a distance from the base region.

Abstract: A method for fabricating a copper containing integrated circuit structure within an integrated circuit, and the copper containing integrated circuit structure formed through the method. There is first provided a substrate layer. There is then formed through a first electroless plating method a nickel containing conductor layer over the substrate layer. There is then activated the nickel containing conductor layer to form an activated nickel surface of the nickel containing conductor layer. Finally, there is then formed through a second electroless plating method a copper containing conductor layer upon the nickel containing conductor layer. Optionally, there may be formed a polysilicon layer over the substrate prior to forming the nickel containing conductor layer over the substrate, where the nickel containing conductor layer is formed upon the polysilicon layer. Optionally, there may also be formed a second nickel containing conductor layer upon the copper containing conductor layer.

Abstract: A semiconductor device has a metal silicide on silicon conductor formed using a salicide process. The metal silicide layer of the conductor includes boron which improves the morphology and conductivity of the metal silicide layer. Implanting boron into the metal silicide layer or the metal to be silicided prevents the metal silicide from aggregating during a subsequent annealing or other heating process. This process allows narrower conductors to be formed without undesirable increases in the resistance of the metal silicide layer. The boron incorporating salicide process is compatible with CMOS processes.

Abstract: A semiconductor device having the base and collector surrounded by a continuous tungsten filled slot as ground plane. The portion of the tungsten filled slot over the buried layer extends beyond the surface of the buried layer and the portion of the tungsten filled slot not over the buried layer extends beyond the interface between the epitaxial layer and the substrate.

Abstract: A method, and resulting product, are disclosed for selectively forming polycrystalline silicon over exposed portions of a single crystal silicon substrate. The method includes inhibiting the formation of such polycrystalline silicon over adjacent silicon oxide surfaces; and the resulting product of such a process. The polycrystalline silicon is selectively deposited over the single crystal silicon substrate by first forming a thin layer of a lattice mismatched material over the single crystal silicon surface, and then depositing a layer of polycrystalline silicon over the lattice mismatched material. Preferably, the thin lattice mismatched layer comprises a silicon/germanium (SiGe) alloy.

Abstract: A base region structure of a bipolar transistor is provided. The base region structure is formed over both an epitaxial layer having a first conductivity type and an insulation film. The base region structure comprises a single layer having a first conductivity type. The single layer comprises both an epitaxial portion extending over the epitaxial layer and a polycrystal portion extending over the insulation film. An emitter region is formed at an upper part of the epitaxial portion. The epitaxial portion serves as a base region and the polycrystal portion serves as a base plug lead.

Abstract: High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

Abstract: A transversal bipolar transistor is structured to have a single crystal semiconductor film provided on a single crystal semiconductor region which is provided on a semiconductor substrate. The semiconductor substrate is of a first conductivity type, and the single crystal semiconductor region is of a second conductivity type which is opposite to the first conductivity type. The single crystal semiconductor film is divided in the transversal direction into a central portion of the second conductivity type for a base region and left and right portions of the first conductivity type for emitter and collector regions. The transversal bipolar transistor may be integrated with a vertical bipolar transistor commonly on the semiconductor substrate.

Abstract: Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the s

Abstract: A back gate bias voltage is applied to the underside of a lateral bipolar transistor to desensitize a portion of the collector-base depletion region to changes in the collector-base voltage. Emitter-collector current flows through an active base region bypassing the portion of the collector-base depletion region that remains sensitive to the collector bias. This allows for a control over the charge in the active base region by the back gate bias, generally independent of the collector-base bias. The transistor is preferably implemented in a silicon-on-insulator-on-silicon (SOIS) configuration, with the back gate bias applied to a doped silicon substrate. The base doping concentration and the thickness of the underlying insulator are preferably selected to produce an inversion layer in the base region adjacent the insulating layer, thereby reducing the collector access resistance.

Abstract: A bipolar transistor includes a substrate, an insulating layer formed on the substrate, and a semiconductor layer having a bottom surface and side surfaces surrounded by the insulating layer. The semiconductor layer includes a collector region formed in a first surface portion of the semiconductor layer, and a collector lead region having a concentration higher than that of the collector region. The collector read region includes a silicon single crystal layer formed in a second surface portion of the semiconductor layer, and a polysilicon layer having side surfaces surrounded by the silicon single crystal layer. A base region is formed on the collector region, and an emitter region is formed in the base region.

Abstract: A lateral pnp transistor for use in programmable logic arrays. The lateral pnp has a layer of oxide disposed between a polysilicon layer and the base along the base width. The oxide layer prevents diffusion of the N+ dopant contained in the polysilicon layer into the N- base region. The base region thus remains N- and the resulting transistor has improved breakdown voltage characteristics while retaining the speed advantages of polysilicon contact layers. The lateral pnp transistor is manufactured by a method which requires minimal deviation from other methods used to manufacture lateral pnp transistors.

Abstract: A device structure is described wherein metal silicide contacts are made to polycrystalline silicon regions and nonmetal silicide contacts to monocrystalline silicon regions of an integrated circuit device. Polycrystalline silicon regions are formed and patterned. A dielectric masking layer is formed over the polycrystalline and monocrystalline silicon regions. The surfaces of the masking layer are covered and the irregularities of the surfaces filled with an organic material to thereby planarize the surfaces. The organic material is blanket etched until the masking layer which covers the polycrystalline silicon regions is exposed and allowing the masking layer which covers the monocrystalline silicon regions to remain covered with organic material. The exposed masking layer is removed from the polycrystalline regions. The remaining organic material is removed. A layer of metal film is blanket deposited over the wafer. The metal silicide contacts to polycrystalline regions are formed.

Abstract: A stress isolating signal path having one end of fixed to a bonding pad of an integrated circuit chip and another end which forms a flexible bonding surface is provided. The flexible bonding surface may be bonded to external package components or external circuitry using conventional wire bond, epoxy bond, tape automated bonding, flip chip bonding, or the like. The signal path is formed using conventional semiconductor thin film deposition, patterning, and etching techniques. The signal path comprises a conductive material compatible with batch semiconductor manufacturing technology.