Abstract: The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.

Abstract: Transistors can be used for a variety of electronic-based applications. Therefore, transistor efficiency and performance is of importance. An apparatus is presented herein to increase the locking range of transistors by leveraging cross-coupled injection transistors in conjunction with symmetry injection transistors. The transistor efficiency can also be increase by reducing a parasitic capacitance associated with the components of the transistor.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.

Abstract: A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed.

Abstract: An apparatus for transceiver signal isolation and voltage clamp from transient electrical events includes a bi-directional protection device comprising a bipolar PNPNP device assembly, a first parasitic PNPN device assembly, and a second parasitic PNPN device assembly. The bipolar PNPNP device assembly includes an NPN bi-directional bipolar transistor, a first PNP bipolar transistor, and a second PNP bipolar transistor, and is configured to receive a transient voltage signal through first and second pads. The first and second pads are electrically connected to the PNPNP device assembly through emitters of the first and second PNP bipolar transistors. The bipolar PNPNP device assembly is electrically connected to a first parasitic PNPN device assembly comprising a parasitic PNP bipolar transistor and a first parasitic NPN bipolar transistor.

Abstract: A semiconductor device having a lateral insulated gate bipolar transistor includes a first conductivity type drift layer, a second conductivity type collector region formed in a surface portion of the drift layer, a second conductivity type channel layer formed in the surface portion of the drift layer, a first conductivity type emitter region formed in a surface portion of the channel layer, and a hole stopper region formed in the drift layer and located between the collector region and the emitter region. Holes are injected from the collector region into the drift layer and flow toward the emitter region through a hole path. The hole stopper region blocks a flow of the holes and narrows the hole path to concentrate the holes.

Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.

Abstract: A structure comprises an N+ region formed over a substrate, a P+ region formed over the substrate, wherein the P+ region and the N+ region form a diode and a first epitaxial growth block region formed between the N+ region and the P+ region.

Abstract: Disclosed is a transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.

Abstract: According to one embodiment, a semiconductor device that has a rectification element includes a semiconductor substrate, a first well region of a first conductivity type formed on the semiconductor substrate, a second well region of a second conductivity type formed on the semiconductor substrate, and a plurality of fins arranged over the first well region and the second well region at a first pitch in the same direction. In the semiconductor device, the rectification element includes a cathode region, an anode region, a well contact region, and a trigger region that are configured using fins. These regions are connected to each wiring portion to form a PNP-type bipolar transistor and an NPN-type bipolar transistor.

Abstract: An electrostatic discharge (ESD) protection element using an NPN bipolar transistor, includes: a trigger element connected at one end with a pad. The NPN bipolar transistor includes: a first base diffusion layer; a collector diffusion layer connected with the pad; a trigger tap formed on the first base diffusion layer and connected with the other end of the trigger element through a first wiring; and an emitter diffusion layer and a second base diffusion layer formed on the first base diffusion layer and connected in common to a power supply through a second wiring which is different from the first wiring.

Abstract: An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.

Abstract: A bidirectional power transistor formed horizontally in a semiconductor layer disposed on a heavily-doped semiconductor wafer with an interposed insulating layer, the wafer being capable of being biased to a reference voltage, the product of the average dopant concentration and of the thickness of the semiconductor layer ranging between 5·1011 cm?2 and 5·1012 cm?2.

Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.

Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance.

Abstract: Disclosed is a device structure using an inverse-mode cascoded Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) beneficial in applications requiring radiation hardened circuitry. The device comprises a forward-mode common-emitter HBT cascoded with a common-base inverse-mode HBT, sharing a common sub-collector. An exemplary device was measured to have over 20 dB of current gain, and over 30 dB of power gain at 10 GHz, thus demonstrating the use of these circuits for high-frequency circuit applications. In addition, the radiation response and voltage limits were characterized and showed to have negligible performance effects in typical operating conditions. Due to the unique topology, the disclosed device has the benefit of being a more compact cascode design and the additional benefit of providing significantly improved radiation tolerance.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract: An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.

Abstract: A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-are lithographic patterning. An opening is aligned above the dielectric pad and etched through an isolation oxide layer to an extrinsic base layer. The opening is equal to or greater in size than the dielectric pad. Another smaller opening is etched through the extrinsic base layer to the dielectric pad. A multi-step etching process is used to selectively remove the extrinsic base layer from the surfaces of the dielectric pad and then to selectively remove the dielectric pad. An emitter is then formed in the resulting trench. The resulting transistor structure has a distance between the edge of the lower section of the emitter and the edge of the extrinsic base that is minimized, thereby, reducing resistance.

Abstract: Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region.

Abstract: A semiconductor device (10) includes a semiconductor body (12) of a first conductivity type (e.g., p-type). A first doped region (14) of a second conductivity type (e.g., n-type) is disposed at an upper surface of the semiconductor body (12). A second doped region (16) of the second conductivity type is disposed at the upper surface of the semiconductor body (12) and is separated from the first doped region (14) by an isolation region (18). A first contact (26) overlies and is electrically coupled to the first doped region (14) and a second contact (28) overlies and is electrically coupled to the second doped region (16). A third doped region (32) of the first conductivity type is disposed within the semiconductor body (12) beneath the first doped region (14).

Abstract: Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body.

Abstract: A power transistor (210) comprises a plurality of unit cell devices (212), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (194), each unit cell device including base (80), emitter (82), and collector (84) portions. The base contact configuration includes (i) a first base feed (150) coupled to the base portion of each unit cell device via a first end of at least one base finger (154) associated with a corresponding unit cell device and (ii) a second base feed (152) coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device.

Abstract: A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, an NPN transistor is formed. Around the NPN transistor, a protection element having a PN junction region is formed. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of the NPN transistor. By use of this structure, when negative ESD surge is applied to a pad for a base electrode, the PN junction region of the protection element breaks down. Accordingly, the NPN transistor can be protected.

Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.

Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.

Abstract: In a protection circuit of an input/output terminal I/O, three types of PNP bipolar transistors are included. In a first PNP type bipolar transistor 10A, the emitter thereof is connected to the input/output terminal I/O, the base thereof is connected to a high-potential power supply terminal VDD, and the collector thereof is connected to a low-potential power supply terminal VSS. In a second PNP type bipolar transistor 10B, the emitter thereof is connected to the input/output terminal I/O, and the base and the collector thereof are connected to the high-potential power supply terminal VDD. In a third PNP type bipolar transistor 10C, the emitter thereof is connected to the low-potential power supply terminal VSS, and the base and the collector thereof are connected to the high-potential power supply terminal VDD.

Abstract: The present invention relates to an integrated circuit. The integrated circuit includes a substrate, at least one device region formed in the substrate, a patterned layer of oxide, a first and second layer of nitride and at least one metal contact region. The patterned layer of oxide is formed over a surface of the substrate, wherein the patterned layer provides at least one opening to the surface of the substrate adjacent the at least one device region. The first layer of nitride is formed over the patterned oxide layer. The second nitride layer is formed along sidewalls to the at least one opening. The patterned oxide layer is sealed with the first and second nitride layers. The at least one metal contact region is formed in the at least one opening.

Abstract: A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.

Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.

Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.

Abstract: A structure of protection of a first area of a semiconductor wafer including a substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer, includes a very heavily-doped wall of the first conductivity type having substantially the depth of the upper portion. The wall is divided into three heavily-doped strips of the first conductivity type separated and surrounded by medium-doped intermediary strips of the first conductivity type. The distance between the heavily-doped strips being of the order of magnitude of the substrate thickness.

Abstract: Placing a flow modifier on a package substrate to create two flow fronts on a molded matrix array package. A flow modifier may be laid on a package substrate to a height that blocks off the bottom of other substrates (e.g., dice) coupled to the package substrate. By separating the top flow front and the bottom flow front, this process prevents the top flow front from wrapping around the sides of the substrates and trapping air below each substrate and in front of the bottom flow front.

Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.

Abstract: A bipolar transistor with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structure and the collector region.

Abstract: A lateral semiconductor device includes: a semiconductor substrate formed on a base region therein; a plurality of emitter regions with a triangle arrangement in an upper part of the base layer and collector regions surrounding the emitter regions, respectively, apart from the emitter regions with a predetermined space through the base layer; the base layer formed in a concentric circular pattern on the upper part; the emitter regions and collector regions provided with contacts respectively; and emitter and collector wiring layers connected to the contacts.

Abstract: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa.

Abstract: A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

Abstract: A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy.

Abstract: The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a third connection conductor (4, 5, 6), while the bandgap of the base region (2) is lower than that of the collector region (3) or of the emitter region (1), for example owing to the use of a silicon-germanium alloy instead of pure silicon. Such a device is very fast, but its transistor shows a relatively low BVceo. In a device according to the invention, the emitter region (1) or the base region (2) comprises a sub-region (1B, 2B) with a reduced doping concentration, which sub-region (1B, 2B) is provided with a further connection conductor (4B, 5B) which forms a Schottky junction with the sub-region (1B, 2B). Such a device results in a transistor with a particularly high cut-off frequency fT but with no or hardly any reduction of the BVceo.

Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.

Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.