Abstract: The invention provides a bipolar transistor attaining large MSG and a method of fabricating the same. The bipolar transistor of this invention includes a collector layer; abase layer deposited on the collector layer; and a semiconductor layer deposited on the base layer in the shape of a ring along the outer circumference of the base layer, the semiconductor layer includes a ring-shaped emitter region functioning as an emitter, and the outer edge of the emitter region and the outer edge of the base layer are disposed in substantially the same plane position.

Abstract: A bipolar transistor having a base contact surrounded by an emitter contact. A plurality of wires extending from the base contact and the emitter contact of the bipolar transistor, wherein the wires of the base contact are stacked higher than the wires of the emitter contact. A device comprising a plurality of these bipolar transistors, wherein at least one side of each emitter contact abuts each adjacent transistor. Increasing the wiring stack of each row of transistors in the device as the distance between the row and the current input increases.

Abstract: A lateral semiconductor device includes an n-type buffer layer (15) selectively formed in the surface of an n-type base layer (14), a p-type drain layer (16) selectively formed in the surface of the n-type buffer layer (15), a p-type base layer (17) formed in the surface of the n-type base layer (14) so as to surround the n-type buffer layer (15), an n+-type source layer (18) selectively formed in the surface of the p-type base layer (17), a source electrode (24) in contact with the p-type base layer (17) and the n+-type source layer (18), a drain electrode (22) in contact with the p-type drain layer (16), and a gate electrode (20) formed via a gate insulating film (19) on the surface of the p-type base layer (17) sandwiched between the n+-type source layer (18) and the n-type base layer (14). The p-type drain layer (16) has an annular structure or horseshoe-shaped structure, or is divided into a plurality of portions. This realizes a high breakdown voltage with a low ON voltage.

Abstract: A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a collector terminal, and an emitter terminal are provided. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. A sub-collector layer is formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter is formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector contact for coupling to the collector terminal is deposited in a trench that is formed in the collector layer and the sub-collector layer.

Abstract: Various embodiments of a novel transistor layout having improved electrical and heat dissipation characteristics are disclosed. Several embodiments include various intrinsic components contoured to the shape of the emitter. The various intrinsic components may include a collector layer center portion, a collector contact, a base pedestal, and/or a base contact. Additional embodiments include improved heat dissipation within single transistors. Still further embodiments include improved heat dissipation across a plurality of transistors.

Abstract: An integrated circuit chip package having a metal substrate core having two or more electrically isolated regions, wherein the electrically isolated regions of the metal substrate core may be coupled with voltage rails of an integrated circuit chip.

Abstract: A power transistor cell includes an air bridge and a plurality of individual transistors. Each of the plurality of individual transistors has at least one separate connection contact. Each of the at least one separate connection contact of the plurality of individual transistors is thermally conductively connected to one another through the air bridge forming air bridge connections, which define a contact plane. A surface of the contact plane that contains each connection path between two of the air bridge connections defines a convex region. The air bridge is formed to have, in the contact plane, dimensions that exceed a smallest convex region containing all of the air bridge connections in all directions of the air bridge. Each of the plurality of power transistor cells can be respectively thermally conductively connected to one another through the air bridge to form a block of power transistor cells.

Abstract: A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electrically isolated and spatially separated from each other. The plural divided sub-emitter regions may typically have a uniform emitter size identical with a basic emitter size of the basic bipolar transistor. A set of the plural divided sub-emitter regions provides an intended emitter current distinctly larger than the basic emitter current by a highly accurate direct current amplification factor corresponding to an intended emitter-size magnification factor.

Abstract: According to a disclosed embodiment, a base region is grown on a transistor region. A dielectric layer is next deposited over the base region. The dielectric layer can comprise, for example, silicon dioxide, silicon nitride, or a suitable low-k dielectric. Subsequently, an opening is fabricated in the dielectric layer, and an emitter layer is formed on top of the dielectric layer and in the opening. Thereafter, an anisotropic polymerizing etch chemistry is utilized to etch the emitter layer down to a first depth, forming an emitter region in the opening. Next, a non-polymerizing etch chemistry having isotropic components is used to create a notch in the dielectric layer below the emitter region. The formation of the notch reduces the overlap area of a capacitor that forms between the emitter region and the base region, which translates to a lower level of emitter to base capacitance.

Abstract: A method for manufacturing a silicon bipolar power high frequency transistor device is disclosed. A transistor device according to the present method is also disclosed. The transistor device assures conditions for maintaining a proper BVCER to avoid collector emitter breakdown during operation. According to the method an integrated resistor is arranged along at least one side of a silicon bipolar transistor on a semiconductor die which constitutes a substrate for the silicon bipolar transistor. The integrated resistor is connected between the base and emitter terminals of the silicon bipolar transistor. The added integrated resistor is a diffused p+ resistor on said semiconductor die or a polysilicon or NiCr resistor placed on top of the isolation layers. In an interdigitated transistor structure provided with integrated emitter ballast resistors the added- resistor or resistors (20) will be manufactured in a step simultaneously as producing the ballast resistors.

Abstract: A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.

Abstract: A semiconductor chip 10 is provided to form a large number of cells constituting transistor units arranged on a planar and rectangular semiconductor substrate. On the front surface of the semiconductor chip 10, an emitter electrode 1 to be connected to an emitter and a base electrode 2 to be connected to an base are formed and electrode pads 1a and 2a of the emitter electrode 1 and the base electrode 2 are formed on opposite long sides of the rectangular substrate. On the rear surface of the semiconductor chip 10, a collector electrode 3 to be connected to a collector is formed. The semiconductor chip 10 is bonded to a rectangular island 6a at the tip of a third lead 6. A first lead 4 and a second lead 5 are directly connected to the emitter electrode pad 1a and base electrode pad 2a, respectively.

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency(fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract: A peripheral structure for a monolithic power device, preferably planar, includes front and rear surfaces, connected respectively to a cathode and an anode, two junctions respectively reverse-biased and forward-biased when a direct and adjacent voltage is respectively applied to the two surfaces and at least an insulating box connecting the front and rear surfaces. The structure is such that when a direct voltage or a reverse voltage is applied, generating equipotential voltage lines, the insulating box enables to distribute the equipotential lines in the substrate.

Abstract: A plurality of MOS transistors are arranged on the top surface of a conductor substrate which is a drain electrode. The drain contact of each MOS transistor is connected to the conductor substrate. The source contact of each MOS transistor is connected to the output conductor path which is a source electrode through a bonding wire. The gate contact of each MOS transistor is connected to a drive signal conductor path which is a gate electrode through a bonding wire. The source contacts of the MOS transistors are interconnected through a bridge electrode and a bonding wire.

Abstract: A lateral bipolar type input/output protection device of the present invention includes a N type well formed below an emitter impurity diffusion layer of N type over a P type substrate. With such construction of the lateral bipolar type input/output protection device, a parasitic bipolar operation occurs easily and sufficient electrostatic durability without degradation of protection performance of the protection device even when a semiconductor integrated circuit is miniaturized by employing the STI isolation structure.

Abstract: In the case of a semiconductor device where a base electrode 11 in a collector top heterojunction bipolar transistor is disposed so as to contact with the side face of a base layer 5 in which no ion is implanted and the surface of a high resistance extrinsic emitter area 14 in which ion is implanted, the dependence of the current gain in the collector top HBT on the collector size can be diminished.

Abstract: The device is constituted by an N+ substrate, by an N− layer on the substrate, by a metal contact for a collector, by a buried P− base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on the base contact region for a base, by an N+ emitter region buried in the insulated region and forming a pn junction with the buried base region, by a P+ body region in the insulated region, by an N+ source region in the P+ region, by a metal contact for a source, and by a gate electrode. In order to achieve a low resistance Ron, the P+ body region extends as far as the buried N+ emitter region and an additional N+ region is provided within the body region and constitutes a drain region, defining, with the source region, the channel of a lateral MOSFET transistor.

Abstract: A semiconductor process is disclosed which forms openings in a dielectric layer through which the base region of both high-voltage and high-gain bipolar transistors are formed. In one embodiment of the invention, the openings for the high-gain transistors are first protected by a photoresist layer that is patterned to expose the openings for the high-voltage transistors. A first base implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the openings for the high-gain devices, and a second base implant is performed, this time into both base regions, and then diffused to a suitable depth. Emitter regions are then formed within the base regions of both transistor types by traditional implantation and contact techniques.

Abstract: A lateral PNP-type transistor, and a process for producing such lateral PNP-type transistor from a substrate are provided. In particular, a PNP-emitter and a PNP-collector. The PNP-collector is provided at a predetermined distance from the PNP emitter. The PNP-emitter is electrically insulated from the PNP-collector.

Abstract: Performance of an RF power bipolar transistor having a collector region, at least one base region, and a plurality of elongated emitter fingers in each major region, is enhanced by forming each emitter finger with at least two spaced segments and contacting the two spaced segments with a metal lead. By eliminating the middle portion of each emitter finger, current hogging at the central portion and hot spot generation are eliminated. Power output is maintained with reduced emitter lengths by minimizing the adverse affects of the hot spot generation in the emitters.

Abstract: A process for fabricating semiconductor devices, comprises forming a surface film on the surface of a semiconductor substrate. The semiconductor substrate is doped with dopant through the surface film to form a dopant distribution layer. The doped surface film is removed, and then anneal is done to accomplish desired dopant profile of the box type.

Abstract: A packaged integrated circuit device includes a substrate including a first circuit component mounted thereon, a first conductor extending from the first circuit component, and a dielectric lid. The dielectric lid includes a component mounting surface, a second circuit component mounted on the component mounting surface, and a second conductor extending from the second circuit component. The dielectric lid is adapted to engage with the substrate such that the first circuit component is in electrical communication with the second circuit component. The second circuit component may comprises an impedance matching circuit. The circuit device may also include fastening means for securing the lid to the substrate. The fastening means may comprise an adhesive, solder, or a spring biased member.

Abstract: In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region (1) of one conductivity type forms a switchable p-n junction (12) with a second region (2) of opposite conductivity type. In accordance with the invention, this first region (1) includes three distinct zones, namely a low-doped zone (23), a high-doped zone (25), and an intermediate additional zone (24). The low-doped zone (23) is provided by a semiconductor body portion (11) having a substantially uniform p-type doping concentration (P−) and forms the p-n junction (12) with the second region (2). The distinct additional zone (24) is present between the low-doped zone (23) and the high-doped zone (25). The high-doped zone (25) which may form a contact zone has a doping concentration (P++) which is higher than that of the low-doped zone (23) and which decreases towards the low-doped zone (23).

Abstract: A semiconductor device which comprises a semiconductor chip packaged in a resin package and having an electrode terminal wire-bonded to a conductor cap having one end defining an exposed top of an external connection terminal protruding from the resin package and the other end defining an orifice embedded in the resin package, wherein the orifice of the conductor cap has a radially outward extending flange which anchors the conductor cap to the resin package. The process of producing the semiconductor device is also disclosed.

Abstract: An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor material over a collector region. A raised sacrificial emitter core is then formed on the intrinsic base region followed by depositing a substantially conformal spacer layer over the sacrificial emitter core. Next, the spacer material is anisotropically etched such that a protective spacer ring is formed about the sacrificial emitter core. An extrinsic base is then formed by implanting dopant into the epitaxial base region wherein the sacrificial emitter core and the spacer ring preserve an emitter region. The spacer ring also serves to self-align the extrinsic base region to the emitter region. The protective sacrificial emitter core and spacer ring are then removed.

Abstract: An n-type first single crystal silicon layer is provided as collector region over a silicon substrate with a first insulating film interposed therebetween. A p-type first polysilicon layer is provided as an extension of a base region over the first single crystal silicon layer with a second insulating film interposed therebetween. A p-type second single crystal silicon layer is provided as intrinsic base region on a side of the first single crystal silicon layer, second insulating film and first polysilicon layer. An n-type third single crystal silicon layer is provided as emitter region on a side of the second single crystal silicon layer. And an n-type third polysilicon layer is provided on the first insulating film as extension of an emitter region and is connected to a side of the third single crystal silicon layer.

Abstract: High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

Abstract: A power transistor comprising a collector region formed in a semiconductor substrate, a base region formed within the collector region, and a hoop-shaped emitter region formed within the base region. The hoop-shaped emitter region divides the base region into an external section and at least one internal section surrounded by the emitter region on the substrate surface, the external and internal base sections being connected within the substrate. A base contact is formed on the surface of each internal base section surrounded by the emitter region. By this design, the electric current is more uniform within the emitter region, and safe operating area (SOA) destruction can be prevented. The invention is also directed to semiconductor integrated circuit devices using the above power transistor, and a method of forming the same.

Abstract: A semiconductor device has a first region, a second region and a border region between the first region and the second region. The semiconductor device has an interlayer dielectric layer, covering at least the first region and the second region. A first wiring layer is located in the first region and defines a relatively small pattern. A second wiring layer is located in the second region and defines a relatively large pattern that is wider than the small pattern. A first dummy pattern is formed in the first region and a second dummy pattern is formed in the border region. The interlayer dielectric layer includes a planarization silicon oxide film. The planarization silicon oxide film is one of a silicon oxide film formed by a polycondensation reaction between a silicon compound and hydrogen peroxide, an organic SOG (Spin On Glass) film an inorganic SOG film and a silicon oxide film formed by reacting an organic silane with ozone or water.

Abstract: One embodiment of a semiconductor device includes a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions.

Abstract: A semiconductor integrated circuit has a protective NMOS transistor having a drain and a source respectively electrically connected to a first interconnection (electrically connected to a base electrode of a bipolar transistor or a gate electrode of a MOS transistor) and ground and a gate electrode in a floating state, upon formation of the first interconnection. The first interconnection is formed by patterning using plasma etching and is connected to ground after the formation of the first interconnection.

Abstract: A power transistor includes a plurality of emitter regions and a plurality of base contacts. In order to decrease base resistance, each of the plurality of emitter regions is adjacent to at least four base contacts. The entire transistor includes multiple emitter regions, e.g., greater than or equal to about 1,000 with no upper limit wherein the actual number of emitter regions is dependent on the desired current carrying capacity. The emitter regions are directly connected in parallel to the high current carrying metal layer of the transistor through vias or metal contact studs. The size of the emitter regions should be made as small as the process design rules will allow in order to allow an increase in the perimeter to area ratio of the emitter region which, for a given current, decreases the peak current density.

Abstract: A method of manufacturing a semiconductor device simultaneously forms a first vertical bipolar transistor which operates at a relatively low speed and is of a high withstand voltage and a low power requirement and a second vertical bipolar transistor which operates at a relatively high speed and is of a high power requirement. The method comprises the steps of forming openings for selectively forming single crystal base regions respectively in the vertical bipolar transistors, forming single crystal base regions via the openings, forming an insulating film on a device forming surface of a semiconductor substrate after the base regions are formed, and introducing ions of an impurity of the same conductivity type as a collection region via the insulating film. The opening in the second vertical bipolar transistor is of a size greater than the opening in the first vertical bipolar transistor.

Abstract: A power semiconductor components has stop zones. In order to optimize the static and dynamic losses of the power semiconductor components, the stop zone is provided with donors which have at least one donor level which lies within the band gap of silicon and is at least 200 meV away from the conduction band edge of silicon.

Abstract: The invention relates to a semiconductor device including a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. In a device according to the invention, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor in a device according to the invention is provided with a pn clamping diode which is formed between the partial region and the collector region.

Abstract: The present invention relates to a vertical bipolar power transistor primarily intended for radio frequency applications and to a method for manufacturing, the bipolar power transistor. The power transistor comprises a substrates, a collector layer of a first conductivity type on the substrate, a base of a second conductivity type electrically connected to the collector layer, an emitter of the first conductivity type electrically connected to the base, the base and the emitter each being electrically connected to a metallic interconnecting layer, the interconnecting layers being at least in parts separated from the collector layer by an insulation oxide. According to the invention the power transistor substantially comprises a field shield electrically connected to the emitter, and located between the metallic interconnecting layer of the base and the insulation oxide.

Abstract: A transistor with a novel compact layout is provided. The transistor has an emitter layout having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. A base terminal, a collector terminal, and an emitter terminal are provided. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. A sub-collector layer is formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter is formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector terminal for coupling to the collector contact is deposited in a trench that is formed in the collector layer and the sub-collector layer.

Abstract: A power transistor includes a plurality of emitter regions and a plurality of base contacts. In order to decrease base resistance, each of the plurality of emitter regions is adjacent to at least four base contacts. The entire transistor includes multiple emitter regions, e.g., greater than or equal to about 1,000 with no upper limit wherein the actual number of emitter regions is dependent on the desired current carrying capacity. The emitter regions are directly connected in parallel to the high current carrying metal layer of the transistor through vias or metal contact studs. The size of the emitter regions should be made as small as the process design rules will allow in order to allow an increase in the perimeter to area ratio of the emitter region which, for a given current, decreases the peak current density.

Abstract: The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base, to form a base contacting region. A second portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor emitter, to form an emitter contacting region.

Abstract: An emitter conducting portion, which comprises a p+-type silicon substrate 10, p+-type emitter buried region 14 and a p+-type emitter leading region 20, is formed in a semiconductor element. The p+-type silicon substrate 10 of the semiconductor element is die-bonded to an emitter lead ER for electrically connecting an emitter electrode E to the emitter lead ER by means of the emitter conducting portion. Thus, it is possible to dispense with an emitter bonding wire for connecting the emitter electrode E to the emitter lead ER, and it is possible to remove impedance caused by the emitter bonding wire, so that it is possible to improve the high-frequency characteristics of a semiconductor device.

Abstract: A semiconductor device includes an emitter region, a contact region, and a resistive medium. The resistive medium is connected between the contact region and the emitter region. The contact region and the emitter region each include an edge facing each other. At least a portion of the emitter region edge and at least a portion of the contact region edge are non-parallel relative to each other. This configuration enables an emitter ballast resistance to be provided with varied emitter current flow along the injecting edge of the emitter. Furthermore, by including an additional contact and an additional resistive medium between the contacts, the ballast resistance of the semiconductor device can be increased without decreasing the figure of merit of the device.

Abstract: A lateral transistor includes a semiconductor substrate of a first conductivity type having a major surface; an emitter region of a second conductivity type in the semiconductor substrate on the major surface of the semiconductor substrate; a collector region of a second conductivity type in the semiconductor substrate on the major surface of the semiconductor substrate, spaced from and surrounding the emitter region, and including sides and corners; an electrically insulating layer on the major surface of the semiconductor substrate and including a first penetrating hole extending to the collector region except at a first of the corners and a second penetrating hole extending to the emitter region; a collector electrode contacting the collector region through the first penetrating hole and surrounding the emitter region except at the first corner; an emitter electrode at the same level as the collector electrode and contacting the emitter region through the second penetrating hole; and an emitter wiring laye

Abstract: A semiconductor device provided with a semiconductor substrate with a bipolar transistor having a collector region of a first conductivity type, a base region adjoining the collector region and of a second conductivity type opposed to the first, and an elongate emitter region of the first conductivity type adjoining the base region; the collector region, the base region, and the emitter region being provided with conductor tracks which are connected to conductive connection surfaces. The conductor track on the elongate emitter region of the semiconductor device has a connection to a connection surface for a further electrical connection at each of the two ends of the emitter region. The emitter region may be made longer in this manner because the length of the emitter region is effectively halved by the connections at the two ends. Consequently, charge carriers need be transported over no more than at most half the emitter length.

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.

Abstract: A bipolar silicon transistor includes at least one emitter zone with n.sup.+ arsenic doping and with a phosphorus doping. The ratio between arsenic dopant concentration and phosphorus dopant concentration is between 10:1 and 500:1 in the at least one emitter zone. The at least one emitter zone may also have a penetration depth of less than 0.5 .mu.m. A method for producing a bipolar silicon transistor includes implanting a n.sup.+ -doped emitter zone with arsenic, implanting the n.sup.+ -doped emitter zone with phosphorus, setting a ratio in the n.sup.+ -doped emitter zone between the arsenic dopant concentration and phosphorus dopant concentration to between 10:1 and 500:1, and annealing crystal defects.

Abstract: A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region, a base region overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried region a surface region, and a first vertical diffusion region connecting the buried layer to the surface region. A second vertical diffusion region connects the buried emitter layer periphery to a first surface contact, while the surface emitter region is contacted, along three peripheral sides thereof, by a second surface contact. The transistor current flows from the substrate, through the base to the buried emitter region. It is then conveyed into the vertical region, which represents a resistive path, and on reaching the surface region splits between two resistive paths included between the vertical region and the surface contacts.

Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.

Abstract: The present invention, generally speaking, provides an apparatus and method whereby the current flow through an RF power transistor may be monitored without the use of any external parts. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, a pair of interdigitated electrodes formed on the silicon die, each having a multiplicity of parallel electrode fingers and at least one bond pad. Regions of a first type of diffusion are formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion are formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes. One electrode has multiple electrode fingers and multiple resistors formed on the silicon die, at least one resistor connected in series with each one of the electrode fingers.