Abstract: A bipolar transistor is provided in which the emitters do not traverse the base but terminate inside the top surface of the base. Each emitter is L-shaped in some embodiments. The base top surface has a polygonal or circular outer boundary. The transistor has a long emitter perimeter available for base current flow and more than two emitter sides (e.g., five sides) available for base current flow. Further, the transistor has a large ratio of the emitter area to the base area. Consequently, the transistor has low noise, high gain, high frequency range, and a small size.

Abstract: A semiconductor device includes a semiconductor body (1) having a semiconductor element with connection points (2, 3) which adjoins a surface (4) of the semiconductor body (1) and is laterally insulated and surrounded by a first depression (5) in the surface (4), which depression (5) is provided with a wall (6) and a bottom (7), while the surface (4) of the semiconductor body (1) and the wall (6) and bottom (7) of the depression (5) are covered with an insulating layer (8). The connection points (2, 3) are provided in the insulating layer (8) on the surface (4) of the semiconductor body (1) and are connected to conductor tracks (10, 11) which connect the connection points (2, 3) across a wall (6) to connection surfaces (12, 13) associated with the connection points (2, 3) and situated on the bottom (7). It is found in practice that, in the case of progressive miniaturization, the manufacture of such devices leads to rejects caused by short-circuits between connection surfaces (12, 13).

Abstract: The present invention discloses method for fabricating, and the structure of, a unique and novel bipolar transistor. The bipolar transistor of the present invention has a substantially uniform current density in base and collector regions. This uniform current density prevents the characteristic early fall-off of bipolar transistor current gain, and improves the forward safe operating area performance. As such, the bipolar transistor of the invention increases current gain at high collector currents, and expands the current and voltage region over which the device may safely operated. The advantages of the present invention are achieved by optimally spacing the neighboring emitters in relation to base thickness and further by maintaining a symmetrical topology by the self-aligned formation of emitters and base contacts.

Abstract: An integrated circuit power transistor, comprising an elongate, resistive, base region and an elongate emitter region formed in part of the base region to provide a base-emitter junction. The power transistor also includes a strip-like base connection formed in part of the base region. The base connection extends from a base terminal towards a remote end, and includes a junction-facing edge facing the base-emitter junction. The junction-facing edge is spaced from the base-emitter junction by a distance that decreases towards the remote end of the base connection. This sets the base side of the base-emitter junction to substantially the same voltage at all points along the length of the base-emitter junction despite an ohmic voltage drop in the base connection that increases towards the remote end of the base connection.

Abstract: Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter, a base 50 and a collector 70 is disclosed, wherein the emitter composed of one or more islands 30 of semiconductor material having a wider energy bandgap than the base 50. The islands 30 are formed so that they do not cross any boundaries of the active area 60 of the transistor.Other devices, systems and methods are also disclosed.

Abstract: A semiconductor device implemented using a transistor (Q1) including at least one emitter (E1) and a transistor (Q2) which is larger than the transistor (Q1) including n emitters (E21 to E2n) each having the same area as the emitter (E1) of the transistor (Q1). The emitter (E1) of the transistor (Q1) is disposed between the emitters (E21 to E2n) of the transistor (Q2). When there is deflection of a substrate due to a stress to cause distortion in shape of the emitters, the emitter (E1) has much less distortion in shape than the emitters located on the end portions of the row region in the longitudinal direction. Since the transistor (Q2) has a number of emitters, the distortion in shape of the emitters (E21 to E2n) of the transistor (Q2), if any, has little effect on the whole.

Abstract: A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: A layout is provided for RF power transistors that reduces common lead inductance and its associated performance penalties. An RF transistor cell is rotated 90.degree. with respect to a conventional RF transistor cell so as to located bond pads nearer the edge of a silicon die, reducing bond wire length and common lead inductance and thereby improving performance at high frequencies. The placement of bond pad and distribution of different parts of the transistor layout further reduces common lead inductance.

Abstract: An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

Abstract: A bipolar integrated circuit with N-type wells (2) formed in a P-type substrate (1) includes in first wells, first transistors (EBC), the well of which constitutes the collector. P-type base region (7a) is formed in the first well with an N+ emitter region (8) formed in the base region. In at least a second well forming a collector, a composite second transistor (E'B'C') is constituted by an elemental third transistor (E.sub.1 B.sub.1 C') comprising regions of the same doping level as the first transistor and an elemental fourth transistor (E.sub.2 B.sub.2 C') having a base region (11) with a high doping level with respect to that of the bases of the first transistor. Emitter regions (8b, 12) of the elemental transistors are of the same doping level as that of the first transistors. The emitters and bases of the third and fourth elementary transistors are interconnected and constitute the emitter and the base of the composite second transistor.

Abstract: An architecture for producing multiple emitter vertical bipolar transistors which substantially eliminates the starved regions found in the standard lattice architecture. An "offset lattice" design is described in which the base contact segments in adjacent stripes are shifted or offset relative to each other. This causes the emitter pieces which are added to connect adjacent emitter stripes to be staggered with respect to each other. As a result, all sections of the emitters face a base contact and the resistance encountered along a current path between a base contact and an emitter is reduced. This results in a vertical bipolar transistor having a larger proportion of highly activated emitter, better high-frequency performance, and a reduction in thermal noise owing to transistor base resistance.

Abstract: The ballast resistance of a semiconductor device is increased without decreasing the figure of merit of the device. The semiconductor device includes an emitter feeder, a first contact coupled to the emitter feeder, a second contact, a resistive medium connected between the first contact and the second contact, an emitter, and a further resistive medium connected between the second contact and the emitter. The ballast resistance of the semiconductor device is increased without decreasing the figure of merit of the device by increasing the distance between the first contact and the second contact.

Abstract: A power transistor has a plurality of small emitter-base complexes arranged in an array. These complexes are electrically insulated from the surrounding semiconductor material by separating regions such that for the current supply to the collectors, a joint subcollector layer and thereupon a collector metallization exist outside of the emitter-base complexes and reaching up to the separating regions. The individual emitter-base complexes are electrically connected with each other via strip-shaped base supply lines and strip-shaped emitter supply lines, and also with a base contact surface and an emitter contact surface.

Abstract: Operating characteristics of an electronics device in which alternating currents flow are improved by reducing positive electromagnetic coupling between currents. This is accomplished by altering the direction of a current flow to obtain negative coupling through current flow in the same direction, or by minimizing electromagnetic coupling through perpendicular current flow, or by increasing the spacing between two electromagnetically coupled currents. In a bipolar transistor structure a feed structure for emitter and base current includes wire bonding pads aligned so that emitter current and base current flow to wire bonding pads perpendicular to the direction of collector current flow and with adjacent emitter currents and base currents flowing in the same direction. Each feed structure includes a plurality of interdigitated fingers for contacting emitter and base regions, all emitter and base currents in said interdigitated fingers of all feed structures flowing in the same direction as the collector.

Abstract: A bipolar transistor is provided in which the emitters do not traverse the base but terminate inside the top surface of the base. Each emitter is L-shaped in some embodiments. The base top surface has a polygonal or circular outer boundary. The transistor has a long emitter perimeter available for base current flow and more than two emitter sides (e.g., five sides) available for base current flow. Further, the transistor has a large ratio of the emitter area to the base area. Consequently, the transistor has low noise, high gain, high frequency range, and a small size.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: A vertical type construction transistor of this invention includes: a semiconductor substrate; a semiconductor multilayer formed on the semiconductor substrate, the semiconductor multilayer including at least an emitter layer, a collector layer, and a base layer; a first electrode electrically connected to the base layer; a second electrode electrically connected to one of the emitter layer and the collector layer; a third electrode formed on the semiconductor multilayer, and electrically connected to the other of the emitter layer and the collector layer, the third electrode being extended in a first direction; an insulating film formed substantially over the semiconductor multilayer; and an overlay electrode at least partially formed on the insulating film, the overlay electrode being electrically connected to the third electrode, at least partially formed on the insulating film, and extending out in a direction normal to the first direction so as to be in partial contact with the semiconductor substrate, t

Abstract: A bipolar transistor is disclosed which substantially reduces prior art problems associated with current crowding by maximizing the active periphery of the transistor's emitter [10].

Abstract: A vertical type construction transistor is provided wherein a bump electrode is disposed immediately on the junction portions formed on the surface of the semiconductor basic plate so as to effect a radiating operation with the electrode being connected to a heat sink. As a result the heating of the junction portion formed on the basic plate surface is effectively released, the inductance of the outgoing line is reduced, and the power amplification used in the microwave band is put to practical use.

Abstract: A bipolar power device and a fast diode are formed in a single chip of semiconductor material. The chip contains a first area having high minority carrier lifetimes in which the bipolar power device is formed. The bipolar power device is therefore capable of handling high current densities. At least one second area of the device is formed with reduced minority carrier lifetimes, with a fast diode being formed in this region.

Abstract: An integrated array of minute transistors, or cells, either of the type having emitters in the form of a mesh and bases in the form of islands, or of the type having emitters in the form of islands and bases in the form of a mesh. When a transistor chip of conventional design was connected to an inductive load such as a transformer or motor and turned off, the outer cells of the chip were more susceptible to breakdown than the inner ones. In order to make all the cells equally resistive to turnoff voltages, a first set of base openings in an insulating film on the semiconductor substrate, through which are exposed the bases of the inner cells are made larger in size than a second set of base openings in the insulating film exposing the bases of the outer cells. Additionally, in a transistor chip having meshed emitters, the peripheral annular part of the mesh is made less in width than each strip of the inner part of the mesh.

Abstract: The feeds to the emitter, base, and collector of an RF power transistor (source, drain, gate feeds of an RF FET) are configured so that negative mutual coupling therebetween is enhanced and positive mutual coupling therebetween is reduced. The emitter and base feeds include elongated portions which are generally parallel to each other with bonding pads provided on the elongated portions so that emitter and base currents flow in the same direction in the elongated portions and in the same direction as collector currents below. Interdigitated contact fingers extend from the elongated portions and contact the emitter region and the base region, respectively. When positive coupling of collector current and emitter current to the controlling base current is reduced or eliminated, the major thermal imbalance problem of operating RF transistors is also reduced or eliminated. Performance, linearity, efficiency, gain, and ruggedness are all enhanced in devices designed to utilize this invention.

Abstract: Relatively constant current sources and current mirrors are formed with vertical bipolar transistors operated in the inverse mode. In one embodiment of the invention, an integrated circuit current mirror includes a dual collector vertical NPN bipolar transistor having first and second regions of one conductivity type defining first and second collector regions, respectively, formed within a common third region of opposite conductivity type defining the base of the transistor. The third region is formed within a fourth region defining the emitter of the transistor. The structure of the dual collector vertical transistor is very compact since the two collectors share the same base region which is embedded in a common emitter (inverse collector) pocket. The "inverse" mode vertical transistor can function as a relatively constant current source with a voltage drop (VCEi) across its collector-to-emitter which is substantially less than that of a bipolar transistor operated in a normal mode.

Abstract: A bipolar transistor of the multi-emitter type which is provided with a large number of emitter diffusion layers formed in the two-dimensionally arranged state on a base diffusion layer of a substrate, a large number of emitter electrode films formed respectively correspondingly on the emitter diffusion layers, a base electrode film formed on the base diffusion layer, and a collector electrode film formed on the substrate, and the transistor is further provided with a wiring film commonly connected to the large number of emitter electrode films except at least one of the emitter electrode films.

Abstract: A semiconductor structure (30) is provided for electrostatic discharge protection. A first bipolar transistor (Q1) has a collector electrically coupled to a first node (12), a base electrically coupled to a second node, and an emitter electrically coupled to a third node (14). A second bipolar transistor (Q2) has a collector, a base electrically coupled to the second node, and an emitter electrically coupled to the first node (14). The second bipolar transistor (Q2) supplies a base current to the base of the first bipolar transistor (Q1) in response to the first node (12) reaching a threshold voltage relative to the third node (14), so that the first bipolar transistor (Q1) conducts current between the first (12) and third (14) nodes in response to the base current.

Abstract: A monolithic integrated power transistor chip includes a plurality of transistor cells arranged in two opposite and mutually spaced rows. Each cell has emitter- and collector connection spots arranged side-by-side and connected to corresponding branch conductors directed by rows of connection points extending along opposite edges on the upper surface of the chip.

Abstract: A thyristor (38) is formed over an insulating layer (44). A gate (70) is operable to create a depletion region through the semiconductor layer (46) in which the thyristor (38) is implemented in order to turn the thyristor off. Isolation regions (48, 52) prevent operation of the thyristor from affecting adjacent devices.