Abstract: In a BJT ESD protection structure, the ESD current density is stabilized by partially blocking one or more of the emitter and n+ collector, sinker, and n-buried layer to define a comb-like structure for the partially blocked regions.

Abstract: An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.

Abstract: The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A field effect transistor (FET) is disclosed that includes a heat spreader adapted to reduce the thermal resistance and channel operating temperature of a field effect transistor used in a circuit block susceptible to self-heating effects. In one embodiment, regulatory circuit blocks of an integrated circuit, such as phase locked loops, utilize the FET to improve the characteristics of a regulatory output required by other circuit blocks, such as digital logic circuits. In one embodiment the FET is a silicon-on-insulator structure.

Abstract: A thermal and electrical interconnect for heterojunction bipolar transistors is disclosed wherein the interconnect is essentially comprised of gold and in thermal and electrical contact with each of the interdigitated emitter fingers and is capable of transporting heat fluxes between 0.25-1.5 mW/&mgr;m2. The interconnect is electrodeposited to form a low-stress interface with the emitter finger, thereby increasing the lifetime and reliability of the transistor.

Abstract: A transistor includes a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of the first type (P+) of conductivity inside the substrate region (14) and adjacent to a first terminal (C) of the transistor, a well (11) of second type (N) of conductivity placed inside the substrate region (14), wherein the well (11) of second type (N) of conductivity includes at least a second contact region (12) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions (10) of the first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E1, . . . , E3) of the transistor interposed each one (10) and other (12) by proper insulating shapes (20).

Abstract: The invention provides a bipolar transistor attaining large MSG and a method of fabricating the same. The bipolar transistor of this invention includes a collector layer; abase layer deposited on the collector layer; and a semiconductor layer deposited on the base layer in the shape of a ring along the outer circumference of the base layer, the semiconductor layer includes a ring-shaped emitter region functioning as an emitter, and the outer edge of the emitter region and the outer edge of the base layer are disposed in substantially the same plane position.

Abstract: Formed on the surface of an n-type semiconductor layer (21) taken as a collector region is a base region (22) consisting of a p-type region, and formed in the p-type region is an emitter region (23) consisting of an n+-type region. Further, provided in the base region is a base electrode connecting portion (24) consisting of an n+-type region, and a base electrode (26) is connected to the surface of the base electrode connecting portion, and an emitter electrode (27) and a collector electrode (28) are provided and connected electrically to the emitter region and the collector region (21), respectively. As a result, a semiconductor device is obtained which has the transistor in which the reduction in power consumption with a high withstand voltage can be achieved, and the fast switching speed is possible and the large current is obtained. Further a voltage-drive type bipolar transistor such as a digital transistor is obtained which is small in load capacity while establishing a desired drive voltage.

Abstract: A semiconductor amplifier includes collector straps that form air bridges over a set of transistors and make parallel electrical connections between the collectors of the transistor and collector contact pad. Base straps establish base bias and electrically connect a dc current source with bases of the transistors through resistive elements.

Abstract: A high-frequency semiconductor amplifier circuit minimizing deterioration of high-frequency characteristics and attaining high thermal stability. A driver stage of a power amplifier has a multi-stage configuration with multi-finger HBTs connected in shunt with each other, each multi-finger HBT having a single emitter. An output stage has a single stage configuration multi-finger HBTs connected in shunt with each other, each HBT including two emitters. As a result, while an increase in capacitance of a p-n junction between an emitter layer and a base layer of the driver stage is prevented, thermal nonuniformity arising in the output stage is minimized. Thus, a power amplifier as a whole is configured with high thermal stability without deterioration of a high-frequency characteristic of the power amplifier.

Abstract: A thermal and electrical interconnect for heterojunction bipolar transistors is disclosed wherein the interconnect is essentially comprised of gold and in thermal and electrical contact with each of the interdigitated emitter fingers and is capable of transporting heat fluxes between 0.25-1.5 mW/&mgr;m2. The interconnect is electrodeposited to form a low-stress interface with the emitter finger, thereby increasing the lifetime and reliability of the transistor.

Abstract: A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electrically isolated and spatially separated from each other. The plural divided sub-emitter regions may typically have a uniform emitter size identical with a basic emitter size of the basic bipolar transistor. A set of the plural divided sub-emitter regions provides an intended emitter current distinctly larger than the basic emitter current by a highly accurate direct current amplification factor corresponding to an intended emitter-size magnification factor.

Abstract: A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.

Abstract: A semiconductor chip 10 is provided to form a large number of cells constituting transistor units arranged on a planar and rectangular semiconductor substrate. On the front surface of the semiconductor chip 10, an emitter electrode 1 to be connected to an emitter and a base electrode 2 to be connected to an base are formed and electrode pads 1a and 2a of the emitter electrode 1 and the base electrode 2 are formed on opposite long sides of the rectangular substrate. On the rear surface of the semiconductor chip 10, a collector electrode 3 to be connected to a collector is formed. The semiconductor chip 10 is bonded to a rectangular island 6a at the tip of a third lead 6. A first lead 4 and a second lead 5 are directly connected to the emitter electrode pad 1a and base electrode pad 2a, respectively.

Abstract: According to the object, the present invention provides an electrostatic discharge (ESD) circuit, coupled between a pad and a power line. The ESD protection circuit comprises a bipolar junction transistor (BJT) . The BJT comprises a collector region having a first conductivity type, formed in a substrate, in contact with a buried layer having the first conductivity type, and coupled to the pad to become the collector of the BJT, a base region having the second conductivity type, formed on the buried layer to become the base of the BJT, and an emitter having the first conductivity type, formed in the base region and coupled to the power line to become the emitter of the BJT. The emitter has a plurality of parallel first regions and a second region connecting the first regions.

Abstract: A plurality of MOS transistors are arranged on the top surface of a conductor substrate which is a drain electrode. The drain contact of each MOS transistor is connected to the conductor substrate. The source contact of each MOS transistor is connected to the output conductor path which is a source electrode through a bonding wire. The gate contact of each MOS transistor is connected to a drive signal conductor path which is a gate electrode through a bonding wire. The source contacts of the MOS transistors are interconnected through a bridge electrode and a bonding wire.

Abstract: Performance of an RF power bipolar transistor having a collector region, at least one base region, and a plurality of elongated emitter fingers in each major region, is enhanced by forming each emitter finger with at least two spaced segments and contacting the two spaced segments with a metal lead. By eliminating the middle portion of each emitter finger, current hogging at the central portion and hot spot generation are eliminated. Power output is maintained with reduced emitter lengths by minimizing the adverse affects of the hot spot generation in the emitters.

Abstract: A semiconductor device of the present invention includes ohmic source plate electrodes, gate plate electrodes, and drain plate electrodes in parallel from each other in a heat generating region various designs are used to more evenly distribute heat generated in the semiconductor device. A first example has gold-plate electrodes formed on the respective source and drain plate electrodes in parallel with the ohmic plate electrodes. The gold-plate electrode arranged at the central portion of the heat generating region plate electrodes has the widest width and gold-plate electrodes arranged toward the center portion to the peripheral portion of the heat generating region narrow gradually. By the structure mentioned above, the semiconductor device of the present invention has uniform temperature distribution in a heat generating region. A second example uses a plurality of stripe plates perpendicular to the ohmic plate electrodes.

Abstract: A power transistor comprising a collector region formed in a semiconductor substrate, a base region formed within the collector region, and a hoop-shaped emitter region formed within the base region. The hoop-shaped emitter region divides the base region into an external section and at least one internal section surrounded by the emitter region on the substrate surface, the external and internal base sections being connected within the substrate. A base contact is formed on the surface of each internal base section surrounded by the emitter region. By this design, the electric current is more uniform within the emitter region, and safe operating area (SOA) destruction can be prevented. The invention is also directed to semiconductor integrated circuit devices using the above power transistor, and a method of forming the same.

Abstract: A power transistor includes a plurality of emitter regions and a plurality of base contacts. In order to decrease base resistance, each of the plurality of emitter regions is adjacent to at least four base contacts. The entire transistor includes multiple emitter regions, e.g., greater than or equal to about 1,000 with no upper limit wherein the actual number of emitter regions is dependent on the desired current carrying capacity. The emitter regions are directly connected in parallel to the high current carrying metal layer of the transistor through vias or metal contact studs. The size of the emitter regions should be made as small as the process design rules will allow in order to allow an increase in the perimeter to area ratio of the emitter region which, for a given current, decreases the peak current density.

Abstract: A vertical PNP transistor integrated in a semiconductor material wafer having an N type substrate and an N type epitaxial layer forming a surface. The transistor has a P type buried collector region astride the substrate and the epitaxial layer; a collector sinker insulating an epitaxial tub from the rest of the wafer; a gain-modulating N type buried base region astride the buried collector region and the epitaxial tub, and forming a base region with the epitaxial tub; and a P type emitter region in the epitaxial tub. An N.sup.+ type base sinker extends from the surface, through the epitaxial tub to the buried base region. The gain of the transistor may be modulated by varying the extension and dope concentration of the buried base region, forming a constant or variable dope concentration profile of the buried base region, providing or not a base sinker, and varying the form and distance of the base sinker from the emitter region.

Abstract: A bipolar transistor (3) is provided with a first main surface (4) in contact with a conductive mounting surface (2), and with an opposed second main surface (12) having connection pads (5, 6, 40) for an emitter, base, and collector. The lateral dimensions of the conductive mounting surface (2) are practically equal to the dimensions of the first main surface (4) of the transistor (3), and may thus be relatively small. The high-frequency properties of the transistor (3) are strongly determined by the size of the conductive mounting surface (2), which through an insulating substrate (1) forms a parasitic capacitance with a conductive ground surface (18), which capacitance is connected to the transistor (3). This parasitic capacitance is very important especially for high-frequency applications. Furthermore, the bonding wires (E, B) for the connection pads of emitter and base are shorter than in the prior art because they need not pass over a relatively large conductive mounting surface (2).

Abstract: The present invention relates to a contact window structure having an insulation layer extending over an electrically conductive region. The insulation layer further has a plurality of contact windows which are filled with electrically conductive layers so that the electrically conductive layers are made into contact with the electrically conductive region so as to allow a contact portion of a probe to contact with at least one of the electrically conductive layers within the contact windows, wherein adjacent two of the contact windows are distanced from each other by a distance which is substantially equal to or narrower than a diameter of the contact portion of the probe, whereby the contact portion of the probe is necessarily made into contact with at least any one of the electrically conductive layers within the contact windows. There is no possibility that the contact portion of the probe is not made into contact with any electrically conductive layers.

Abstract: A unit transistor forming a power transistor includes a collector region, a base region, and an emitter region. A base contact portion is formed at a prescribed portion on the base region. The base region has a convex portion, which projects in the direction toward the emitter region, at a portion where the base contact portion is formed. The emitter region has, at a portion where the base region projects, a convex portion projecting in the same direction as the direction in which the base region projects. The base region has, at a portion where the emitter region projects, a concave portion. A base resistor region is expanded by the convex portion provided at the emitter region, thereby increasing the resistance value of the base resistor R.sub.B. Consequently, a power transistor having a wide area of safety operation and capable of performing operation in a stable manner can be obtained without an increase in size of the transistor.

Abstract: A semiconductor device includes an emitter region, a contact region, and a resistive medium. The resistive medium is connected between the contact region and the emitter region. The contact region and the emitter region each include an edge facing each other. At least a portion of the emitter region edge and at least a portion of the contact region edge are non-parallel relative to each other. This configuration enables an emitter ballast resistance to be provided with varied emitter current flow along the injecting edge of the emitter. Furthermore, by including an additional contact and an additional resistive medium between the contacts, the ballast resistance of the semiconductor device can be increased without decreasing the figure of merit of the device.

Abstract: A semiconductor device provided with a semiconductor substrate with a bipolar transistor having a collector region of a first conductivity type, a base region adjoining the collector region and of a second conductivity type opposed to the first, and an elongate emitter region of the first conductivity type adjoining the base region; the collector region, the base region, and the emitter region being provided with conductor tracks which are connected to conductive connection surfaces. The conductor track on the elongate emitter region of the semiconductor device has a connection to a connection surface for a further electrical connection at each of the two ends of the emitter region. The emitter region may be made longer in this manner because the length of the emitter region is effectively halved by the connections at the two ends. Consequently, charge carriers need be transported over no more than at most half the emitter length.

Abstract: An integrated structure is made in a chip of semiconductor material inside an insulated N type region extending from a surface of the chip. The structure comprises a Zener diode formed by a P type first region extending from the surface inside the insulated region and by a second region of type N extending from the surface inside the first region. These regions form between themselves a buried junction, in which the structure further includes a lateral bipolar transistor having an emitter region provided by the first region.

Abstract: A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.

Abstract: A base region and an emitter region are formed at a surface of an n-well region (collector region). A contact hole reaching a portion of the surface of the collector region is formed, a contact hole reaching a portion of the surface of the emitter region is formed, and a contact hole reaching a portion of the surface of the base region is formed. A collector electrode, an emitter electrode and a base electrode are formed in the contact holes, respectively. Assuming that L represents a longitudinal length of the contact hole accommodating the emitter electrode and S represents a width thereof perpendicular to the longitudinal direction, a value of L/S is 10 or more. Thereby, a collector resistance of a bipolar transistor can be reduced, and a manufacturing cost can be reduced.

Abstract: A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region, a base region overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried region a surface region, and a first vertical diffusion region connecting the buried layer to the surface region. A second vertical diffusion region connects the buried emitter layer periphery to a first surface contact, while the surface emitter region is contacted, along three peripheral sides thereof, by a second surface contact. The transistor current flows from the substrate, through the base to the buried emitter region. It is then conveyed into the vertical region, which represents a resistive path, and on reaching the surface region splits between two resistive paths included between the vertical region and the surface contacts.

Abstract: The present invention relates to a heterojunction bipolar transistor structure having a device mesa 401 with a collector region 402, a base region 403 and an emitter region 404. An emitter metal layer 405 is connected to a ballast resistor 406 which in turn is connected to an emitter bump 407 by way of the air bridge 408. The thermal bump 409 is connected to the emitter metallization by way of a layer of heat dissipation material 410, preferably silicon nitride. The present structure enables dissipation of heat at the emitter contact as well as a ballast resistor connected to the emitter by way of metallization 405. This arrangement enables the dissipation of joule heat to avoid higher temperature of operation which results increased current at the collector which increases the temperature thereby further increasing the current, as well as provides a ballast resistor to reduce the collector current back to an acceptable value to avoid thermal runaway.

Abstract: A bipolar transistor designed to support a substantially uniform current density in base and collector regions to prevent the characteristic early fall-off of bipolar transistor current gain, and to improve the forward safe operating area performance. The advantages of the present invention are achieved by optimally spacing the neighboring emitters in relation to base thickness and further by maintaining a symmetrical topology by the self-aligned formation of emitters and base contacts. The spacing distance between the neighboring emitters does not exceed the base thickness. As a result, the current density below each emitter island is substantially uniform and the transistor as a whole can conduct a higher total current. Moreover, the transistor inhibits formation of current filaments and hot spots because the electric field in the collector region is uniform.

Abstract: The present invention, generally speaking, provides an apparatus and method whereby the current flow through an RF power transistor may be monitored without the use of any external parts. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, a pair of interdigitated electrodes formed on the silicon die, each having a multiplicity of parallel electrode fingers and at least one bond pad. Regions of a first type of diffusion are formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion are formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes. One electrode has multiple electrode fingers and multiple resistors formed on the silicon die, at least one resistor connected in series with each one of the electrode fingers.

Abstract: A lateral IGBT has a n-source layer and a p-contact layer both in contact with a source electrode. The source layer has a trunk adjacent to a channel region under a gate electrode, and a plurality of branches extending from its trunk to the source electrode to be in contact with the source electrode. The contact layer has a trunk in contact with the source electrode, and a plurality of branches extending from its trunk to the source layer trunk The source layer branches and the contact layer branches have shapes complementary with each other and are alternately arranged. The source layer trunk has a width La in an X direction (channel direction), which satisfies a condition, 0.5 .mu.m<La<2 .mu.m.

Abstract: Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.

Abstract: A silicon bipolar junction transistor in integrated form is disclosed having a ballast resistance integrated onto a silicon chip. This resistance is for the purpose of thermal stability. In addition, a bypass capacitance circuit is placed in parallel with the ballast resistance again in integrated form. The silicon BJT is flip-chip mounted on a heterolithic microwave integrated circuit glass substrate having the integrated bypass capacitor circuit fabricated directly thereon. This bypass capacitor circuit is electrically in contact with the emitter fingers of the bipolar junction transistor.

Abstract: The present invention implements a novel emitter scheme that maximizes the emitter perimeter to emitter area ratio of an integrated circuit transistor, thereby achieving improved low noise characteristics over the prior art. Emitter regions are disposed in the transistor in discrete "dotted " segments. The dotted emitter segments may be realized by etching into emitter regions defined by an appropriately formed photoresistive overlay, which can be modified without fabrication process changes. The effect is to reduce the total emitter area by half, while maintaining the total emitter perimeter unchanged. As a result, the noise-capacitance product of the transistor is reduced, improving the overall performance of the transistor.

Abstract: Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor structure having a small surface area to minimize parasitic capacitance, whereby resistor and capacitor surface areas of 100 square micrometers or less are obtained. Another feature of the invention is the use of a high dielectric material in realizing a resistor-capacitor impedance zero at a frequency much lower than the operating frequency of the transistor. For an operating frequency of 2 GHz and resistor values of 50-250 ohms, capacitance required is 3 pF or greater. Another feature of the invention is a method of fabricating the integrated resistive-capacitive element in either a low temperature process or a high temperature process which minimizes capacitor leakage when using a thin high dielectric insulative material between capacitor plates.

Abstract: A bipolar semiconductor integrated circuit has a pnp transistor through which a DC power is supplied from an external DC power to various elements of the bipolar IC and a constant current circuit for turning the pnp transistor on and regulating the base current of the pnp transistor to a constant level causing operation in the saturation range of the pnp transistor.

Abstract: An RF power transistor having improved thermal balance characteristics includes a first emitter electrode and a base electrode formed on a silicon die, each having a multiplicity of parallel electrode fingers. A second emitter electrode is formed over the base electrode, and is electrically connected to the first emitter electrode. Ballast resistors are formed in a substantially evenly spaced manner on each side the silicon die, in series with at least some of the electrode fingers of the first emitter electrode and in series of at least some of the electrode fingers of the second emitter electrode.

Abstract: An electrode lead of a transistor extends beyond other electrode leads of the transistor, is disposed adjacent to the corresponding electrode, and is disposed outside the other electrode leads for heat radiation. A wider part of the electrode lead may have a via hole or a thick metal plating for heat radiation. Further, the electrode is preferably grounded and is connected to an external input terminal to which heat is transferred.

Abstract: A novel ring shaped emitter structure with an extrinsic base and base contact in the central portion of the ring is described. This structural configuration is useful for improving the performance of bipolar transistors used in BiCMOS integrated circuits with only minimal changes to conventional CMOS processing technology. A single additional mask is required to form the intrinsic base region of the transistor. The emitter is diffused from a polysilicon layer which also serves as the emitter contact. The polysilicon layer overlies a perimeter portion of an active region defined by an opening in a field oxide and rises up over the field oxide itself. The active emitter region then forms a ring along the perimeter of the active region. The extrinsic base is formed through an opening within the polysilicon layer representing a central portion of the active region.

Abstract: Structure and fabrication details are disclosed for AlGaAs/GaAs microwave HBTs having improved thermal stability during high power operation. The use of a thermal shunt joining emitter contacts of a multi-emitter HBT is shown to improve this thermal stability and eliminate "current-crush" effects. A significant reduction in thermal resistance of the disclosed devices is also achieved by spreading the generated heat over a large substrate area using thermal lens techniques in the thermal shunt. These improvements achieve thermally stable operation of AlGaAs/GaAs HBTs up to their electronic limitations. A power density of 10 mW/.mu.m2 of emitter area is achieved with 0.6 W CW output power and 60% power-added efficiency at 10 GHz. The thermal stabilization technique is applicable to other bipolar transistors including silicon, germanium, and indium phosphide devices.

Abstract: The present invention implements a novel emitter scheme that maximizes the emitter perimeter to emitter area ratio of an integrated circuit transistor, thereby achieving improved low noise characteristics over the prior art. Emitter regions are disposed in the transistor in discrete "dotted" segments. The dotted emitter segments may be realized by etching into emitter regions defined by an appropriately formed photoresistive overlay, which can be modified without fabrication process changes. The effect is to reduce the total emitter area by half, while maintaining the total emitter perimeter unchanged. As a result, the noise-capacitance product of the transistor is reduced, improving the overall performance of the transistor.

Abstract: A semiconductor device implemented using a transistor (Q1) including at least one emitter (E1) and a transistor (Q2) which is larger than the transistor (Q1) including n emitters (E21 to E2n) each having the same area as the emitter (E1) of the transistor (Q1). The emitter (E1) of the transistor (Q1) is disposed between the emitters (E21 to E2n) of the transistor (Q2). When there is deflection of a substrate due to a stress to cause distortion in shape of the emitters, the emitter (E1) has much less distortion in shape than the emitters located on the end portions of the row region in the longitudinal direction. Since the transistor (Q2) has a number of emitters, the distortion in shape of the emitters (E21 to E2n) of the transistor (Q2), if any, has little effect on the whole.

Abstract: A transistor includes (a) a first semiconductor layer formed by a semiconductor substrate; (b) a second semiconductor layer formed on the first semiconductor layer and having an impurity of the same conductivity type as the first layer in a concentration lower than that of the first semiconductor layer; and (c) a third semiconductor layer formed on the second semiconductor layer having an impurity of the same conductivity type as the first semiconductor layer in a concentration lower than that of the second semiconductor layer. A base region is formed in the third layer and an emitter region is formed in the base region.

Abstract: A self-aligned fully-walled monocrystalline silicon emitter-base structure for a bipolar transistor and methods for producing the structure are provided. The methods involve creating an oxide side wall surrounding a monocrystalline silicon emitter-base structure by first defining the emitter region in a base island region. Successive oxide layers are deposited on top of the emitter region and etched back to produce an oxide wall around the entire perimeter of the emitter region. In a preferred embodiment of the invention a metal silicide is also formed across the top of the base island region of the semiconductor outside of the emitter region. Since the extrinsic base region, outside of the oxide sidewalls, is entirely covered by a low resistance silicide film, the base contact area can be significantly reduced compared to prior art devices.The process results in a fully-walled emitter-base structure made of monocrystalline silicon which exhibits improved high-frequency performance.

Abstract: An insulating film formed on a base region is patterned to form emitter contact holes and base contact holes arranged alternately in such a manner that those contact holes are short in the center portion and become longer toward the peripheral portions, and to form emitter regions which are aligned with the emitter contact holes. This structure can suppress the current concentration on the center portion of a transistor without using a ballast resistor, thus ensuring a high-output operation, and can improve the transfer gain. The elimination of such a ballast resistor results in an increased effective utilization area and a simplified fabrication.

Abstract: A bipolar transistor of the multi-emitter type which is provided with a large number of emitter diffusion layers formed in the two-dimensionally arranged state on a base diffusion layer of a substrate, a large number of emitter electrode films formed respectively correspondingly on the emitter diffusion layers, a base electrode film formed on the base diffusion layer, and a collector electrode film formed on the substrate, and the transistor is further provided with a wiring film commonly connected to the large number of emitter electrode films except at least one of the emitter electrode films.