Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Abstract: A substrate has a collector region of a first conductivity type, and a base layer of a single crystalline structure and including impurities of a second conductivity type is located over the collector region. An emitter region is defined at least in part by impurities of the first conductivity type contained in the base layer. An emitter electrode of the first conductivity type contacts the emitter region, and at least a portion of the emitter electrode which is in contact with the emitter region has a single crystalline structure.

Abstract: A semiconductor device has a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region and a second conductivity-type third semiconductor region both located on or above the first semiconductor region, a second conductivity-type fourth semiconductor region between the second semiconductor region and the third semiconductor region, and a first conductivity-type fifth semiconductor region between the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region and the fifth semiconductor region are electrically connected by a conductive member. A distance between the fourth semiconductor region and the third semiconductor region is larger than a width of the fourth semiconductor region.

Abstract: A cascode of a high-frequency circuit, includes a first transistor having a first base semiconductor region, a first collector semiconductor region and a first emitter semiconductor region, and a second transistor having a second base semiconductor region, a second collector semiconductor region and a second emitter semiconductor region. The first emitter semiconductor region of the first transistor and the second collector semiconductor region of the second transistor are geometrically arranged on top with respect to a wafer surface, while the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor are geometrically arranged on the bottom with respect to the wafer surface.

Abstract: A bipolar transistor includes a collector located over a substrate; and a heat conductive path connecting the substrate to the collector. The heat conductive path is filled with a heat conductive material such as metal or polysilicon. In one embodiment the heat conductive path runs through the collector to extract heat from the collector and drain it to the substrate. In alternate embodiments, the transistor can be a vertical or a lateral device. According to another embodiment, an integrated circuit using BiCMOS technology comprises pnp and npn bipolar transistors with heat conduction from collector to substrate and possibly p-channel and n-channel MOSFETS. According to yet another embodiment, a method for making a transistor in an integrated network comprises steps of etching the heat conducting path through the collector and to the substrate and fill with heat conductive material to provide a heat drain for the transistor comprising the collector.

Abstract: The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.

Abstract: A device. The device includes two bipolar transistors electrically connected to each other. Each bipolar transistor of the two bipolar transistors may include a base contact and an emitter contact surrounding the base contact, wherein the emitters contacts of the two bipolar transistor are in electrical contact with each other. A first bipolar transistor of the two bipolar transistors may have a first wiring stack and a second bipolar transistor two bipolar transistors may have a second wiring stack, wherein the second wiring stack includes at least one more wiring level than the first wiring stack.

Abstract: A method for forming a semiconductor package is provided. In one embodiment, the method comprises providing a semiconductor substrate having at least one bump pad formed thereon. A solder mask layer is provided above the bump pad, the solder mask layer having at least one opening formed therein exposing a portion of the bump pad. A layer of solder wettable material is formed on the exposed surface of the bump pad and the sidewalls and substantially on the comers of the solder mask layer. A solder material is deposited above the layer of solder wettable material and portions of the solder mask layer and the solder material is reflown to create a solder bump.

Abstract: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.

Abstract: Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching speed and current gain of bipolar transistors. Current fabrication techniques involve high temperature procedures that melt desirable low-resistance substitutes, such as aluminum, during fabrication. Accordingly, one embodiment of the invention provides an emitter contact structure that includes a polysilicon-carbide layer and a low-resistance aluminum, gold, or silver member to reduce emitter resistance. Moreover, to overcome manufacturing difficulties, the inventors employ a metal-substitution technique, which entails formation of a polysilicon emitter, and then substitution or cross-diffusion of metal for the polysilicon.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductive type, a collector layer formed on the semiconductor substrate and made of a first semiconductor being of the first conductive type and having a higher resistance than that of the semiconductor substrate, an intrinsic base region having a junction surface with the collector layer and made of a second semiconductor of a second conductive type, and an emitter region having a junction surface with the intrinsic base region and made of a third semiconductor of the first conductive type. A periphery of the intrinsic base region is surrounded by an insulating region extending from the collector layer to the semiconductor substrate.

Abstract: The invention relates to a manufacturing method for an insulated gate semiconductor device cell, comprising the steps of forming a cell window (3) in a layered structure that is located on top of a semiconductor substrate (1), forming at least one process mask that partially covers the cell window (3). In forming the cell window (3), at least one strip (41, 42) of the layered structure is left to remain inside the cell window (3) and at least one strip (41, 42) is used to serve as an edge for the at least one process mask (51, 52). The invention further relates to an insulated gate semiconductor device, comprising a semiconductor substrate (1) having an essentially planar top surface and an insulated gate formed on the top surface by a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41, 42) of the layered structure (2) is disposed on a third area of the top surface between an edge of the insulated gate and a first main contact (6).

Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.

Abstract: A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric layer juxtaposed on at least the total surface of the emitter region and adjoining portions of the surface of the base region. A portion of the field plate layer is removed to expose a first portion of the emitter surface. A second dielectric layer is formed over the field plate layer and the exposed portion of the emitter. A portion of the second dielectric layer is removed to expose the first portion of the emitter surface and adjoining portions of the field plate layer. A common contact is made to the exposed first portion of the emitter surface and the adjoining portions of the field plate layer. In another embodiment, the field plate and emitter contact are formed simultaneously.

Abstract: A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.

Abstract: A Low Noise semiconductor amplifier structure formed from layers of differently doped semiconductor material. This structure when properly biased will amplify voltage signals applied to the input terminal (Base1 or signal-base), and provide the same signal, amplified at the terminal designated as the output or collector. The semiconductor material can be any of a number of semiconductor materials, Germanium, Silicon, Gallium-Arsenide or any material with suitable semi-conducting properties. The structure can be any BJT (Bipolar Junction Transistor) form. The presence of an additional, distinct highly doped layer indicated as Base2 in the BJT form, provides an electrical noise suppression function. This inhibits intrinsic electrical noise, and improves the high frequency performance of the device in conjunction with an external capacitor connected to this new Base2 (or anti-base) region.

Abstract: A compression assembled semiconductor package for housing a power semiconductor die which includes two major pole pieces in intimate electrical contact with respective major electrodes of a power semiconductor die. The package includes a plastic molded insulation ring disposed around the power semiconductor die. The pole pieces are secured to respective ends of the plastic molded insulation ring. One of the pole pieces may include an annular flange that penetrates the plastic molded insulation ring from an interior wall thereof and is embedded in its body. The annular flange preferably comprises a projection having a squared tab and circular distal end that is received by a receiving groove having a notch (to receive the squared tab) and a cavity (to receive the distal end).

Abstract: An amplifier GaAs MMIC for microwave band applications includes a ground electrode 8 having a via hole group 12 composed of three via holes 11 filled with plated metals 10a that are formed adjacently. The interaction thereby generates high frequency electromagnetic bonding, which reduces the ground inductance. According to the MMIC, the ground inductance of the via hole may be reduced while decrease of a strength and increase of a size being restrained.

Abstract: A substrate has a collector region of a first conductivity type, and a base layer of a single crystalline structure and including impurities of a second conductivity type is located over the collector region. An emitter region is defined at least in part by impurities of the first conductivity type contained in the base layer. An emitter electrode of the first conductivity type contacts the emitter region, and at least a portion of the emitter electrode which is in contact with the emitter region has a single crystalline structure.

Abstract: The gist of the present invention is as follows: In a monolithic microwave integrate circuit (MMIC) using a heterojunction bipolar transistor (HBT), via holes are respectively formed from the bottom of the MMIC for the emitter, base and collector. Of the via holes, one is located so as to face the HBT. The respective topside electrodes for the other via holes located so as not to face the HBT are provided in contact with the MMIC substrate.

Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.

Abstract: A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n? polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

Abstract: In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base terminal is formed on the substrate surface, and an emitter window having a wall area is formed in the base-terminal layer. A first spacing layer is formed on the wall area of the emitter contact window, and a recess is etched into the substrate within a window specified by the first spacing layer. A base layer contacted by outdiffusion from the base-terminal layer is formed in the recess of the emitter window, and a second spacing layer is formed on the first spacing layer and on the base layer. The second spacing layer is structured for the purpose of specifying a planar terminal pad on the base layer, and an emitter layer is formed on the planar terminal pad.

Abstract: A semiconductor package in which solder balls can be loaded on an encapsulated resin to reduce the package area and a method for producing the semiconductor package. An apparatus for carrying out the method includes a first insulating substrate 5 carrying a mounting portion 3 for mounting a semiconductor device 2 and a first electrically conductive pattern 4 electrically connected to the semiconductor device 2, a sidewall section 6 formed upright around the mounting portion of the first insulating substrate, a cavity 7 defined by the first insulating substrate 5 and the sidewall section and encapsulated by an encapsulating resin 12 as the semiconductor device 2 is mounted on the mounting portion 3 and a second insulating substrate 10 provided in the cavity 7 and on the sidewall section 6 and carrying a second electrically conductive pattern 31 electrically connected to the first electrically conductive pattern 4 via plated through-holes 26 formed in the sidewall section 6.

Abstract: A bipolar transistor having a base contact surrounded by an emitter contact. A plurality of wires extending from the base contact and the emitter contact of the bipolar transistor, wherein the wires of the base contact are stacked higher than the wires of the emitter contact. A device comprising a plurality of these bipolar transistors, wherein at least one side of each emitter contact abuts each adjacent transistor. Increasing the wiring stack of each row of transistors in the device as the distance between the row and the current input increases.

Abstract: A semiconductor device with high structural reliability and low parasitic capacitance is provided. In one example, the semiconductor device has a surface. The semiconductor device comprises a semiconductor region, wherein an emitter region, a base region, and a collector region are laminated from a side near a substrate of the semiconductor region; an insulating protection layer disposed on the surface; and a wiring layer disposed on the surface, the insulating protection layer forming a via hole from the side of the substrate of the semiconductor region, the via hole being formed to allow the wiring layer to make a contact to an electrode of the emitter region from a side of the substrate where the emitter region, the base region, and the collector region are laminated and where the semiconductor region is isolated.

Abstract: A MEM tunneling gyroscope assembly includes (1) a beam structure, and a mating structure defined on a first substrate or wafer; and (2) at least one contact structure, and a mating structure defined on a second substrate or wafer, the mating structure on the second substrate or wafer being of a complementary shape to the mating structure on the first substrate or wafer; and (3) a bonding layer is disposed on at least one of said mating structures for bonding the mating structure defined on the first substrate or wafer to the mating structure on the second substrate or wafer.

Abstract: The present disclosure provides a deep submicron electrostatic discharge (ESD) protection structure for a deep submicron integrated circuit (IC) and a method for forming such a structure. The structure includes at least two electrodes separated by a dielectric material, such as a thin gate oxide layer. In some examples, the thin gate oxide may be less than 25 ? thick. A source and drain are positioned proximate to and on opposite sides of one of the electrodes to form a channel. The drain is covered with a silicide layer that enhances the ESD protection provided by the structure. The source may also be covered with a silicide layer. In some examples, the drain may be floating.

Abstract: A semiconductor device and a method for manufacturing the device using a semiconductor substrate of a high resistance with improved Q value of a passive circuit element. Leakage current due to an impurity fluctuation, in the high resistance semiconductor substrate and noise resistance of an active element in the high resistance semiconductor substrate are improved. The semiconductor device includes a bipolar transistor at a main surface of and in the semiconductor substrate. The bipolar transistor includes a semiconductor layer of a first conductivity type at a bottom portion of the bipolar transistor and the semiconductor device includes a buried layer of a second conductivity type, located in the semiconductor substrate and facing the semiconductor layer of the first conductivity type.

Abstract: A semiconductor integrated circuit device has a semiconductor integrated circuit chip, a package enclosing the chip, and a plurality of conductors connecting the bonding pads of the chip to the leads of the package. The chip has an internal circuit, a plurality of bonding pads having signal paths formed between themselves and the internal circuit, and a switching circuit provided in a predetermined signal path so as to perform a switching operation to allow the internal circuit to be connected selectively to one of different bonding pads. The switching circuit is fed with an external signal to perform its switching operation in such a way as to prevent the signals passing through mutually adjacent conductors from affecting each other.

Abstract: The present invention provides a hetero-bipolar transistor having a new configuration of the interconnection. The bipolar transistor of the present invention includes the collector mesa, having the base and collector layers therein, includes a first side having a normal mesa surface and extending along the [01-1] orientation, and a second side having a reverse mesa surface and extending along the [011] orientation. The present HBT has a base interconnection, a portion of which diagonally intersects the first side of the collector mesa, accordingly, the breaking of the interconnection may not occur and the high frequency performance of the HBT may be enhanced because the width of the collector mesa is not necessary to widen to disposed the base interconnection on the first side.

Abstract: In a bipolar double-poly transistor comprising a layer of base silicon (1?) on a silicon substrate (2?), a first layer of silicon dioxide (3?) on the base silicon layer (1?), an emitter window (4?) extending through the first layer (3?) of silicon dioxide and the base silicon layer (1?), a second layer (5?) of silicon dioxide in the emitter window (4?), silicon nitride spacers (6?) on the second layer (5?) of silicon dioxide in the emitter window (4?), and emitter silicon (9?) in the emitter window (4?), an isolating silicon nitride seal is provided to separate the base silicon (1?) from the emitter silicon (9?) to prevent short-circuiting between the base silicon (1?) and the emitter silicon (9?) in the transistor.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: A semiconductor device includes a low resistance semiconductor substrate, a high resistance semiconductor layer formed on the substrate, an insulation layer formed on the semiconductor layer, and a transistor element composed of a collector region, abase region, and an emitter region formed in the semiconductor layer. The device further includes an emitter electrode formed in the insulation layer to be connected to the emitter region, a sub-emitter electrode formed in the insulation layer connected to the emitter electrode, a low resistance impurity-diffusion region formed in the semiconductor layer such that the sub-emitter electrode is connected to the substrate through the impurity-diffusion region, a base electrode formed in the insulation layer to be connected to the base region, and a base-bonding pad formed on the insulation layer to be connected to the base electrode.

Abstract: A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a polysilicon emitter contact by using a single mask to define respective openings for these elements. In particular, a dielectric layer is deposited on a semiconductor wafer and has two openings defined by a single masking step, one opening above an emitter region and a second opening above a base-collector junction region. Polysilicon is deposited on the dielectric layer and selectively doped in the areas of the openings. Thus for an NPN transistor for example, the area above the emitter opening is doped N type and the area above the base/field plate opening is doped P type. The doped polysilicon is patterned and etched to leave a polysilicon emitter contact and an integrated polysilicon base contact and field plate within the respective openings.

Abstract: A method and system for providing a bipolar power transistor on a semiconductor device is disclosed. The method and system comprise providing a semiconductor substrate. The method and system includes providing an emitter base structure in the power device. The method and system further includes providing at least one oxidized slot through the emitter base structure and into the semiconductor substrate utilizing the highly inefficient portion of the emitter for this structure, thus wasted space is utilized to provide a power buss ground. This results in a smaller transistor for a given current. This is provided without any extra steps. This approach results in lower operating temperatures for a given current as compared to standard approaches.

Abstract: As external connection terminals for an emitter electrode (12) of an IGBT chip, a first emitter terminal (151) for electrically connecting a light emitter in a strobe light control circuit to the emitter electrode (12) and a second emitter terminal (152) for connecting a drive circuit for driving an IGBT device to the emitter electrode (12) are provided. The first emitter terminal (151) and the second emitter terminal (152) are individually connected to the emitter terminal (12) by wire bonding.

Abstract: A heterojunction bipolar transistor with self-aligned features having a self-aligned dielectric sidewall spacer disposed between base contact and emitter contact, and self-aligned base mesa aligned relative to self-aligned base contact. The base contact is self-aligned relative to the self-aligned dielectric sidewall spacer providing a predetermined base-to-emitter spacing thereby. The emitter may be an n-type, InP material; the base can be a p-type InGaAs material, possibly carbon-doped. The fabrication method includes forming a emitter electrode on an emitter layer; using the emitter contact as a mask, anisotropically etching the emitter exposing the base layer; forming a self-aligned dielectric sidewall spacer upon the emitter and base; self-alignedly depositing a self-aligned base electrode; using the self-aligned base electrode as a mask, anisotropically etching the base layer to expose the subcollector; and depositing a collector electrode on the subcollector layer.

Abstract: A semiconductor device includes a semiconductor substrate, an electrode disposed on an upper surface of the substrate, and a set of one or more transistor element(s) disposed on the upper surface of the substrate. The set of transistor element(s) compactly surrounds the electrode with a threshold distance. In one embodiment, the set also compactly surrounds a via hole. In another, the element(s) comprises a bipolar junction transistor that has an aggregate emitter length of not less than 10 microns. In still another embodiment, the device is coupled to a RF circuit for power amplification.

Abstract: The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This intermediary connection region is located under a trench. The manufacturing method enables forming of vertical devices, in particular fast bipolar transistors.

Abstract: A heterojunction bipolar transistor is fabricated by laminating and emitter layer, a base layer and a collector layer on a top surface of a semiconductor substrate, forming a via hole through the emitter layer, the base layer, the collector layer and the substrate at a specific depth, and providing a heat sink layer made of a metal on a rear surface of the substrate. A surface electrode of the emitter layer and the heat sink layer are connected to each other by a metal wiring line running through within the via hole, thereby improving the heat radiation and reducing the emitter inductance.

Abstract: A semiconductor device having contact surfaces of different heights electrically connected to conductors defined on one or more patterned metal planes and a method for fabricating the semiconductor device. In one embodiment, the semiconductor device comprises a substrate having a process surface; a first contact and a second contact arranged on the substrate, a second contact surface of the second contact being at a greater distance, in a substrate-normal direction, from the substrate than a first contact surface of the first contact; a first conductor disposed in a first patterned metal plane and electrically connected to the first contact surface; and a second conductor disposed in a second patterned metal plane and electrically connected to the second contact surface, wherein the second metal plane is disposed at a greater distance, in the substrate-normal direction, from the substrate than the first metal plane.

Abstract: In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base terminal is formed on the substrate surface, and an emitter window having a wall area is formed in the base-terminal layer. A first spacing layer is formed on the wall area of the emitter contact window, and a recess is etched into the substrate within a window specified by the first spacing layer. A base layer contacted by outdiffusion from the base-terminal layer is formed in the recess of the emitter window, and a second spacing layer is formed on the first spacing layer and on the base layer. The second spacing layer is structured for the purpose of specifying a planar terminal pad on the base layer, and an emitter layer is formed on the planar terminal pad.

Abstract: A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure.

Abstract: An ESD protection structure for use with bipolar or BiCMOS ICs that is relatively immune to thermal overheating and, thus, stable during an ESD event. This immunity is achieved by employing a heat sink region adjacent to a polysilicon emitter within a distance of less than 2 microns. Such a heat sink region provides temporal heat capacity to locally dissipate the heat generated during an ESD event. Bipolar transistor-based ESD protection structures according to the present invention include a semiconductor substrate and a bipolar transistor in and on the semiconductor. The bipolar transistor includes a base region, a collection region and a polysilicon emitter. The bipolar transistor-based ESD protection structures also include a heat sink region disposed above the semiconductor substrate adjacent to the polysilicon emitter.

Abstract: A field effect transistor (FET) is disclosed that includes a heat spreader adapted to reduce the thermal resistance and channel operating temperature of a field effect transistor used in a circuit block susceptible to self-heating effects. In one embodiment, regulatory circuit blocks of an integrated circuit, such as phase locked loops, utilize the FET to improve the characteristics of a regulatory output required by other circuit blocks, such as digital logic circuits. In one embodiment the FET is a silicon-on-insulator structure.

Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

Abstract: Bipolar junction transistors utilize trench-based base electrodes and lateral base electrode extensions to facilitate the use of preferred self-alignment processing techniques. A bipolar junction transistor is provided that includes an intrinsic collector region of first conductivity type in a semiconductor substrate. A trench is also provided in the substrate. This trench extends adjacent the intrinsic collector region. A base electrode of second conductivity type is provided in the trench and a base region of second conductivity type is provided in the intrinsic collector region. This base region is self-aligned to the base electrode and forms a P-N rectifying junction with the intrinsic collector region. An emitter region of first conductivity type is also provided in the base region and forms a P-N rectifying junction therewith.

Abstract: In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat dissipation layers within the dielectric region. Each heat dissipation layer includes electrically inactive thermally conductive structures, at least two such structures in at least one such layer being substantially horizontally connected and thermally coupled to one another within the layer. The electrically inactive thermally conductive structures cooperate to facilitate dissipation of heat from the heat generating structure. In another embodiment, an integrated circuit includes one or more heat generating structures within a dielectric region and electrically inactive thermal posts formed at least partially within the dielectric region. At least one such post is substantially horizontally connected and thermally coupled to another such post.