Abstract: The invention relates to a semiconductor device including a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. In a device according to the invention, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor in a device according to the invention is provided with a pn clamping diode which is formed between the partial region and the collector region.

Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

Abstract: This invention describes fabrication procedures to construct MEMS devices, specifically band-pass filter resonators, in a manner compatible with current integrated circuit processing. The final devices are constructed of single-crystal silicon, eliminating the mechanical problems associated with using polycrystalline silicon or amorphous silicon. The final MEMS device lies below the silicon surface, allowing further processing of the integrated circuit, without any protruding structures. The MEMS device is about the size of a SRAM cell, and may be easily incorporated into existing integrated circuit chips. The natural frequency of the device may be altered with post-processing or electronically controlled using voltages and currents compatible with integrated circuits.

Abstract: A semiconductor device with a reduced insulating capacitance between an emitter electrode and a base layer, and a manufacturing method thereof are disclosed. In the semiconductor device, at least first and second insulating layers are interposed between the emitter electrode and the base layer. Preferably, the first insulating layer, a semiconductor layer having insulation characteristics, and the second insulating layer are interposed between the emitter electrode and the base layer.

Abstract: A power semiconductor device having an breakdown voltage improving structure and a manufacturing method thereof are provided. A collector region and a base region create a pn junction between them. At least one accelerating region of the same conductivity type as the collector region is formed spaced from the pn junction and at a dose higher than that of the collector region. A field plate overlaps the pn junction and the accelerating region. The field plate has an edge portion that extends past the accelerating region. When a voltage of a reverse direction is applied to the pn junction, an electric field becomes concentrated on the accelerating region as well as on the pn junction and on the edge portion of the field plate. This increases an electric field distribution area and thus also increases the breakdown voltage.

Abstract: A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter resistivity found in prior homojunction devices is circumvented using a low work function material layer in forming the emitter. This produces an economically viable high performance alternative to SiGe HBTs or SiGe retrograde base transistors.

Abstract: A semiconductor device comprising a silicon substrate is provided with semiconductor elements on a first side, a metallization with connection pads for external contact, and a passivation layer which leaves the connection pads of the metallization exposed. The integrated circuit thus formed is also provided with a ceramic security coating having a matrix of monoaluminium phosphate which also leaves the connection pads of the metallization exposed. The protective layer can be deposited so as to have a thickness in the range from 2 to 10 &mgr;m, and hence is suitable for protecting integrated circuits used in smart cards. As a result, the information stored therein is not accessible.

Abstract: A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors.

Abstract: An emitter conducting portion, which comprises a p+-type silicon substrate 10, p+-type emitter buried region 14 and a p+-type emitter leading region 20, is formed in a semiconductor element. The p+-type silicon substrate 10 of the semiconductor element is die-bonded to an emitter lead ER for electrically connecting an emitter electrode E to the emitter lead ER by means of the emitter conducting portion. Thus, it is possible to dispense with an emitter bonding wire for connecting the emitter electrode E to the emitter lead ER, and it is possible to remove impedance caused by the emitter bonding wire, so that it is possible to improve the high-frequency characteristics of a semiconductor device.

Abstract: In an element intrinsic region 12 of a bipolar transistor, an emitter is formed by two emitter layers 31,32 so as to reduce the potential barrier presented to minority carriers, this resulting in a smooth flow of minority carriers that are injected into the base layer from the emitter, and in the element external region 13, the emitter layer 32 that acts to reduce the potential barrier to injected minority carriers is removed, thereby suppressing the injection of minority carriers from the emitter layer 31 into the base layer.

Abstract: On an n-type semiconductor substrate 41 doped in high density, a p-type semiconductor layer 2, an n-type semiconductor layer 4 doped in high density, which is a collector, a p-type semiconductor layer 6 doped in high density, which is a base, and the n-type semiconductor layer 7, which is an emitter, are sequentially stacked. To the collector layer, a collector electrode 12 is electrically connected, and to the base layer, a base electrode 11 is electrically connected, and to the emitter layer, an emitter electrode 9 is electrically connected, and thus a bipolar transistor is structured. On the bipolar transistor, an insulated isolation area 55 is formed with an opening therein, whose depth reaches the surface of the substrate, and a substrate electrode 48 is formed thereon. On the bipolar transistor and the insulated isolation area 55, an inter-layer dielectric layer 54 is formed having contact holes formed to upper parts of the emitter electrode 49 and to the substrate electrode 48.

Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying a semiconductor substrate (11). The semiconductor device (10) includes a base region (44) that contacts the corners (13) of the pedestal structure (16). Electrical connection to the base region (44) is provided by a conductive layer (28) that contacts the sides (12) and corners (13) of the pedestal structure (16).

Abstract: A lead electrode is formed to expose an active base region. A lead electrode for an emitter electrode is formed on the lead electrode in an emitter region, through an insulating film. The insulating film on the lead electrode is then etched to form a contact hole. After that, the emitter contact hole is formed to expose the lead electrode. Also, a silicon nitride film SN is interposed between the lead electrode and insulating film and between the lead electrode and LOCOS oxide film each to decrease resistance of the lead electrodes.

Abstract: The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base, to form a base contacting region. A second portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor emitter, to form an emitter contacting region.

Abstract: A vertical conduction NPN bipolar transistor with a tunneling barrier of silicon carbide in the emitter providing a high emitter injection efficiency and high, stable current gain. The emitter structure comprises a heavily doped polysilicon layer atop a silicon carbide layer that contacts a shallow, heavily doped emitter region at the surface of an epitaxial silicon layer, which is disposed on a monocrystallinie silicon substrate. The silicon carbide layer is about 100 to 200 angstroms thick and has a composition selected to provide an energy band gap in the 1.8 to 3.5 eV range. The thickness and composition of the silicon carbide can be varied within the preferred ranges to tune the transistor's electrical characteristics and simplify the fabrication process.

Abstract: The present invention relates to a contact window structure having an insulation layer extending over an electrically conductive region. The insulation layer further has a plurality of contact windows which are filled with electrically conductive layers so that the electrically conductive layers are made into contact with the electrically conductive region so as to allow a contact portion of a probe to contact with at least one of the electrically conductive layers within the contact windows, wherein adjacent two of the contact windows are distanced from each other by a distance which is substantially equal to or narrower than a diameter of the contact portion of the probe, whereby the contact portion of the probe is necessarily made into contact with at least any one of the electrically conductive layers within the contact windows. There is no possibility that the contact portion of the probe is not made into contact with any electrically conductive layers.

Abstract: An integrated device comprises a high-voltage transistor and a low-voltage transistor in an emitter-switching configuration integrated in a chip (400) of semiconductor material comprising a buried P-type region (120) and a corresponding P-type contact region (405) which delimit a portion of semiconductor material within which the low-voltage transistor is formed. The contact region (405) has a network structure such as to divide this portion of semiconductor material into a plurality of cells (410) within each of which there is an elemental P-type base region (425) and an elemental N-type emitter region (430) of the low-voltage transistor. The elemental regions (425) and (430) of the various cells (410) are electrically connected to one another by means of surface metal contacts.

Abstract: A lead electrode (57) is formed to expose an active base region (61). On the lead electrode (57) is formed a lead electrode (64) for an emitter electrode via an insulation film (56). When a base contact hole (65') for exposing the lead electrode (57) and an emitter contact hole for exposing the lead electrode (64) are formed at the same time, total thickness of the insulation film on the lead electrode (64) is thinner than that of the insulation layer on the lead electrode (57), which results in excessive etching on a part of the surface of the lead electrode to form recess. The lead electrode (64) is led out to a LOCOS film to form the emitter contact hole in a region on the LOCOS film to expose the lead electrode (64). Therefore, the recess having been formed on the lead electrode (64) upon forming the emitter contact hole is made to form on the LOCOS film outside the emitter region. The recess prevents depth of the emitter region from dispersing.

Abstract: A semiconductor device provided with a semiconductor substrate with a bipolar transistor having a collector region of a first conductivity type, a base region adjoining the collector region and of a second conductivity type opposed to the first, and an elongate emitter region of the first conductivity type adjoining the base region; the collector region, the base region, and the emitter region being provided with conductor tracks which are connected to conductive connection surfaces. The conductor track on the elongate emitter region of the semiconductor device has a connection to a connection surface for a further electrical connection at each of the two ends of the emitter region. The emitter region may be made longer in this manner because the length of the emitter region is effectively halved by the connections at the two ends. Consequently, charge carriers need be transported over no more than at most half the emitter length.

Abstract: In order to prevent an epitaxial layer from contamination by metal when the epitaxial layer is formed on a substrate on which a conductor film comprising a metallic film is formed, a bipolar transistor (semiconductor device) 1 has the first conductor pattern 8 comprising a high-melting metallic film or a high-melting metallic compound film formed on the substrate 4, and the second conductor pattern 9 comprising a non-metallic film formed so as to cover the first conductor pattern 8. On the substrate 4 is formed the first conductivity type base layer 10 on the semiconductor layer comprising an epitaxial layer so as to come in contact with the second conductor pattern 9. Furthermore, when manufacturing the bipolar transistor 1, the semiconductor layer as the base layer 10 is formed with the epitaxial process after the first conductor pattern 8 is covered by the second conductor pattern 9.

Abstract: To provide a semiconductor device including a self-align type multi-emitter bipolar transistor wherein every collector-base isolation length can be reduced into a minimum value allowed in connection with the collector-base breakdown voltage, in a self-align type bipolar transistor having a multi-emitter structure, more than one emitter/base formation regions (114 and 115) and at least one collector leading region (106) are arranged in a single array, and extrinsic base regions (114) are connected to at least one base electrode (119c) having a contact plug (118c) provided outside the single array by way of a base leading electrode (109). Therefore, collector-base isolation lengths can be set to be a minimum length (e) determined by a collector-base breakdown voltage, enabling to minimize the collector resistance, the collector-base capacitance and the collector-substrate capacitance, as well as to minimize the element size of the bipolar transistor.

Abstract: In a bipolar transistor including a semi-insulating substrate, a collector layer formed on the semi-insulating substrate and a base layer formed on the collector layer, a base contact layer is in contact; with a part of a lower surface of the base layer.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of, in consequence, (a) partially forming a buried layer in a semiconductor substrate and also forming an epitaxial layer on the buried layer, (b) forming a collector region in the epitaxial layer by selectively introducing impurities into the epitaxial layer so that the collector region reaches the buried layer, (c) forming an insulating film on the epitaxial layer, (d) forming a polysilicon film on the insulating film, (e) patterning the polysilicon film to form a base electrode, (f) forming an interlayer insulating film over the base electrode and the insulating film, (g) patterning both the interlayer insulating film and the base electrode to form a base opening at a region at which a base region is to be formed and a collector opening above the collector region, (h) side-etching portions of the insulating film located below the base electrode to form undercut hollow portions in the insulating film, (i) filling the under

Abstract: A bipolar transistor formed on a SOI substrate has a buried collector layer underlying an emitter region and a collector contact region for connection thereof, both of which are made of a doped polysilicon film deposited in a removed portion of an oxide film etched by wet etching and a collector contact groove, respectively. By reducing the area of the buried collector layer, the bipolar transistor has excellent frequency characteristics in a high-frequency range.

Abstract: A semiconductor device, and corresponding method of fabrication, includes a device isolation region formed in a semiconductor layer of a SOI substrate, the semiconductor layer having a first type of conductivity, a first impurity region made of portions of the semiconductor layer, and second and third impurity regions formed in the semiconductor layer outside of the first impurity region, the second and third impurity regions having a second type of conductivity. A base electrode is electrically connected to the first impurity region, a bit line electrode is electrically connected to the second impurity region and a capacitor is electrically connected to the third impurity region. The base electrode may be formed by etching a first contact hole through a first interlayer insulating film formed over the semiconductor layer and filling the first contact hole with an electrically conductive material.

Abstract: A field controlled bipolar switch having a bulk single crystal silicon carbide substrate of a first conductivity type having an upper surface and a lower surface. A first epitaxial layer of a second conductivity type silicon carbide is formed upon the upper surface of the substrate. A second epitaxial layer of the second conductivity type silicon carbide is formed on the first epitaxial layer of silicon carbide. A plurality of regions of a third conductivity type silicon carbide are formed in the second epitaxial layer to form a gate grid in the second epitaxial layer. A third epitaxial layer of the second conductivity type silicon carbide is formed on the second epitaxial layer and a fourth epitaxial layer of the second conductivity type silicon carbide is formed upon the third epitaxial layer. The fourth epitaxial layer has a higher carrier concentration than is present in the first, second and third epitaxial layers.

Abstract: A method of forming a dual damascene structure includes forming an oxide layer and a mask layer there on, which both have protuberances over the conductive layers. Then a chemical mechanical polishing is performed to remove the protuberances and to form openings. The protuberances are above the conductive layers.

Abstract: The present invention provides a microwave integrated circuit device in which a sufficiently large gain can be obtained even in a high-frequency region by effectively reducing a ground inductance of a transistor. The device includes both a semiconductor substrate on which a bipolar transistor is formed and a microstrip line formed on the semiconductor substrate. The microstrip line is constituted of a grounded conductive layer, which is electrically connected to both ends of a base electrode, and input and output signal lines connected to emitter and collector electrodes of the transistor, respectively.

Abstract: A high-frequency bipolar transistor structure includes a base region of a first conductivity type formed in a silicon layer of a second conductivity type, the base region comprising an intrinsic base region surrounded by an extrinsic base region, an emitter region of the second conductivity type formed inside the intrinsic base region, the extrinsic base region and the emitter region being contacted by a first polysilicon layer and a second polysilicon layer respectively. The first and the second polysilicon layers are respectively contacted by a base metal electrode and an emitter metal electrode. Between the extrinsic base region and the first polysilicon layer, a silicide layer is provided to reduce the extrinsic base resistance of the bipolar transistor.

Abstract: A bipolar transistor having a pair of transistor cells formed on a single crystal substrate. Each one of the cells including a collector electrode, an elongated emitter electrode and a base electrode disposed over a first surface of the substrate. The base electrode is adapted to control a flow of carriers between the collector and emitter electrodes. An emitter pad is disposed over the first surface of the substrate. A pair of conductive, air-bridge members is provided. First ends of the bridge members are connected to the emitter pad and second ends of the bridge members are connected along a length of the elongated emitter electrode. The substrate has an emitter contact disposed on a second surface of the substrate. The emitter pad and the emitter contact are electrically connected by an electrically conductive via passing through the substrate between the first and second surfaces of the substrate.

Abstract: A semiconductor device with a bipolar transistor that decreases the parasitic capacitance between a base connection layer and a collector region is provided. This device is comprised of a semiconductor substrate having a main surface, a collector region formed in the substrate, a base region formed in the substrate, an emitter region formed in the substrate, a first dielectric layer formed on the main surface of the substrate to be overlapped with the collector region, a conductive layer formed on the first dielectric layer and applied with a specific electric potential, a second dielectric layer formed to cover the conductive layer, a base connection layer formed on the second dielectric layer and electrically connected to the base region, and a base electrode electrically connected to the base connection layer. The emitter region, the base region, and the collector region constitute a bipolar transistor.

Abstract: A high frequency bipolar transistor (30, 60) having reduced capacitance and inductance is formed over a substrate (61). The substrate (61) is heavily doped to form a low resistance current path. A lightly doped epitaxial layer (62) isolates the substrate (61) from layers which form the transistor. The epitaxial layer (62) is the same conductivity type as the substrate (61). A topside substrate contact (73) couples an emitter of the transistor (60) to the substrate (61). The backside of the substrate (61) is metalized and conductively attached to a leaded flag of a leadframe (51) thereby eliminating wirebond inductance in the emitter of the transistor.

Abstract: A base region and an emitter region are formed at a surface of an n-well region (collector region). A contact hole reaching a portion of the surface of the collector region is formed, a contact hole reaching a portion of the surface of the emitter region is formed, and a contact hole reaching a portion of the surface of the base region is formed. A collector electrode, an emitter electrode and a base electrode are formed in the contact holes, respectively. Assuming that L represents a longitudinal length of the contact hole accommodating the emitter electrode and S represents a width thereof perpendicular to the longitudinal direction, a value of L/S is 10 or more. Thereby, a collector resistance of a bipolar transistor can be reduced, and a manufacturing cost can be reduced.

Abstract: A complementary bipolar transistor device, made of two separate conductive films such as two highly doped polysilicon films of opposite conductivity types. The doped polysilicon film is used for a base of NPN transistor and an emitter of a PNP transistor whereas the other doped polysilicon film is used for emitter of the NPN and a base of the PNP. The resulting base and emitter isolating structure is easy to fabricate, and self-aligned to the advantage of size reduction of individual devices.

Abstract: A semiconductor integrated circuit having a lateral bipolar transistor, is fabricated in a manner compatible with sub-micron CMOS processing. A base contact structure is formed over a bipolar active area, in essentially direct contact to a portion of the upper surface of the active region, essentially concurrent to the formation of a gate electrode on a gate dielectric layer in a CMOS active area. Sidewall spacers, adjacent the base contact region, are formed and a base region formed under the base contact structure using an oblique angle implantation. Emitter region and collector contact regions are formed concurrent with CMOS source and drain regions. An optional, oblique angle collector implant can be performed where desired.

Abstract: A compound semiconductor device has a stripe-shaped heterojunction bipolar transistor cell region mounted on a semi-insulating semiconductor substrate and comprising an array of unit transistor cells each having a base region, an emitter region, and a collector region. A base wiring electrode and a collector wiring electrode are disposed on the substrate parallel to the cell region. The base wiring electrode and the collector wiring electrode have toothed shapes connected to the base region and the collector region. A heat-radiating electrode is disposed on the substrate parallel to the cell region with the base wiring electrode or the collector wiring electrode. A relatively thick gold-plated layer is connected to the heat-radiating electrode and the emitter regions of the unit cells and has a bridge structure over the base wiring electrode or the collector wiring electrode with an insulating film interposed therebetween.

Abstract: A merged single polysilicon bipolar NPN transistor, rather than using separate isolation islands for emitter-base and collector contacts, utilizes a single isolation island. This significantly reduces device area because elimination of the second isolation island used in conventional designs reduces the N+ sink to NPN spacing. Buried layer and isolation layer processing proceed in the conventional manner. At sink mask, however, the mask is sized to uncover one end of the main device active region and a sink implant is performed. At base mask, the sink implant remains covered, rather than being exposed as in the conventional flow. At silicide exclusion, the oxide spacer layer is patterned to exclude silicide from the area above the sink implant region.

Abstract: A method for fabricating a bipolar device, including the steps of forming an epitaxial growth retarding layer on a substrate at a predetermined angle, forming a collector layer on the substrate so that the collector layer is adjacent the epitaxial growth retarding layer and has an inclined portion formed over an edge portion of the epitaxial growth retarding layer, forming a base layer having an inclined portion on the collector layer, and forming an emitter layer on the inclined portion of the base layer.

Abstract: A circuit element is produced in a circuit, and a thermoelectric cooling element comprising two dissimilar metals is thermally coupled to the circuit element for cooling the circuit element. A source is provided for applying a driving current to the circuit element. The circuit is arranged such that the driving current passes to the thermoelectric cooling element as an operating current thereof.

Abstract: A heterojunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

Abstract: To obtain both the highest possible maximum operating frequency f.sub.max and early voltage V.sub.A, a semiconductor device provided with a bipolar transistor including a collector region, a base region formed on the collector region, an emitter region formed in contact with the base region, a base leading electrode connected to the base region, and an emitter electrode connected to the emitter region, is characterized in that a ratio Q.sub.B /N.sub.c of base Gunmel number Q.sub.B to impurity concentration N.sub.C of the collector region of the bipolar transistor lies within a range from 0.2.times.10.sup.-3 cm to 2.5.times..sup.-3 cm.

Abstract: A contact structure of a semiconductor device includes an impurity-doped region formed in the semiconductor substrate, a trench having a groove in the semiconductor substrate, with the groove being in contact with at least one side face of the impurity-doped region, a conductive layer buried in the trench, and a contact region formed on at least one side face of the impurity-doped region, for connecting the impurity-doped region and the conductive layer. Thus, the area occupied by a unit cell is reduced and integration density can be increased accordingly.

Abstract: A semiconductor device. A semiconductor substrate has a first conductivity. A first insulating layer is on the semiconductor substrate and has an opening so that a portion of the semiconductor substrate is exposed. A semiconductor layer has a second conductivity on the portion. A region in said semiconductor layer prevents a leakage current caused by a minute defect and faceting.

Abstract: A bipolar junction transistor includes a semiconductor substrate having a surface, a base region of first conductivity type in the substrate, and an emitter region of second conductivity type extending from the surface into the base region to form a generally concave semiconductor junction having an apex oriented towards the surface. The emitter region preferably includes a plurality of contiguous emitter subregions extending from the surface into the base region in an arcuate manner and merging to form the generally concave semiconductor junction. The transistor preferably includes an emitter terminal electrically contacting the emitter region at an emitter contact area on the surface, the emitter contact area having a central portion substantially centered with respect to the apex of the semiconductor junction.

Abstract: A semiconductor device includes a semiconductor substrate having opposite front and rear surfaces; a semiconductor element disposed on the front surface of the semiconductor substrate and including an electrode; a PHS for dissipating heat generated in the semiconductor element, the PHS including a metal layer and disposed on the rear surface of the semiconductor substrate; a via-hole including a through-hole penetrating through the semiconductor substrate from the front surface to the rear surface and having an inner surface, and a metal disposed in the through-hole and contacting the PHS; and an air-bridge wiring including a metal film and having first and second portions, the air-bridge contacting the electrode of the semiconductor element at the first portion and contacting the metal of the via-hole at the second portion.

Abstract: Methods of forming electrical interconnects on semiconductor substrates include the steps of forming a first electrically insulating layer (e.g., silicon dioxide) and then forming a contact hole in the insulating layer to expose a layer underlying the insulating layer. A first electrically conductive region (e.g., W, Ti, Tin, Al) is then formed in the contact hole. A step is then performed to remove a portion of the first electrically insulating layer to define a recess therein which preferably surrounds an upper portion of the first conductive region. A second electrically conductive region (e.g., Al, Cu, W, Ti, Ta and Co) is then formed in the recess. Here, the first conductive region is preferably chosen to have good step coverage capability to fully bury the contact hole and the second conductive region is preferably chosen to have very low resistance even if some degree of step coverage capability is sacrificed. Planarization steps (e.

Abstract: A semiconductor device having the base and collector surrounded by a continuous tungsten filled slot as ground plane. The portion of the tungsten filled slot over the buried layer extends beyond the surface of the buried layer and the portion of the tungsten filled slot not over the buried layer extends beyond the interface between the epitaxial layer and the substrate.

Abstract: A vertical transistor is provided on and extends in a first direction along a surface of a substrate. A bump electrode is formed over the transistor and crosses the transistor in a second direction perpendicular to the first direction. The bump electrode is butterfly-shaped and has a first area overlapping the transistor and a second area that does not overlap with the transistor. The size of the second area in the first direction is greater than the size of the first area in the first direction. The bump electrode shape has no interior angle exceeding 270.degree..

Abstract: An RF power transistor having improved thermal balance characteristics includes a first emitter electrode and a base electrode formed on a silicon die, each having a multiplicity of parallel electrode fingers. A second emitter electrode is formed over the base electrode, and is electrically connected to the first emitter electrode. Ballast resistors are formed in a substantially evenly spaced manner on each side the silicon die, in series with at least some of the electrode fingers of the first emitter electrode and in series of at least some of the electrode fingers of the second emitter electrode.

Abstract: A semiconductor device including a bipolar transistor is provided, which can reduce the base resistance of the transistor. This device includes a semiconductor base region having a first semiconductor active region of a first conductivity type in its inside. A first insulating layer is formed on the main surface of the substructure to cover the first active region. The first insulating layer has a first penetrating window exposing the first active region. A semiconductor contact region of a second conductivity type is formed on the first insulating layer. The contact region has an overhanging part which overhangs the first window. The second window is defined by the inner end of the overhanging part to be entirely overlapped with the first window. The contact region is made of a polycrystalline semiconductor. A second semiconductor active region of the second conductivity type is formed on the first active region in the first window.