With Field Electrode Under Or On A Side Edge Of Amorphous Semiconductor Material (e.g., Vertical Current Path) Patents (Class 257/60)
  • Patent number: 10840271
    Abstract: A display device is described that has reduced resistance in one or more of the gate, common, data electrical lines that control the operation of the pixels of the display device. Reduced resistance is achieved by forming additional metal and/or metal-alloy layers on the gate, common, and/or data lines in such a manner so that the cross-sectional area of those lines is increased. As a consequence, each such line is formed so as to be thicker than could otherwise be achieving without causing defects in the rubbing process of an alignment layer. Additionally, no widening of these lines is needed, thus preserving the aspect ratio of the device. The gate insulating and semiconducting layers that in part make up the thin film transistors that help control the operation of the pixels of the device may also be designed to take into account the increased thickness of the lines.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 17, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Youngmin Jeong, Seunghwan Shin, Daeyoung Seo, Soyoung Lee
  • Patent number: 10770595
    Abstract: A thin film transistor, a method for manufacturing the same and a display device are provided in the present disclosure. The thin film transistor includes an active layer, a first electrode and a second electrode, and a gate electrode. The active layer includes an active layer body and an electrode hole in a center of the active layer body. The gate electrode is insulated and spaced apart from the active layer body and is disposed to surround the electrode hole. The first electrode and the second electrode are insulated from each other, both coupled to the active layer body, and insulated and spaced apart from the gate electrode. At least a portion of an orthographic projection of the first electrode on the active layer is within the electrode hole. An orthographic projection of the second electrode on the active layer surrounds the active layer body.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 8, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xueyan Tian, Zunqing Song, Xiaolong Li
  • Patent number: 10756161
    Abstract: A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Shivasubramanian Balasubramanian, Dilan Seneviratne
  • Patent number: 10720529
    Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ziwei Fang
  • Patent number: 10688868
    Abstract: An on-vehicle display control device includes a video image acquiring unit configured to acquire left and right side rear view video images captured by imaging units configured to capture the left and right side rear view video images of a vehicle, a turning information acquiring unit configured to acquire turning information on the vehicle, and a video image processing unit configured to display, on determining that the vehicle is going to make a turn based on the turning information, the side rear view video image for a turning direction in an area away from a center of the vehicle in a side monitor provided in a turning direction, and the side rear view video image for a direction opposite to the turning direction in an area close to the center of the vehicle in the side monitor provided in the turning direction.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 23, 2020
    Assignee: JVC KENWOOD Corporation
    Inventors: Naoto Hayashi, Ichiro Ishida, Yoshiyuki Shimizu, Tsuneo Satomi
  • Patent number: 10658517
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a source electrode layer and a drain electrode layer are provided over and in contact with an oxide semiconductor film, entry of impurities and formation of oxygen vacancies in an end face portion of the oxide semiconductor film are suppressed. This can prevent fluctuation in the electric characteristics of the transistor which is caused by formation of a parasitic channel in the end face portion of the oxide semiconductor film.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 19, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Masahiro Takahashi
  • Patent number: 10643975
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventor: Junfeng Zhao
  • Patent number: 10559569
    Abstract: A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Il-Sik Jang, Ji-Hwan Park, Mi-Ri Lee, Bong-Seok Jeon, Yong-Soo Joung, Sun-Hwan Hwang
  • Patent number: 10304944
    Abstract: A method of forming a semiconductor structure is provided. The method including forming a first vertical channel on a first layer of source/drain material that is perpendicular relative to the first vertical channel, and forming a first source/drain semiconductor structure by removing one or more portions of the first layer of source/drain material such that i) the first source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel and ii) a width of the source/drain is greater than a width of the first vertical channel, wherein the first source/drain semiconductor structure extends perpendicularly from its vertical side farther than the first vertical channel extends perpendicularly from its vertical side.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Wilfried E. Haensch, Ali Khakifirooz, Davood Shahrjerdi
  • Patent number: 10269979
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a source electrode layer and a drain electrode layer are provided over and in contact with an oxide semiconductor film, entry of impurities and formation of oxygen vacancies in an end face portion of the oxide semiconductor film are suppressed. This can prevent fluctuation in the electric characteristics of the transistor which is caused by formation of a parasitic channel in the end face portion of the oxide semiconductor film.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Masahiro Takahashi
  • Patent number: 10263083
    Abstract: A thin film transistor array substrate comprises: a substrate, a plurality of thin film transistors disposed on the substrate, wherein each of the plurality of thin film transistors comprises: a gate electrode structure, an isolate protective layer disposed on the gate electrode structure, an active layer disposed on the isolate protective layer, a source electrode layer disposed on a side of the active layer and forming an ohmic contact with the active layer, a drain electrode layer disposed on other side of the active layer and forming an ohmic contact with the active layer, a first concentration doping layer disposed on the active layer and between the source electrode layer and the drain electrode layer, a passivation layer covered onto the active layer, the source electrode layer and the drain electrode layer, and a pixel electrode layer covered onto the passivation layer and the drain electrode layer.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 16, 2019
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: En-Tsung Cho
  • Patent number: 10263086
    Abstract: A semiconductor device includes first and second field electrode structures that extend from a first surface into a semiconductor portion. The first field electrode structures include a first field dielectric insulating spicular first field electrodes against the semiconductor portion. The second field electrode structures include a second field dielectric insulating spicular second field electrodes against the semiconductor portion. The second field dielectric is thicker than the first field dielectric. Openings of the first and second field electrode structures in the first surface may be non-circular symmetric, wherein the openings of the second field electrode structures are tilted with respect to the openings of the first field electrode structures. Alternatively or in addition, the openings of the second field electrode structures in the first surface may be greater than the openings of the first field electrode structures.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 16, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Martin Vielemeyer
  • Patent number: 10224435
    Abstract: An exemplary embodiment of the present disclosure provides a transistor including: a drain electrode; a first insulating member on the drain electrode and having a tilted side wall; a source electrode on the first insulating member; an active member covering the tilted side wall of the first insulating member, a side wall of the source electrode, and a side wall of the drain electrode; a second insulating member covering the source electrode and the active member; and a gate electrode on the second insulating member and overlapping the active member, wherein the active member defines a first channel region adjacent to the drain electrode and a second channel region adjacent to the source electrode, and wherein a width of the first channel region may be greater than that of the second channel region.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: March 5, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jee Hoon Kim, Shin Hyuk Yang, Kwang Soo Lee
  • Patent number: 10158019
    Abstract: A device includes a first channel region and a first gate structure formed over the first channel region. A first source/drain region is adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers. A gradient of decreasing concentration of the first dopant is one decade for every 5.5 to 7.5 nanometers deeper than the first concentration.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ziwei Fang
  • Patent number: 10155369
    Abstract: The present disclosure relates to a method for debonding a pair of bonded substrates. In the method, a debonding apparatus is provided comprising a wafer chuck, a flex wafer assembly, and a set of separating blades. The pair of bonded substrates is placed upon the wafer chuck so that a first substrate of the bonded substrate pair is in contact with a chuck top surface. The flex wafer assembly is placed above the bonded substrate pair so that its first surface is in contact with an upper surface of a second substrate of the bonded substrate pair. A pair of separating blades having different thicknesses is inserted between the first and second substrates from edges of the pair of bonded substrates diametrically opposite to each other while the second substrate is concurrently pulled upward until the flex wafer assembly flexes the second substrate from the first substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Chen Tsao, Kuo Liang Lu, Ru-Liang Lee, Sheng-Hsiang Chuang, Yu-Hung Cheng, Yeur-Luen Tu, Cheng-Kang Hu
  • Patent number: 10153377
    Abstract: The present disclosure proposes a dual-gate thin film transistor and manufacturing method thereof and an array substrate. A manufacturing method includes: forming a first gate electrode, a gate insulating layer, a semiconductor layer, and an etch stop layer on a first substrate sequentially; forming a drain electrode, an independent electrode, and a source electrode on the exposed semiconductor layer; forming an insulating passivation layer on surfaces of the exposed etch stop layer, the drain electrode, the source electrode, and the independent electrode; and forming a second gate electrode on the insulating passivation layer in an area corresponding to the first gate electrode. The present disclosure can resolve the leakage current problem caused by the effective channel length between the source electrode and the drain electrode to improve the electrical properties of the dual-gate thin film transistor and improve its stability. The present disclosure can simplifies processes and reduce cost.
    Type: Grant
    Filed: December 25, 2015
    Date of Patent: December 11, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Hejing Zhang
  • Patent number: 10008585
    Abstract: A semiconductor structure that has adjacent transistors that share a common source/drain semiconductor structure. At least one of the adjacent transistors comprising: a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Wilfried E. Haensch, Ali Khakifirooz, Davood Shahrjerdi
  • Patent number: 9997605
    Abstract: The present invention discloses an LDMOS device, whose drift region is composed of a first drift region and a second drift region, the first drift region being composed of an ion implantation region formed in a selected region of the silicon substrate; the second drift region, composed of the doped polysilicon formed on the surface of the silicon substrate, is superimposed on the first drift region, with the drain region formed in the second drift region. With the second drift region of the present invention, the thickness of the entire drift region can be increased, and thus the parasitic resistance of the entire drift region can be reduced, the linear current of the device can be effectively increased, and the on-resistance of the device can be effectively reduced; the device of the present invention can also maintain a high breakdown voltage and lower process cost. The present invention further discloses a method for manufacturing the LDMOS device.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: June 12, 2018
    Assignee: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
    Inventor: Wensheng Qian
  • Patent number: 9871118
    Abstract: A semiconductor structure having an electrical contact that is connected to source/drain structures of two different transistors. The semiconductor structure has a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Wilfried E. Haensch, Ali Khakifirooz, Davood Shahrjerdi
  • Patent number: 9842901
    Abstract: A semiconductor device includes first and second field electrode structures that extend from a first surface into a semiconductor portion. The first field electrode structures include a first field dielectric insulating spicular first field electrodes against the semiconductor portion. The second field electrode structures include a second field dielectric insulating spicular second field electrodes against the semiconductor portion. The second field dielectric is thicker than the first field dielectric. Openings of the first and second field electrode structures in the first surface may be non-circular symmetric, wherein the openings of the second field electrode structures are tilted with respect to the openings of the first field electrode structures. Alternatively or in addition, the openings of the second field electrode structures in the first surface may be greater than the openings of the first field electrode structures.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 12, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Martin Vielemeyer
  • Patent number: 9837480
    Abstract: An array substrate, a method for fabricating the array substrate and a display device are described. The array substrate includes: a first gate electrode metal layer; a first gate insulation layer; an active layer on the first gate insulation layer; an etching barrier layer on the active layer; a source-drain metal layer including a source electrode and a drain electrode that contact with two sides of the active layer respectively; a second gate insulation layer on the source-drain metal layer; and a second gate electrode metal layer on the second gate insulation layer. The array substrate has an optimized TFT performance and a reduced gate line resistance, and light may be blocked from irradiating on the active layer, which is beneficial to restrain IR Drop, drifting of TFT threshold voltages or generation of a light-incurred leakage current on the active layer. Performance of the display device is improved.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: December 5, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Cuili Gai, Danna Song, Baoxia Zhang
  • Patent number: 9627547
    Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: April 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku
  • Patent number: 9559167
    Abstract: One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: January 31, 2017
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler
  • Patent number: 9536894
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hikari Tajima, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Hiroki Tokuhira
  • Patent number: 9455324
    Abstract: The present invention provides a thin film transistor and a method of fabricating the thin film transistor, an array substrate and a method of fabricating the array substrate, and a display device. The thin film transistor includes a substrate and a gate, an insulation layer, an active layer, a source and a drain which are provided on the substrate. A spacer layer is also provided between the gate and the active layer, and the spacer layer overlaps at least with one of the gate and the active layer having a smaller area in an orthographic projection direction. The spacer layer can effectively prevent material forming the gate from being diffused into the active layer, thereby ensuring stability of performance of the thin film transistor. In the array substrate utilizing the thin film transistor, the spacer layer further extends to a region corresponding to a gate line.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 27, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhanfeng Cao, Qi Yao, Luke Ding, Bing Sun, Xiangchun Kong
  • Patent number: 9401431
    Abstract: A method of fabricating metal oxide TFTs on transparent substrates includes the steps of positioning an opaque gate metal area on the front surface of the substrate, depositing transparent gate dielectric and transparent metal oxide semiconductor layers overlying the gate metal and a surrounding area, depositing transparent passivation material on the semiconductor material, depositing photoresist on the passivation material, exposing and developing the photoresist to remove exposed portions, etching the passivation material to leave a passivation area defining a channel area, depositing transparent conductive material over the passivation area, depositing photoresist over the conductive material, exposing and developing the photoresist to remove unexposed portions, and etching the conductive material to leave source and drain areas on opposed sides of the channel area.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: July 26, 2016
    Assignee: CBRITE INC.
    Inventors: Chan-Long Shieh, Gang Yu
  • Patent number: 9293649
    Abstract: A display device in which various embodiments can prevent a vertically-striped blur is disclosed. In one aspect, the display device includes first gate lines, second gate lines, data lines, dummy data lines, and a plurality of pixels. The first and second gate lines are extended in a first direction. The data lines and the dummy data lines are extended in a second direction intersecting the first direction. The pixels are defined by the intersection of a first gate line of the first gate lines and a first data line of the data lines.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: March 22, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Ji Ryun Park
  • Patent number: 9269826
    Abstract: The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 1018/cm3, and a thin film transistor using such an amorphous oxide. In a thin film transistor having a source electrode 6, a drain electrode 5, a gate electrode 4, a gate insulating film 3, and a channel layer 2, an amorphous oxide having an electron carrier concentration less than 1018/cm3 is used in the channel layer 2.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: February 23, 2016
    Assignees: JAPAN SCIENCE AND TECHNOLOGY AGENCY, CANON KABUSHIKI KAISHA, TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Hideo Hosono, Masahiro Hirano, Hiromichi Ota, Toshio Kamiya, Kenji Nomura
  • Patent number: 9236484
    Abstract: A thin film transistor, a pixel, and an organic light emitting diode (OLED) display including the same are disclosed. The thin film transistor includes a connection to the channel region separate from connections to the source and drain.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: January 12, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chang-Yeop Kim, Won-Kyu Kwak, Jin-Tae Jeong
  • Patent number: 9214481
    Abstract: An embodiment of the disclosed technology provides a driving device for a thin film transistor liquid crystal display (TFT-LCD) and a method for manufacturing the same. The driving device comprises at least one first TFT and at least one second TFT formed a base substrate, wherein load of the first TFT is larger than load of the second TFT, the first TFT is of a top-gate configuration, and the second TFT is of a bottom-gate configuration.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: December 15, 2015
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kun Cao, Ming Hu
  • Patent number: 9130048
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a source electrode layer and a drain electrode layer are provided over and in contact with an oxide semiconductor film, entry of impurities and formation of oxygen vacancies in an end face portion of the oxide semiconductor film are suppressed. This can prevent fluctuation in the electric characteristics of the transistor which is caused by formation of a parasitic channel in the end face portion of the oxide semiconductor film.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: September 8, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Masahiro Takahashi
  • Patent number: 9117922
    Abstract: A thin film transistor includes a gate electrode, a channel layer, a source electrode, and a drain electrode. The channel layer is made of an amorphous oxide semiconductor. The channel layer includes one high oxygen ion concentration region, or two high oxygen ion concentration regions one above the other. An oxygen ion density of each high oxygen ion concentration region is in a range of from about 1×1018 to about 1×1021 per cubic centimeter. A thin film transistor substrate and a method of manufacturing the thin film transistor substrate are also provided.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: August 25, 2015
    Assignee: Ye Xin Technology Consulting Co., Ltd.
    Inventor: Anjo Kenji
  • Patent number: 9048312
    Abstract: A semiconductor device including a substrate having an active region is disclosed. A field-plate region and a bulk region are in the active region, wherein the bulk region is at a first side of the field-plate region. At least one trench-gate structure is disposed in the substrate corresponding to the bulk region. At least one source-doped region is in the substrate corresponding to the bulk region, wherein the source-doped region surrounds the trench-gate structure. A drain-doped region is in the substrate at a second side opposite to the first side of the field-plate region, wherein an extending direction of length of the trench-gate structure is perpendicular to that of the drain-doped region as viewed from a top view perspective.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: June 2, 2015
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsiung-Shih Chang, Jui-Chun Chang
  • Patent number: 9035287
    Abstract: Disclosed are polysulfone-based materials that can be used as active and/or passive components in various electronic, optical, and optoelectronic devices, particularly, metal-oxide-semiconductor field-effect transistors. For example, various metal-oxide-semiconductor field-effect transistors can include a dielectric layer and/or a passivation layer prepared from such polysulfone-based materials and exhibit good device performance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Polyera Corporation
    Inventors: Antonio Facchetti, Daniel Batzel, Jing Chen, Chun Huang, Shaofeng Lu, William Christopher Sheets, Jingqi Wang, Yu Xia
  • Patent number: 9012918
    Abstract: The threshold voltage is shifted in a negative or positive direction in some cases by an unspecified factor in a manufacturing process of the thin film transistor. If the amount of shift from 0 V is large, driving voltage is increased, which results in an increase in power consumption of a semiconductor device. Thus, a resin layer having good flatness is formed as a first protective insulating film covering the oxide semiconductor layer, and then a second protective insulating film is formed by a sputtering method or a plasma CVD method under a low power condition over the resin layer. Further, in order to adjust the threshold voltage to a desired value, gate electrodes are provided over and below an oxide semiconductor layer.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Abe, Hideaki Shishido
  • Patent number: 9006019
    Abstract: A method for manufacturing a light-emitting device includes a step of forming an etching resistant protection layer on a substrate provided with an organic planarizing layer, a step of forming a plurality of electrodes on the etching resistant protection layer, a step of forming an organic compound layer on the substrate provided with the plurality of electrodes, a step of forming a resist layer on the organic compound layer formed on parts of electrodes among the plurality of electrodes using a photolithographic method, and a step of removing the organic compound layer in a region not covered with the resist layer by dry etching, wherein an entire surface of the organic planarizing layer on the substrate on which steps up to the step of forming the plurality of electrodes have been performed is covered with at least one of the etching resistant protection layer and the electrode.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Manabu Otsuka, Tomoyuki Hiroki
  • Patent number: 8981348
    Abstract: A semiconductor element (semiconductor device) including a substrate having a patterned structure of an organic semiconductor material and a method of manufacturing the semiconductor element are disclosed. According to one embodiment, the method of manufacturing the semiconductor element provides a substrate having a patterned structure of an organic semiconductor material which is cost-effective and which realizes a structure having a high degree of uniformity of the patterned semiconductor regions. The method includes: providing the substrate, applying a continuous layer of an organic semiconductor material onto the substrate, applying a solvent onto the continuous layer in the second regions thereby dissolving and removing the organic semiconductor material, which is located in the second regions, from the continuous layer.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: March 17, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joerg Fischer, Arthur Mathea, Marcus Schaedig
  • Patent number: 8981448
    Abstract: A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam Kyun Park
  • Patent number: 8969873
    Abstract: A pixel structure is formed in a pixel area and coupled to a scan line and a data line. The pixel structure includes a first transistor, a second transistor and a pixel electrode. The first transistor is formed in the pixel area and coupled to the scan line and the data line. The second transistor is formed in the pixel area and coupled to the first transistor. The pixel electrode is formed in the pixel area and coupled to the second transistor. The pixel electrode includes a main portion and a first branch portion. The first branch portion is disposed between the first transistor and the second transistor. An electrophoretic display including the pixel structure is also disclosed herein.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 3, 2015
    Assignee: AU Optronics Corporation
    Inventors: Sheng-Wen Huang, Chun-Hung Chu, Chih-Jen Hu
  • Patent number: 8963159
    Abstract: This disclosure provides systems, methods and apparatuses for pixel vias. In one aspect, a method of forming an electromechanical device having a plurality of pixels includes depositing an electrically conductive black mask on a substrate at each of four corners of each pixel, depositing a dielectric layer over the black mask, depositing an optical stack including a stationary electrode over the dielectric layer, depositing a mechanical layer over the optical stack, and anchoring the mechanical layer over the optical stack at each corner of each pixel. The method further includes providing a conductive via in a first pixel of the plurality of pixels, the via in the dielectric layer electrically connecting the stationary electrode to the black mask, the via disposed at a corner of the first pixel, offset from where the mechanical layer is anchored over the optical stack in an optically non-active area of the first pixel.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: February 24, 2015
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Hojin Lee, Fan Zhong, Yi Tao
  • Patent number: 8952447
    Abstract: A non-linear element (e.g., a diode) with small reverse saturation current is provided. A non-linear element includes a first electrode provided over a substrate, an oxide semiconductor film provided on and in contact with the first electrode, a second electrode provided on and in contact with the oxide semiconductor film, a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode, and a third electrode provided in contact with the gate insulating film and adjacent to a side surface of the oxide semiconductor film with the gate insulating film interposed therebetween or a third electrode provided in contact with the gate insulating film and surrounding the second electrode. The third electrode is connected to the first electrode or the second electrode.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8946720
    Abstract: An organic light emitting diode display device and a method of manufacturing the same are disclosed. The organic light emitting diode display device includes a substrate having an emission section and a non-emission section, a semiconductor layer located on the substrate, a gate dielectric layer located over an entire front surface of the substrate, a gate electrode located in correspondence to the semiconductor layer, a dielectric layer located over the entire front surface of the substrate, source and drain electrodes and a first electrode located on the dielectric layer and electrically connected to the semiconductor layer, a pixel definition layer exposing a part of the first electrode, a spacer located on the pixel definition layer and located on the non-emission section of the substrate, an organic film layer located on the first electrode, and a second electrode located over the entire front surface of the substrate.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Do-Hyun Kwon, Choong-Youl Im, Dae-Hyun No, Jong-Mo Yeo, Ju-Won Yoon, Il-Jeong Lee, Song-Yi Jeon, Cheol-Ho Yu
  • Patent number: 8901631
    Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 2, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Sheng-Wei Yang, Ying-Cheng Chuang, Shyam Surthi
  • Patent number: 8896123
    Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehun Jeong, Hansoo Kim, Jaehoon Jang, Hoosung Cho, Kyoung-Hoon Kim
  • Publication number: 20140339562
    Abstract: According to an aspect of the present invention, there is provided a thin-film transistor (TFT) sensor, including a bottom gate electrode on a substrate, an insulation layer on the bottom gate electrode, an active layer in a donut shape on the insulation layer, the active layer including a channel through which a current generated by a charged body flows, an etch stop layer on the active layer, the etch stop layer including a first contact hole and a second contact hole, and a source electrode and a drain electrode burying the first and second contact holes, the source and drain electrodes being disposed on the etch stop layer so as to face each other.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventors: Mu-Gyeom KIM, Chang-Mo PARK
  • Patent number: 8847233
    Abstract: It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Junichi Koezuka, Shunpei Yamazaki
  • Patent number: 8847232
    Abstract: A transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer overhangs the first electrically conductive material layer. An electrically insulating material layer, having a thickness, is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. The thickness of the first electrically conductive material layer is greater than the thickness of the electrically insulating material layer.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: September 30, 2014
    Assignee: Eastman Kodak Company
    Inventors: Lee W. Tutt, Shelby F. Nelson
  • Patent number: 8847230
    Abstract: A thin film transistor is provided that includes a gate electrode, a source electrode, and a drain electrode, an oxide semiconductor active layer formed over the gate electrode, a fixed charge storage layer formed over a portion of the oxide semiconductor active layer, and a fixed charge control electrode formed over the fixed charged storage layer.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 30, 2014
    Assignee: Sony Corporation
    Inventors: Yasuhiro Terai, Eri Fukumoto, Toshiaki Arai
  • Patent number: 8841677
    Abstract: A thin film transistor array panel includes: a gate line and a storage electrode on a substrate and separated from each other; a gate insulating layer covering the gate line and the storage electrode; a data line crossing the gate line and being on the gate insulating layer; a thin film transistor formed at a crossing region of the gate line and the data line, and including a gate electrode, a source electrode, and a drain electrode; a passivation layer exposing a portion of the drain electrode and formed on the thin film transistor and the data line; and a pixel electrode contacting the drain electrode and overlapping the storage electrode with the gate insulating layer interposed therebetween.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: September 23, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sun-Kyo Jung
  • Patent number: 8823005
    Abstract: A thin-film transistor (TFT) and a method of manufacturing the same are disclosed herein. The TFT may include a gate electrode disposed on an insulating substrate, an insulating layer disposed on the insulating substrate and the gate electrode, an active layer pattern disposed on the insulating layer to overlap the gate electrode, a source electrode disposed on the insulating layer and at least part of which overlaps the active layer pattern, and a drain electrode which is separated from the source electrode and at least part of which overlaps the active layer pattern. A first ohmic contact layer pattern may be disposed between the active layer pattern and the source electrode and between the active layer pattern and the drain electrode. The first ohmic contact layer may have higher nitrogen content on its surface than in other portions of the first ohmic contact layer.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: O-Sung Seo, Seong-Hun Kim, Yang-Ho Bae, Jean-Ho Song