With Field Electrode Under Or On A Side Edge Of Amorphous Semiconductor Material (e.g., Vertical Current Path) Patents (Class 257/60)
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Patent number: 7176790Abstract: A vehicle has a display device which widens the field of view (visible area) reflected by a side mirror or a back mirror mounted on the vehicle. To enable a driver driving the vehicle to confirm safety even when it is difficult for the driver to visually recognize some of objects surrounding the vehicle, a liquid crystal display device or an EL display device is provided in the side mirror (door mirror), the back mirror (room mirror) or in an interior portion of the vehicle. A camera is mounted on the vehicle and an image from the camera is displayed on the display device. Further, information read from a sensor (distance measuring sensor) having the function of measuring the distance to another vehicle, and a sensor (impact sensor) having the function of sensing an externally applied impact force larger than a predetermined value is displayed on the display device.Type: GrantFiled: November 1, 2001Date of Patent: February 13, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 7154117Abstract: A display device in which variations of characteristics of a TFT are eliminated and the aperture ratio is improved is provided. A display device has a thin film transistor on an insulating substrate 10. The thin film transistor includes first gate electrodes 11, a gate insulating film 12, a semiconductor film 13 which is formed on the first gate electrode 11, and a interlayer insulating film 15. The thin film transistor further includes second gate electrodes 70 which are on the interlayer insulating film 15 and at least above channels 13c, and which are connected to the first gate electrodes 11. A reflective display electrode 19 connected to the source of the thin film transistor is elongated to extend above the thin film transistor.Type: GrantFiled: January 15, 2004Date of Patent: December 26, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Yasuo Segawa, Keiichi Sano, Kazuto Noritake
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Patent number: 7148510Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.Type: GrantFiled: June 14, 2005Date of Patent: December 12, 2006Assignee: Semiconductor Energy Laboratory Co. Ltd.Inventors: Shunpei Yamazaki, Satoshi Murakami, Masahiko Hayakawa, Kiyoshi Kato, Mitsuaki Osame, Takashi Hirosue, Saishi Fujikawa
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Patent number: 7145175Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.Type: GrantFiled: September 7, 2004Date of Patent: December 5, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Tomoaki Atsumi, Atsuo Isobe
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Patent number: 7115903Abstract: An insulating film having depressions and projections are formed on a substrate. A semiconductor film is formed on the insulating film. Thus, for crystallization by using laser light, a part where stress concentrates is selectively formed in the semiconductor film. More specifically, stripe or rectangular depressions and projections are provided in the semiconductor film. Then, continuous-wave laser light is irradiated along the stripe depressions and projections formed in the semiconductor film or in a direction of a major axis or minor axis of the rectangle.Type: GrantFiled: December 27, 2002Date of Patent: October 3, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Shunpei Yamazaki, Mai Akiba
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Patent number: 7067845Abstract: In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit. the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT.Type: GrantFiled: December 4, 2001Date of Patent: June 27, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Yosuke Tsukamoto, Tomoaki Atsumi, Masayuki Sakakura
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Patent number: 7034336Abstract: The channel region (11) and the source-drain regions (9, 10) are arranged vertically at a sidewall of a dielectric trench filling (4). On the opposite side, the semiconductor material is bounded by the gate dielectric (18) and the gate electrode (16), which is arranged in a cutout of the semiconductor material. A memory cell array comprises a multiplicity of vertically oriented strip-type semiconductor regions in which source-drain regions are implanted at the top and bottom and a channel region embedded in insulating material on all sides is present in between as a floating body.Type: GrantFiled: August 5, 2004Date of Patent: April 25, 2006Assignees: Infineon Technologies AG, Infineon Technologies Flash GmbH & Co. KGInventor: Josef Willer
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Patent number: 7002176Abstract: A vertical organic transistor comprises a substrate, a first electrode positioned over the substrate, a first semiconductor layer formed over the first electrode, a second electrode formed on the first semiconductor layer and shaped into a prescribed pattern, a second semiconductor layer formed over the second electrode and the first semiconductor layer, and a third electrode formed over the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are made of different semiconductor materials.Type: GrantFiled: May 16, 2003Date of Patent: February 21, 2006Assignees: Ricoh Company, Ltd., Kazuhiro KudohInventors: Hiroyuki Iechi, Kazuhiro Kudoh
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Patent number: 6995472Abstract: An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as to provide a cavity between the first and second sidewall insulating films having the same height as the first sidewall insulating film, and an upper insulating film provided over the first and second sidewall insulating films.Type: GrantFiled: October 27, 2003Date of Patent: February 7, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Tsuyoshi Matsumura, Takahito Nakajima, Hiroshi Kawamoto, Mikie Miyasato, Yoshihiro Uozumi
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Patent number: 6930326Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.Type: GrantFiled: March 25, 2003Date of Patent: August 16, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Tomoaki Atsumi, Atsuo Isobe
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Patent number: 6906390Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.Type: GrantFiled: October 25, 2001Date of Patent: June 14, 2005Assignee: Sony CorporationInventors: Kazumasa Nomoto, Hiroshi Aozasa, Ichiro Fujiwara, Shinji Tanaka
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Patent number: 6900464Abstract: The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a first insulating film for covering a first island-like semiconductor film, forming a resist mask that has an opening portion in an inner region with respect to a periphery of the first island-like semiconductor film by exposing/developing the negative photoresist film from a back surface side of a transparent substrate, etching the first insulating film in the opening portion of the resist mask, forming a second insulating film for covering the first insulating film and a conductive film thereon, and forming a first gate electrode and a second gate electrode by patterning the conductive film.Type: GrantFiled: December 9, 2002Date of Patent: May 31, 2005Assignee: Fujitsu Display Technologies CorporationInventors: Seiji Doi, Kazushige Hotta, Takuya Hirano, Kenichi Yanai
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Patent number: 6885028Abstract: A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines includes a core, at least the surface of which is electrically conductive, an insulating layer that covers the core, and a semiconductor layer that covers the insulating layer. Each of the function lines contacts with, and crosses, the conductor lines. Each of the transistors includes a first ohmic contact region, which is defined by a region where one of the conductor lines crosses one of the function lines and which makes an ohmic contact with the semiconductor layer, a second ohmic contact region, which also makes an ohmic contact with the semiconductor layer, and a channel region, which is defined in the semiconductor layer between the first and second ohmic contact regions.Type: GrantFiled: March 18, 2003Date of Patent: April 26, 2005Assignee: Sharp Kabushiki KaishaInventors: Hirohiko Nishiki, Kazuki Kobayashi
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Patent number: 6849873Abstract: In liquid crystal display device having a multi-layer conductive layer, such conductive layer is formed using a photoresist pattern having different thicknesses depending on the position. Upper layer of the gate pad is removed using an etch mask of the photoresist pattern of different thickness. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire. Finally passivation layer is formed and an indium tin oxide layer is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad.Type: GrantFiled: November 25, 2002Date of Patent: February 1, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-Ki Baek, Mun-Pyo Hong, Jang-Soo Kim, Sung-Wook Huh, Jong-Soo Yoon, Dong-Gyu Kim
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Patent number: 6844599Abstract: A semiconductor device has thin film resistors connected in series to form a bleeder resistance circuit. Each of the thin film resistors is made of a polysilicon film doped with B or BF2 P-type impurities and has two end portions each having a high impurity concentration region. A first insulating film overlies the thin film resistors. First conductors are connected to the ends of the thin film resistors for connecting the thin film resistors in series. The semiconductor device has second conductors each connected to a respective one of the first conductors and overlying a respective one of the thin film resistors through the first insulating film.Type: GrantFiled: July 27, 2001Date of Patent: January 18, 2005Assignee: Seiko Instruments Inc.Inventors: Mika Shiiki, Hiroaki Takasu
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Patent number: 6777754Abstract: A semiconductor device a bleeder resistance circuit having conductors, an insulating film disposed on the conductors, and thin film resistors each overlying a respective one of the conductors with the insulating film disposed therebetween. Each of the thin film resistors contains p-type impurities and has a thickness in the range of 10 to 2000 angstroms. Each of the conductors is electrically connected to and has the same electric potential as a respective one of the thin film resistors.Type: GrantFiled: January 9, 2003Date of Patent: August 17, 2004Assignee: Seiko Instruments Inc.Inventor: Mika Shiiki
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Patent number: 6774399Abstract: An active-matrix substrate is provided, which suppresses the unevenness of its surface due to the height difference of the TFTs and gate and data lines from the remaining area. After TFTs, gate lines, and data lines are formed on a transparent base, a transparent dielectric layer is formed on the base to cover the TFTs, the gate lines, and the data lines. The dielectric layer is selectively etched to form transparent dielectric portions arranged in a matrix array in such a way as to form a first plurality of recesses extending along the respective gate lines and a second plurality of recesses extending along the respective data lines. Each of the portions has a thickness equal to or greater than the maximum height of the TFTs, the gate lines, or the data lines, and a distance equal to or greater than the thickness thereof from a corresponding one of the TFTs, the gate lines, or the data lines.Type: GrantFiled: March 12, 2002Date of Patent: August 10, 2004Assignee: NEC CorporationInventor: Kazumi Hirata
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Patent number: 6724010Abstract: A solid state imager is provided that comprises an imaging array of gated photodiodes. The imager comprises a plurality of photosensor pixels arranged in a pixel array, and each of the photosensor pixels includes a photodiode having a sidewall, the sidewall having a gate dielectric layer disposed thereon, and a field plate disposed around the photodiode body. The field plate comprises amorphous silicon disposed on the gate dielectric layer and extends substantially completely around the sidewall of said photodiode. The field plate is electrically coupled to the common electrode of the imaging array so that the field plate creates an electric field around the photodiode body in correspondence with the potential of said common electrode. A method of fabricating the gated photodiode array is also provided.Type: GrantFiled: August 3, 2000Date of Patent: April 20, 2004Assignee: General Electric CompanyInventors: Robert Forrest Kwasnick, George Edward Possin, Ching-Yeu Wei
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Patent number: 6686606Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.Type: GrantFiled: March 18, 2003Date of Patent: February 3, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chua-Gi You
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Patent number: 6603168Abstract: An integrated circuit memory device includes a substrate having at least one connection line therein and a plurality of memory cells formed on the substrate. Each memory cell includes a pillar comprising a lower source/drain region for a cell access transistor electrically connected to the connection line, an upper source/drain region for the cell access transistor, and at least one channel region extending vertically between the lower and upper source/drain regions. Each memory cell further includes at least one lower dielectric layer vertically adjacent the substrate and laterally adjacent the pillar and at least one upper dielectric layer vertically spaced above the at least one lower dielectric layer and laterally adjacent the pillar. Further, each memory cell includes at least one gate for the at least one channel of the cell access transistor between the lower and upper dielectric layers so that the vertical spacing therebetween defines a gate length for the cell access transistor.Type: GrantFiled: April 20, 2000Date of Patent: August 5, 2003Assignee: Agere Systems Inc.Inventor: Seungmoo Choi
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Patent number: 6570182Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.Type: GrantFiled: July 9, 2002Date of Patent: May 27, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chun-Gi You
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Patent number: 6562645Abstract: Disclosed is a method of fabricating fringe field switching mode liquid crystal display by forming a gate bus line and a common electrode line on a lower substrate in parallel with each other; forming a gate insulating layer on the lower substrate; forming a counter electrode on the gate insulating layer to overlap with a predetermined part of the common electrode line; depositing a metal layer on the resulting lower substrate and then selectively patterning the metal layer, thereby forming a contacting part connecting the counter electrode to the exposed common electrode line; depositing a protective layer on the lower substrate obtained after formation of the source, the drain and the contacting part; selectively etching the protective layer to expose a predetermined part of the drain; and forming a pixel electrode on the protective layer to form a field with the counter electrode, being in contact with the drain.Type: GrantFiled: June 28, 2001Date of Patent: May 13, 2003Assignee: Boe-Hydis Technology Co, Ltd.Inventors: Un Cheol Sung, Chang Yong Jeong
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Patent number: 6559472Abstract: A method of depositing a thin film on a substrate in a semiconductor device using Atomic Layer Deposition (ALD) process parameters exposes the substrate to at least one adherent material in a quantity sufficient for the material to adsorb onto the substrate and thereby form an initiation layer. The initiation layer presents at least one first reactive moiety which is then chemically reacted with at least one first reaction material using atomic layer deposition conditions to form a second reactive moiety. The second reactive moiety is then chemically reacted with at least one second reaction material under process conditions sufficient to form a reaction layer over the initiation layer. The process may be repeated to form successive reaction layers over the initiation layer. The adherent material constituting the initiation layer is preferably one which is not substantially degraded by the atomic layer deposition parameters.Type: GrantFiled: January 14, 2002Date of Patent: May 6, 2003Assignee: Micron Technology, Inc.Inventors: Gurtej Sandhu, Garo J. Derderian
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Patent number: 6531710Abstract: An ULSI MOSFET formed using silicon on insulator (SOI) principles includes masking regions of an amorphous silicon film on a substrate and exposing intended active regions. Laser energy is directed against the intended active regions to anneal these regions without annealing the masked regions, thereby increasing production throughput and decreasing defect density.Type: GrantFiled: May 10, 2001Date of Patent: March 11, 2003Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Patent number: 6504173Abstract: The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.Type: GrantFiled: January 9, 2001Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Li-Kong Wang
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Patent number: 6486494Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with An Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.Type: GrantFiled: January 4, 2002Date of Patent: November 26, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chun-Gi You
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Patent number: 6448577Abstract: A high quality semiconductor device comprising at least a semiconductor film having a microcrystal structure is disclosed, wherein said semiconductor film has a lattice distortion therein and comprises crystal grains at an average diameter of 30 Å to 4 &mgr;m as viewed from the upper surface of said semiconductor film and contains oxygen impurity and concentration of said oxygen impurity is not higher than 7×1019 atoms.cm−3 at an inside position of said semiconductor film. Also is disclosed a method for fabricating semiconductor devices mentioned hereinbefore, which comprises depositing an amorphous semiconductor film containing oxygen impurity at a concentration not higher than 7×1019 atoms.cm−3 by sputtering from a semiconductor target containing oxygen impurity at a concentration not higher than 5×1018 atoms.Type: GrantFiled: March 11, 1998Date of Patent: September 10, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hongyong Zhang
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Patent number: 6445004Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed.Type: GrantFiled: July 14, 2000Date of Patent: September 3, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chun-Gi You
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Patent number: 6429457Abstract: A field-effect transistor is made with electrodes (2, 4, 5) and isolators (3) in vertically provided layers, such that at least the electrodes (4, 5) and the isolators (3) form a step (6) oriented vertically relative to the first electrode (2) or the substrate (1). Implemented as a junction field-effect transistor (JFET) or a metal-oxide semiconducting field-effect transistor (MOSFET) the electrodes (2, 5) forming respectively the drain and source electrode of the field-effect transistor or vice versa and the electrode (4) the gate electrode of the field-effect transistor. Over the layers in the vertical step (6) an amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor material is provided and forms the active semiconductor of the transistor contacting the gate electrode (8) directly or indirectly and forming a vertically oriented transistor channel (9) of the p or n type between the first (2) and the second (5) electrode.Type: GrantFiled: September 15, 1999Date of Patent: August 6, 2002Assignee: Thin Film Electronics ASAInventors: Rolf Magnus Berggren, Bengt Goran Gustafsson, Johan Roger Axel Karlsson
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Patent number: 6429456Abstract: This invention provides an inverted staggered type thin-film transistor element wherein the n-doped amorphous silicon film (14) present in the region where the amorphous silicon film (13) does not overlap with the source-drain electrodes (15) is modified into an insulating film (17) by exposure to a plasma containing ions or radicals of oxygen and/or nitrogen, so that the undesired n-doped amorphous silicon film above a channel region need not be removed and the amorphous silicon film can be made thinner. Moreover, the aperture ratio of a liquid crystal display can be enhanced by utilizing such elements.Type: GrantFiled: April 22, 1998Date of Patent: August 6, 2002Assignee: NEC CorporationInventors: Kazushige Takechi, Naoto Hirano
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Patent number: 6369409Abstract: It is an object to provide a highly precise bleeder resistance circuit having an accurate voltage division ratio and a small temperature coefficient of the resistance value and a highly precise semiconductor device having a small temperature coefficient using such a bleeder resistance circuit, e.g., a semiconductor device such as a voltage detector and a voltage regulator. Such characteristic features that the potential of electric conductors on the thin film resistors and electric conductors under the thin film resistors of a bleeder resistance circuit using thin film resistors is made almost equal to the potential of respective thin film resistors and that, when polysilicon is used in the thin film resistor, the dispersion of the resistance value is controlled and the temperature dependency of the resistance value is made lower by thinning the film thickness of the polysilicon thin film resistor are constituted.Type: GrantFiled: August 15, 1996Date of Patent: April 9, 2002Assignee: Seiko Instruments Inc.Inventors: Hiroaki Takasu, Jun Osanai, Kenji Kitamura
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Publication number: 20020028540Abstract: A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.Type: ApplicationFiled: January 8, 1998Publication date: March 7, 2002Inventors: HIDAKI TAKIZAWA, SHOUGO HAYASHI, TAKESHI KINJO, MAKOTO TACHIBANAKI, KENJI OKAMOTO
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Patent number: 6313507Abstract: The present invention provides an SOI device preventing the floating body effect, and a method for manufacturing the same. Disclosed is a method comprising the steps of: forming an isolation layer on a first silicon substrate; forming a conductive layer on the isolation layer and the first silicon substrate; forming a buried insulating layer on the conductive layer; bonding the second silicon substrate so as to contact with the buried insulating layer; exposing the isolation layer by removing backside of the first silicon substrate by selected thickness thereby defining a semiconductor layer; forming a transistor by forming a gate electrode, a source region and a drain region at selected portions of the semiconductor layer; etching a selected portion of the isolation layer so as to expose the conductive layer; and forming a body electrode to be contacted with the conductive layer within the isolation layer.Type: GrantFiled: December 21, 1999Date of Patent: November 6, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Jong-Wook Lee
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Publication number: 20010035528Abstract: A method of fabricating a thin-film transistor on an insulation substrate. A first conductive layer, a gate dielectric layer, a silicon layer and a doped silicon layer are formed on the insulation substrate. These four layers are patterned to form a gate and a gate line. A second conductive layer is formed over the insulation substrate. The second conductive layer and the doped silicon layer are patterned to form a source/drain region, a source/drain conductive layer and a source/drain line on both sides of the gate line. A protection layer is formed over the insulation layer, followed by a patterning step to form openings on the source/drain conductive layer and the source/drain line. A transparent conductive layer is formed on the protection layer and in the openings. After being patterned, a pixel electrode is formed, and a portion of the transparent conductive layer remains to electrically connect the source/drain line and the source/drain conductive layer.Type: ApplicationFiled: April 27, 2001Publication date: November 1, 2001Inventors: Chien-Sheng Yang, Fang-Chen Luo
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Patent number: 6310363Abstract: In those thin-film transistors (TFTs) employing as its active layer a silicon film crystallized using a metal element, the objective is to eliminate bad affection of such metal element to the TFT characteristics. To this end, in a TFT having as its active layer a crystalline silicon film that was crystallized using nickel (Ni), those regions corresponding to the source/drain thereof are doped with phosphorus; thereafter, thermal processing is performed. During this process, nickel residing in a channel formation region is “gettered” into previously phosphorus-doped regions. With such an arrangement, it becomes possible to reduce the Ni concentration in certain regions in which lightly-doped impurity regions will be formed later, which in turn enables suppression of affection to TFT characteristics.Type: GrantFiled: February 29, 2000Date of Patent: October 30, 2001Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Shunpei Yamazaki
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Publication number: 20010030324Abstract: A photo sensor array comprises a plurality of photoelectric conversion elements separated from each other in a predetermined direction to be arranged, each photo conversion element including a semiconductor layer having an incidence effective region on which excited light is incident, source-drain electrodes provided respectively on both ends of the semiconductor layer, a first gate electrode provided below the semiconductor layer via the first gate insulating film. A second gate electrode provided above the semiconductor layer via the second gate insulating film. A source terminal commonly connects to the source electrodes of the photoelectric conversion elements, and a drain terminal commonly connects the drain electrodes of the photoelectric conversion elements, a first gate terminal commonly connects the first gate electrodes of the photoelectric conversion elements, and a second gate terminal commonly connects the second gate terminal of the photoelectric conversion elements.Type: ApplicationFiled: April 5, 2001Publication date: October 18, 2001Applicant: Casio Computer Co., Ltd.Inventors: Shigeru Morikawa, Makoto Sasaki
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Patent number: 6294814Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.Type: GrantFiled: August 24, 1999Date of Patent: September 25, 2001Assignee: Silicon Genesis CorporationInventors: Francois J. Henley, Nathan W. Cheung
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Patent number: 6288412Abstract: A method of manufacturing a polycrystalline silicon film having a particular field effect mobility is disclosed. A first polycrystalline silicon film is formed on a transparent insulation substrate. The surface of the silicon film is oxidized, and an amorphous silicon film is formed on the first polycrystalline silicon film and oxide layer. The amorphous silicon film is subjected to a solid phase growth process to be converted to a second polycrystalline silicon film. The field effect mobility of the second polycrystalline silicon film can be adjusted to a desired value by controlling the relative thicknesses of the first and second polycrystalline silicon films.Type: GrantFiled: November 19, 1997Date of Patent: September 11, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Hiroki Hamada, Kiichi Hirano, Nobuhiro Gouda, Hisashi Abe, Eiji Taguchi, Nobuhiko Oda, Yoshihiro Morimoto
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Patent number: 6265249Abstract: An additional high quality insulating layer is grown over the substrate after the formation of the gate electrode of a thin film transistor (TFT). The growth temperature of the insulating layer can be higher than conventional method and the insulating layer is more free of pin-holes. After the insulating layer in the thin oxide region of the TFT is etched away, conventional fabrication processes are followed. The dielectric of the thin film oxide region is the same as that of the conventional TFT; but the dielectric in the vicinity of the thin oxide region, the crossovers of the data lines and the scan lines, and the gate dielectric layer of the TFT are now composed of the high quality insulating layer. The TFT structure can improve the yield of fabrication by confining the channel region in the shadow of the gate electrode to reduce the leakage photo-current, and by reducing the steps at crossovers steps and interconnections to avoid open-circuit.Type: GrantFiled: December 1, 1997Date of Patent: July 24, 2001Assignee: Industrial Technology Research InstituteInventor: Biing-Seng Wu
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Patent number: 6225667Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.Type: GrantFiled: January 18, 2000Date of Patent: May 1, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Matthew S. Buynoski, Donald L. Wollesen
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Patent number: 6215154Abstract: A thin film transistor (TFT) which may be used as a pixel drive element in an active matrix LCD display includes a pair of side wall spacers adjacent to the opposing side walls of its gate electrode. The side wall spacers provide the gate electrode with a substantially rectangular cross section, such that the gate electrode has a substantially constant thermal conductivity over its area. The TFT has a uniform device characteristic.Type: GrantFiled: February 13, 1998Date of Patent: April 10, 2001Assignees: Sanyo Electric co., Ltd., Sony CorporationInventors: Satoshi Ishida, Yasuo Nakahara, Hiroyuki Kuriyama, Tsutomu Yamada, Kiyoshi Yoneda, Yasushi Shimogaichi
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Patent number: 6188104Abstract: A trench DMOS device has a gate insulating layer on the bottom and sidewalls of the trench. The upper edges of the trench have an impurity injection region and are rounded. In addition, a first conductive layer is formed on the gate insulating layer, and a second conductive layer is formed on the first conductive layer and filled in the trench. The second conductive layer has different crystallization from the first conductive layer. As such the first conductive layer acts as a buffer between the gate insulating layer and the filled in second conductive layer. A method for fabricating a trench DMOS device includes the steps of forming an epitaxial layer on a semiconductor substrate. Then an impurity is injected into the epitaxial layer to form an impurity injection region. Then a trench is formed in the semiconductor substrate passing through the impurity injection region. Then a dry etching process is used to round the upper edges of the trench.Type: GrantFiled: March 27, 1998Date of Patent: February 13, 2001Assignee: Samsung Electronics Co., LtdInventors: Mun-Heui Choi, Dong-Soo Jeong
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Patent number: 6184541Abstract: On the polycrystal semiconductor film 3 formed on the insulating substrate 1, the source 6 and drain 7 in LDD structure having a low concentration region 4 and a high concentration region 5 are formed. The region 4 has a low impurity concentration, and the region 5 has a high impurity concentration. The length of the low concentration region 4 measured from the edge of gate insulating film 9 is not smaller than the average grain size of the polycrystal semiconductor film 3. The LCD device employing the TFT thus constructed is free from white spots (micro brighter spots) in a high temperature atmosphere.Type: GrantFiled: December 3, 1998Date of Patent: February 6, 2001Assignee: Matsushita Electronics CorporationInventors: Hitoshi Oka, Yutaka Ito
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Patent number: 6166395Abstract: In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550.degree. C. to about 560.degree. C.Type: GrantFiled: March 1, 1999Date of Patent: December 26, 2000Assignee: Micron Technology, Inc.Inventors: Keith Smith, Phillip G. Wald
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Patent number: 6160268Abstract: This invention is related to a method for controlling a threshold voltage of a bottom gate type thin film transistor as follows. Gate electrodes and a gate insulating film are formed on a glass substrate. An amorphous silicon film is formed thereon and then crystallized into a crystalline silicon film. After a buffer layer is formed thereon, an impurity element (selected from Group 13 or Group 15 elements) for a threshold voltage control is added to the crystalline silicon film by ion implantation or ion doping.Type: GrantFiled: June 29, 1999Date of Patent: December 12, 2000Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 6140668Abstract: Amorphous and polycrystalline silicon (hybrid) devices are formed close to one another employing laser crystallization and back side lithography processes. A mask (e.g., TiW) is used to protect the amorphous silicon device during laser crystallization. A patterned nitride layer is used to protect the amorphous silicon device during rehydrogenation of the polycrystalline silicon. An absorption film (e.g., amorphous silicon) is used to compensate for the different transparencies of amorphous and polycrystalline silicon during the back side lithography. Device spacing of between 2 and 50 micrometers may be obtained, while using materials and process steps otherwise compatible with existing hybrid device formation processes.Type: GrantFiled: April 28, 1998Date of Patent: October 31, 2000Assignee: Xerox CorporationInventors: Ping Mei, Rene A. Lujan
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Patent number: 6093937Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.Type: GrantFiled: February 19, 1997Date of Patent: July 25, 2000Assignee: Semiconductor Energy Laboratory Co. Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Akiharu Miyanaga, Takeshi Fukunaga
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Patent number: 6018181Abstract: A thin film transistor has a gate electrode formed of polysilicon on a surface of an insulating substrate or an insulating layer. The surface of the gate electrode is covered with a dielectric layer. A polysilicon layer is formed on a surface of the dielectric layer and source/drain regions are formed in this polysilicon layer. The dielectric layer covers the surface of the gate electrode and has its surface made flat. The source/drain regions are formed in the polysilicon layer on the surface of this flat dielectric layer. In another embodiment, a dielectric layer has a 2-layered structure with sidewall insulating layers located on sidewalls of a gate electrode and another insulating layer covering a surface of the gate electrode and surfaces of the sidewall insulating layers. By having larger film thickness of the dielectric layer in the vicinity of a side portion of the gate electrode than that above the gate electrode, the electric field concentration is modified in the vicinity thereof.Type: GrantFiled: December 16, 1994Date of Patent: January 25, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kazuhito Tsutsumi
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Patent number: 5982003Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier.Type: GrantFiled: June 5, 1995Date of Patent: November 9, 1999Assignee: The Regents of the University of CaliforniaInventors: Chenming Hu, Mansun John Chan, Hsing-Jen Wann, Ping Keung Ko
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Patent number: 5965905Abstract: A TFT with a drain-offset structure is provided, which realizes a high ON current while keeping an OFF current at a low level. This TFT includes a substrate and a patterned semiconductor film formed on a main surface of the substrate. At least the main surface of the substrate has an insulating property. The patterned semiconductor film is made of a silicon-system semiconductor material and is not monocrystalline. The patterned semiconductor film includes a source region of a first conductivity type, a channel region of a second conductivity type opposite to the first conductivity type, a first drain region of the first conductivity type, and a second drain region of the second conductivity type. The first drain region serves as an offset region. A gate electrode is formed to be opposite to the channel region through a gate insulating film. The source region is formed on one end of the semiconductor film. The second drain region is formed on an opposite end of the semiconductor film to the source region.Type: GrantFiled: November 24, 1997Date of Patent: October 12, 1999Assignee: NEC CorporationInventor: Fumihiko Hayashi