Abstract: In a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings adjacent the first plate ring. Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding the surge voltage increases.

Abstract: A power MOSFET includes a semiconductor substrate having a drift region therein and first and second transition regions of first conductivity type that extend between the drift region and a first surface of the semiconductor substrate. Each of the first and second transition regions has a vertically retrograded first conductivity type doping profile therein that peaks at a first depth relative to the first surface. First and second shielding regions of second conductivity type are provided in the drift region and define respective P-N junctions with the first transition region. The shielding regions extending laterally towards each other in a manner that constricts a neck of the first transition region to a minimum width at a second depth relative to the first surface. An anode electrode is provided. The anode electrode that extends on the first surface of the semiconductor substrate and defines a Schottky rectifying junction with the second transition region.

Abstract: A recessed p-type region cap layer avalanche photodiode (12) is provided. The photodiode (12) includes a semiconductor substrate (30) and a semiconductor stack (32), which is electrically coupled to the substrate (30). A cap layer (34) is electrically coupled to the stack (32) and includes a recessed p-type region (36). The recessed p-type region (36) forms a p-n junction (38) with the stack (32). A method of forming the photodiode (12) is also provided. The method includes forming the substrate (30), the stack (32), and the cap layer (34). The cap layer (34) is selectively etched to expose the stack (32) and form a cap layer opening (42). Dopant is diffused through the cap layer opening (42) into the stack (32) to form the p-n junction (38).

Abstract: There is disclosed a p-n junction diode structure whose electrical characteristics can be affected by the application of pressure or other mechanical stresses that will control sensitivity. The p-n junction consists of two different semiconductor materials, one being of p-type and the other of n-type, both having predetermined crystallographic axes which are fusion bonded together to form a p-n junction. Because of the ability to control the position of the crystallographic axes with respect to one another, one can affect the electrical characteristics of the p-n junction and thereby produce devices with improved operating capabilities such as Zener diodes, tunnel diodes as well as other diodes.

Abstract: A semiconductor arrangement and a method for manufacturing the semiconductor arrangement are provided, which arrangement and method allow an improvement in the current-carrying capacity for given chip dimensions. The semiconductor arrangement includes trenches introduced in the interior of the chip, which trenches reduce power loss and improve the heat dissipation of the chip, as well as reduce the forward voltage of diode.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: The invention relates to a high frequency oscillator for an integrated semiconductor circuit and its use.

Abstract: This invention provides a method or an auxiliary method to implement optimum variation lateral flux on a semiconductor surface. The method is to cover one or more thin films of high permittivity dielectric material on the semiconductor surface. The one or more films are capable of transmitting flux into or extracting flux from the semiconductor surface, or even to extract some flux from a part of the semiconductor surface and then transmit the flux to another part of the semiconductor surface. By using optimum variation lateral flux, not only can high-voltage lateral devices be made, but also an edge-termination technique for high-voltage vertical devices is provided. While the thin films can be used to prevent the occurrence of strong electric fields produced at the edges of some doped regions, these regions are used to compensate other doped regions with opposite doping and different location.

Abstract: An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of silicon carbide, while suppressing occurrence of voltage oscillation of the device having a high amplitude. A resistor (12) is connected in parallel to a diode (11) made of silicon carbide. Although a resistive component of the diode (11) varies widely with turn-on and turn-off of the diode (11), connecting the resistor (12) in parallel to the diode (11) allows suppression of variations in a resistive component of an LCR circuit formed by the diode (11) and an external wiring. Accordingly, the LCR circuit is unlikely to satisfy the condition of natural oscillation and an increase in the quality factor of the LCR circuit is suppressed.

Abstract: Indium phosphor (InP) Gunn diode that realizes improvements in thermal characteristics, yield factor of good products and easy assembly to planar circuits is provided. In a Gunn diode of the present invention, contact layers are interposing an active layer. An anode electrode and a cathode electrode are formed on the uppermost contact layer. A high resistance region around the cathode electrode is formed at least in an uppermost contact layer by ion implantation using the cathode and anode electrode as a mask. A region under the cathode electrode functions as a Gunn diode and a region under the anode electrode function as a conductive path from the anode electrode to the active layer. These two regions are defined by the high resistance region.

Abstract: A protective circuit for protecting an IGBT from a stress due to application of an overvoltage which is induced by a surge such as static electricity is provided. The protective circuit allows for improvement in a voltage tolerance to a stress due to application of an overvoltage induced by a surge while ensuring a current tolerance to flow of a direct current from an external power supply when the external power supply is improperly connected in a direction contrary to a normal direction. The protective circuit includes a resistor having one end connected to a terminal for connecting to the external power supply and the other end connected to a semiconductor element, and a first zener diode including a cathode connected to the other end of the resistor. The protective circuit further includes a plurality of second zener diodes connected in series between the one end of the resistor and a generator of a constant potential such as a ground.

Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.

Abstract: A lead frame for a high power semiconductor device die has three external lead conductors, the outer two of which are reentrantly bent outwardly from the center of the lead frame. When the lead frame is overmolded, the outer conductors are spaced from a central conductor by an increased creepage distance along the plastic surface of the housing. Further, the lead sequence of the exterior leads is gate, source, drain for a power MOSFET. The post area for wire bonding to the source post is enlarged to permit wire bonding with at least three bond wires. The external conductors can be downwardly bent to form a surface mount device. The cross-sectional area of the external conductors is substantially enlarged, although only a small enlargement of the circuit board hole is needed. The package outline has a long flat area centered over the main die area, with a tapered end surface which allows the package to pry open a mounting spring for surface mounting of the package.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and thus also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A high-voltage diode has a dopant concentration of an anode region and a cathode region optimized in terms of basic functions static blocking and conductivity. Dopant concentrations range from 1×1017 to 3×1018 dopant atoms per cm3 for the anode emitter, especially on its surface 1019 dopant atoms per cm3or more for the cathode emitter and approximately 1016 dopant atoms per cm3 for the blocking function of an anode-side zone.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: A semiconductor device includes a polysilicon layer in which a first region of a first conductivity type and a second region of a second conductivity type is formed. The first region and the second region form a p-n junction in the polysilicon layer. The semiconductor device further includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. In operation, a low resistance path is formed between the first and second metallization region when a voltage or a current exceeding a predetermined threshold level is applied to the first or the second region. The voltage or current is applied for zap trimming of the p-n junction where the voltage or current exceeding a predetermined threshold level, together with the resulting current or resulting voltage, provides power sufficient to cause the low resistance path to be formed.

Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.

Abstract: A flat panel display lighting system 20 includes: semiconductor light-emitting device 10; board 21; and light guide plate 22. The device 10 includes an inverted T-shaped substrate 1 having a base portion 1a, on which a pair of electrodes 2 and 3 are formed, and a mounting portion 1b, on which a light emitter 4 is mounted. The device 10 is mounted through the board 21 with the mounting portion 1b set through an opening 21a formed in the board 21. A light guide plate 22 is mounted on the board 21 so that a face of the plate 22 faces the light emitter 4. Each of the pair of electrodes 2 and 3 is formed on the substrate 1 of the device 10 so as to be electrically connected to the light emitter 4 and to a circuit pattern formed on the board 21.

Abstract: Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate such as silicon. Furthermore, a cathode side P layer 103 is also formed facing a cathode electrode 105 in a position on the N layer 101 that a depletion layer extended during application of a reverse bias voltage does not reach. By providing the cathode side P layer 103, a current density of a reverse current obtained during a reverse recovery operation can be increased, the sudden change of a resistance component of a diode can be prevented and the generation of a voltage oscillation can be suppressed. The cathode side P layer 103 has a diameter W of approximately 400 &mgr;m or less and a rate of an area of the cathode side P layer 103 occupying a cathode surface is kept at approximately ⅖ or less.

Abstract: In a ESD protection clamp, breakdown and triggering voltage of the structure are reduced by introducing an internal zener diode structure that has a lower avalanche breakdown than the p-n junction of the ESD device. This introduces extra holes into the source junction region causing electrons to be injected into the junction and into the drain junction region to increase the carrier multiplication rate to increase the current density and lower the triggering voltage and breakdown voltage of devices such as NMOS devices or LVTSCRs.

Abstract: This invention relates to a technique of improving reverse recovery characteristic of a semiconductor device, and an object of the invention is to solve a technical problem of breakdown voltage reduction which has conventionally caused in enhancing soft recover.

Abstract: The invention concerns an integrated circuit, including a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a Vcc power supply terminal, an input point (in) and an output point (out). At least one of the Vcc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, and the overvoltage protection circuit includes means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point. The means include two or more diode elements of the Zener type connected in series. The substrate of a first conductivity type is provided with a well (WLL) of a second, opposed conductivity type formed in the substrate.

Abstract: A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semiconductor component further includes at least one more diode (240, 250, 280, 290, 440, 450) over the electrically insulative layer, the semiconductor layer, and the diode in the semiconductor layer.

Abstract: A semiconductor device is provided which minimizes a reduction in the breakdown voltage caused by a metal electrode to which a high voltage is applied. An n− semiconductor layer (3) is formed on a p− semiconductor substrate (1). A p+ impurity region (4) is formed within the n− semiconductor layer (3), extending from the surface of the n− semiconductor layer (3) to the interface of the n− semiconductor layer (3) and the p− semiconductor substrate (1). The p+ impurity region (4) is formed to surround part of the n− semiconductor layer (3) and forms a high-potential island region (101) where a logic circuit (103), an n+ impurity region (5) which is a cathode region of a bootstrap diode (102), and a p+ impurity region (6) which is an anode region are located.

Abstract: A power semiconductor device of the present invention comprises a voltage drive type power MOS transistor, a series connection of a first resistor and Zener diode, a second resistor, and a series connection of a third resistor and MOS transistor. The power MOS transistor has a gate, source and drain. A drain-to-source voltage of the power MOS transistor is applied across the series connection of the first resistor and Zener diode. A gate-to-source voltage of the power MOS transistor is applied across the second resistor. The gate-to-source voltage of the power MOS transistor is applied across a series connection of a third resistor and the MOS transistor. The MOS transistor has a gate, source and drain. The gate of the MOS transistor is connected to a node between the first resistor and the Zener diode.

Abstract: An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.

Abstract: A structure of an ESD protection circuit device located under a pad, protecting an internal circuit and a method of manufacturing the same are disclosed. The ESD protection circuit device having a pad window, located under a pad, includes a semiconductor substrate having a P-well and an N well. The P-well and the N-well have an interface. A predetermined area, pad window is selected in the substrate. A first STI structure, a second STI structure and a third STI structure are formed in the substrate within the pad window. N-type doped regions are formed P-well and in the N-well. First p-type doped regions are formed in the P-well and in the N-well and second p-type doped regions are formed in the P-well and in the N-well. A first zener diode is formed in the N-well and a second zener diode is formed in the P-well.

Abstract: A semiconductor light emitting device has a blue LED and a green LED which each have a protection circuit connected in parallel thereto. The protection circuit has two Zener diodes that are connected in series in opposite directions to each other. When an AC voltage below a breakdown voltage of the protection circuit is applied to the semiconductor light emitting device and when the voltage is in forward direction, a current passes through the blue and green LEDs to emit lights. A current is intercepted by the protection circuit when the voltage is in reverse direction. When an high AC voltage above a breakdown voltage of the protection circuit is applied, a current passes through the protection circuit whether the current in forward direction or in reverse direction, so that the green and blue LEDs are protected. Even when the semiconductor light emitting devices are connected to one another in a matrix form and subject to dynamic driving, a leakage current is intercepted by the protection circuits.

Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.

Abstract: The semiconductor device has an insulated-gate field-effect transistor (MOS transistor), a bipolar transistor, and a Zener diode. The MOS transistor is formed in a well of a first conductive type (p-type) and has a gate insulation layer, a gate electrode, side wall insulation layers, and second conductive type (n-type) of source and drain regions. The bipolar transistor has the drain region as a collector region, the well as a base region, and an n-type impurity-diffusion layer isolated from the drain region as an emitter region. The Zener diode is formed by the junction of an n-type impurity-diffusion layer continuous with the drain region and a p-type impurity-diffusion layer. The source and drain regions have a silicide layer formed on the surface thereof. A protection layer is formed on the surface of the n-type impurity-diffusion layer of the Zener diode.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semiconductor component further includes at least one more diode (240, 250, 280, 290, 440, 450) over the electrically insulative layer, the semiconductor layer, and the diode in the semiconductor layer.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/ electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.

Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.

Abstract: A method is provided for suppressing a transient signal (VTR) using a single semiconductor die (130). The method comprises the step of loading the transient signal with first and second junctions (110, 112) formed adjacent to a first doped region (140) of the semiconductor die. The first junction breaks down to generate a current while the second junction forward biases to route the current across an undepleted portion (161) of the first doped region and through the second junction.

Abstract: A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a constant voltage device, a desired voltage is applied to the electrode. Then, trapping of carriers in the interface between the field oxide and the semiconductor region can be suppressed, although such trapping is ordinarily caused by a reverse breakdown phenomenon at the pn junction between the doped layer and the P-type semiconductor substrate. Accordingly, the variation in strength of the electric field between the doped layer and the semiconductor substrate can be suppressed. As a result, it is possible to suppress a variation in reverse withstand voltage, which is usually caused by a reverse breakdown voltage at a pn junction, for a semiconductor device functioning as a constant voltage device.

Abstract: A wide bandgap semiconductor single crystal is applied as a semiconductor substrate material of a semiconductor surge absorber, and a surge absorption operation starting voltage is set by a punchthrough of a pn junction, to obtain a semiconductor surge absorber with a repetitive operation and a high surge endurance.

Abstract: A semiconductor device is provided with an electrostatic protection circuit that causes rapid breakdown of a Zener diode immediately after a static charge is applied, to discharge the static charge by a high-gain thyristor with good response characteristics, and that has a small surface area. When a static charge is applied, a Zener diode breaks down, which acts as a trigger to turn on a thyristor formed of an NPN bipolar transistor and a PNP bipolar transistor. The PNP bipolar transistor is formed of p-type, n-type, and p-type impurity diffusion regions formed in the thickness direction of the substrate and the Zener diode is formed of n-type and p-type impurity diffusion regions. Ann-type impurity diffusion region is provided adjacent to a surface-layer p-type impurity diffusion region, and these p-type and n-type impurity diffusion regions are connected to a signal terminal through a silicide layer formed on the surfaces thereof.

Abstract: A monolithic assembly of a vertical fast diode with at least one additional vertical component, in which the fast diode is formed by an N-type substrate in one surface of which an N+-type continuous region is formed and in the other surface of which a P+-type discontinuous region is formed. The bottom surface of the assembly is coated with a single metallization. The other vertical component is, for example, a diode.

Abstract: An edge termination for a semiconductor component containing a semiconductor body formed of silicon carbide. The edge termination has at least one diode chain that is insulated from the semiconductor body and provided with a plurality of semiconductor layers having alternating conductivity types.

Abstract: A semiconductor light emitting device has a blue LED and a green LED which each have a protection circuit connected in parallel thereto. The protection circuit has two Zener diodes that are connected in series in opposite directions to each other. When an AC voltage below a breakdown voltage of the protection circuit is applied to the semiconductor light emitting device and when the voltage is in forward direction, a current passes through the blue and green LEDs to emit lights. A current is intercepted by the protection circuit when the voltage is in reverse direction. When an high AC voltage above a breakdown voltage of the protection circuit is applied, a current passes through the protection circuit whether the current in forward direction or in reverse direction, so that the green and blue LEDs are protected. Even when the semiconductor light emitting devices are connected to one another in a matrix form and subject to dynamic driving, a leakage current is intercepted by the protection circuits.

Abstract: A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.

Abstract: An improved semiconductor device which includes a zener diode and RC network combination that share common semiconductor mask steps during the fabrication process. A common N+ layer serves to provide both the separate N+ cathode regions of the zener diode and the separate bottom electrode N+ region of the capacitor. A common metal layer serves to provide separate electrical contacts to the N+ cathode regions of the zener diode and also provides a separate top metal electrode for the capacitor. The capacitor dielectric is comprised of silicon nitride. A silicon dioxide/silicon nitride insulation layer is formed between the top metal electrode of the capacitor and a resistive layer typically made from tantalum nitride.

Abstract: The present invention provides a semiconductor device having multilayer interconnections including a first interconnection and a second interconnection, wherein: the second interconnection is formed to be connected to one of a ground, a positive power source and a negative power source; the second interconnection is formed either not to be electrically connected to the first interconnection or to be connected to the first interconnection in a high impedance state; and the first interconnection and the second interconnection are electrically connected to each other during or after a characteristic inspection during which the second interconnection is provided with a pad for inspecting characteristics of the semiconductor device.

Abstract: A semiconductor device with a tunnel diode (23) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications. In a device according to the invention, the portions (2A, 3A) of the semiconductor regions (2, 3) adjoining the junction (23) comprise a mixed crystal of silicon and germanium. It is surprisingly found that the doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions (2, 3).

Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.

Abstract: The present invention provides a power semiconductor device comprising a semiconductor substrate; a voltage-controlled transistor comprising a first electrode formed on the lower surface of the semiconductor substrate, a gate formed on the semiconductor substrate with a gate oxide interpolated in between and a second electrode formed on the semiconductor substrate; and a zener diode formed on the upper surface of the semiconductor substrate so as to be connected between the gate and the second electrode; wherein p-type regions and n-type regions alternately formed between the zener diode and the second electrode on the semiconductor substrate, a plurality of pad electrodes on the semiconductor substrate provided with the alternate p-type regions and n-type regions so as to allow one or not less than two diodes are series connected between the zener diode and the second electrode, and the distance between the adjacent pad electrodes is set so that when the diode is subjected to a current not less than a predet