Abstract: A semiconductor device of band-to-band tunneling type including a silicon substrate, a first gate electrode formed by a highly doped surface region of the silicon substrate, a first silicon oxide film formed on a surface of the surface region, a silicon thin film formed on the first silicon oxide film, a second silicon oxide film formed on a surface of the thin silicon film, and a second gate electrode formed by a metal film applied on a surface of the second silicon oxide film. In the thin silicon film, there are formed P and N type regions side by side to constitute a PN junction. When a gate bias voltage is applied across the first and second gate electrodes, a band bend having a large height and inclination in a direction perpendicular to the thin silicon film is produced in the depletion region in the vicinity of the PN junction.

Abstract: Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a p-n junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two p-n junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. Minority carriers injected by the diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

Abstract: A MOS transistor is formed in a first low-doped P-type retion coating a second more highly doped P-type region. The transistor comprises an N-type drain region, an N-type source region, and a region contacting the for region. The drain, cource and contacting regions are formed at the surface of the first region. The source and contacting regions are interconnected. An N-type highly doped region extends from the drain region through the first low-doped P-type region to the second more highly doped P-type region.

Abstract: A high voltage avalanche diode formed in an integrated circuit includes vertical power components. The integrated circuit is formed in an N-type semiconductor substrate. The rear surface of the substrate corresponds to a first main electrode of the power components, whose second main electrodes correspond to regions formed in P-type wells which are formed in the front surface of the substrate. The diode includes a P-type region wound substantially as a spiral that is formed in the front surface of the substrate; non-overlapping N-type regions formed in equal number in each turn of the spiral and forming with the spiral elemental avalanche diodes; metallizations connecting in series the elemental diodes; and a connection between an end of the spiral and the first electrode.

Abstract: The hold current of a breakover type surge protection device is increased by irradiating the device with .gamma. or x rays so as to form crystal lattice defects in the semiconductor regions thereof.

Abstract: An integrated protective structure provides protection from electrostatic discharges of structures to an integrated circuit functionally connected to a certain external pin. The protective structure is formed in a single epitaxial tub and includes a triggering Zener diode and a vertical bipolar transistor. The collector region of the vertical bipolar transistor is connected to the pin and constitutes also one of the two terminal regions of the triggering Zener. Around the emitter region and separated therefrom by the smallest distance feasible, is an annular region, having a heavier doping than the base region of the transistor formed with the purpose of intercepting the avalanche current of the Zener junction and distributing it in a uniform manner into the base region of the vertical transistor as well as acting as a shield for eventual electrons moving from the emitter region toward the breakdown junction.

Abstract: An integrated circuit including an array of diodes includes first Schottky diodes, each of which is connected by its cathode to a point to be protected and by its anode to a reference voltage, and second Schottky diodes, each of which is connected by its anode to a point to be protected and by its cathode to the cathode of an avalanche diode, the anode of which is connected to the reference voltage. This integrated circuit includes, in a P-type substrate, a first and a second group of N-type wells; an ohmic contact and a Schottky contact on each well; an N-type region on the upper surface of the substrate; a metallization connecting the ohmic contacts of the first group of wells to the N-type region; a metallization connecting the Schottky contacts of the second wells; metallizations respectively connecting a Schottky contact of the second group of wells to an ohmic contact of the first wells; and a rear surface metallization.

Abstract: An avalanche diode structure incorporated in an integrated circuit is embodied by the lateral junction between two adjacent buried layers having opposite conductivity types and a high doping level. This diode includes: a first highly doped buried layer of the same first conductivity type as the integrated circuit substrate; a second highly doped buried layer of the second conductivity type, surrounding the first buried layer and laterally contacting the first layer; and a third low doped buried layer of the second conductivity type disposed beneath the first buried layer and overlapping with respect to the second layer so as to also contact a portion of the second buried layer.

Abstract: A zener diode having a semiconductor body (1) with a surface zone (1') doped with more than 10.sup.18 atoms/cc, in which at least two regions (2, 3) are provided through diffusion, which regions have substantially the same concentration of doping atoms and adjoin a surface (4) of the surface zone (1') and form p-n junctions (5,6) with the surface zone (1'), a first region (2) having a smaller lateral cross-section and a smaller depth than a second region (3). Both regions (2, 3) are connected to a first connection electrode (7, 8) provided on the surface (4), and a second connection electrode (9), which is spaced apart from the regions (2, 3), is provided on the semiconductor body (1). The first region has a side edge (10) which is formed through lateral diffusion and which is at least partly spaced apart from the second region (3). A higher electric field is created locally in the junction (5) during operation of the zener diode owing to the side edge (10).

Abstract: A monolithic protection component is formed in a P-type low-doped semiconductor substrate. The protection diode comprises, in an upper surface of the substrate, a first and a second N-type well with a mean doping level; at the surface of the first well, a first highly doped P region; at the surface of the second well, a second very highly doped N region; a third very highly doped N region laterally contacting the first well; a fourth highly-doped P region beneath a portion of the lower surface of the third region; a first metallization contacting the surface of the first and second regions which constitute the first diode terminal; and a second metallization coupled to a P-type area extending up to the fourth region and second well, which forms the second terminal of the diode. The protection component provides a unidirectional protection diode. Two of the protection components may be combined in a single structure to provide a bidirectional protection diode.

Abstract: A semiconductor device including a switching device such as a MOSFET or an IGBT, and an avalanche device for protecting the switching device by generating an avalanche current when an overvoltage is applied to the switching device. The avalanche device shares a drift layer, that is, an epitaxial layer with the switching device. With this arrangement, the avalanche voltage of the avalanche device follows changes in the withstanding voltages of the switching device due to variations in the thickness or impurity concentration of the epitaxial layer or temperature. This makes it possible to reduce the margin between the avalanche voltage of the avalanche device and the withstanding voltage of the switching device, and to positively protect the switching device from damage.

Abstract: An avalanche diode is formed in an N layer (20) of a bipolar integrated circuit. The diode comprises a first (P) region (22) and N region (21) disposed inside the first region. The portion of the first region which resides under the N region and close to the interface with the latter has a first doping level. A second (P) region (23) extends under the N region with a second doping level higher than the first close to the junction. A third P region (30) is disposed under the N region and overlaps the second P region. The third region has, at its interface with the N region, a doping level intermediate the first and second doping levels.

Abstract: A semiconductor device having a power switch (12) and a saturation detection diode (13) formed in an upper surface of a semiconductor drift region (11) is provided. The saturation detector diode (13) and the power switch (12) are electrically coupled by the drift region (11). An external signal applied to the detector diode (13) forward biases the detector diode (13) when the drift region (11) potential is below a predetermined voltage and the detector diode (13) becomes reverse biased when the drift region (11) potential is greater than the predetermined voltage.

Abstract: A zener diode with a low reverse breakdown avalanche voltage and the use of zener diode in electrostatic discharge protection circuit is described herein. The low breakdown avalanche voltage is achieved by creating a zener diode with a lightly doped region between the P+ and N+ zones. Zener diode disclosed herein is particularly useful in protection circuits for integrated circuits having features or sizes of one micron or less.

Abstract: A semiconductor device for suppressing transient voltages is adapted for use on high frequency data lines. The semiconductor device combines an avalanche type diode which has high capacitance in series with a rectifying diode which has a capacitance three magnitudes lower. The resultant semiconductor device is fabricated using a single, monolithic silicon die instead of stacking two separate dies as has been done in prior art transient voltage suppressors to achieve the same characteristics. The semiconductor die is adaptable for packaging in surface mountable DIP packages and other common circuit board mountable packages.

Abstract: The efficiency of semiconductor cathodes based on avalanche breakdown is enhanced by using ".delta.-doping" structures. The quantization effects introduced thereby decrease the effective work function. A typical cathode structure has an n-type semiconductor region and a first p-type semiconductor region, with the n-type region having a thickness of at most 4 nanometers.

Abstract: The invention relates to a controllable, temperature-compensated voltage limiter with a p.sup.+ np.sup.+ (or n.sup.+ pn.sup.+) semiconductor structure in which the width and doping of the central zone is selected such that no avalanche or Zener effect appears when voltage is applied to the two outer layers (punch-through diode). In accordance with the invention, the voltage U.sub.B to be limited is applied between the blocking pn-juncture (B-C). In addition, an adjustable auxiliary voltage (U.sub.H) is applied between the other pn-junction (H-C). The punch-through can be set to a higher defined value via the auxiliary voltage U.sub.H, this value being independent of the temperature to a large extent.

Abstract: A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9).

Abstract: An active semiconductor device having a negative resistance based upon a negative effective mass of carriers in the semiconductor. A PN junction formed between semiconductor regions of P and N conductivity types is biased in a constant steady state current condition of a fixed reversible break down in the reverse direction based on the avalanche phenomenon, then the carriers may have negative effective mass in all directions within the region in which the carriers moved out of the transition region and are not so many times scattered by the lattice. The negative resistance relying upon this condition can be directly obtained as output by providing two output electrodes on one of the surfaces of the two types of semiconductor regions which sandwich the PN junction.

Abstract: A circuit for protection from overvoltages of an external electrical connection pad of a circuit integrated in an n type conductivity epitaxial layer formed on a monocrystal semiconductor substrate, comprises a lateral integrated transistor having an emitter connected to said pad, a collector connected to ground and a base connected to said pad across a resistor, and an integrated Zener diode functionally connected between the base and the collector of said transistor.

Abstract: A MOS semiconductor device having a surge protecting circuit comprising a semiconductor substrate having a major surface, a plurality of electrodes overlying the major surface, a MOS circuit in the major surface, and a bidirectional semiconductor surge absorber coupled between the gate of the MOS circuit and a reference electrode contacting the major surface of the substrate. In another embodiment, the MOS semiconductor device further comprises a bidirectional Zener diode connected in series with the bidirectional semiconductor surge absorber.