Abstract: An array substrate and a manufacturing method thereof are disclosed. The method includes: forming a first thin film transistor which includes a first semiconductor layer, a first gate electrode, a first drain electrode and a first source electrode; forming a second thin film transistor which includes a second semiconductor layer, a second gate electrode, a second drain electrode and a second source electrode; and forming a dielectric layer which spaces the first semiconductor layer apart from the second semiconductor layer; the method further includes: processing the same layer to form at least one selected from the group consisting of the first gate electrode, the first drain electrode and the first source electrode, at least one selected from the group consisting of the second gate electrode, the second drain electrode and the second source electrode, and the dielectric layer by the same layer.

Abstract: Described herein are various amorphous metal thin film transistors. Embodiments of such transistors include an amorphous metal gate electrode and a channel conductor formed on a non-conducting substrate. Further embodiments of such transistors include an amorphous metal source electrode, an amorphous metal drain electrode, and a channel conductor formed on a non-conducting substrate. Methods of forming such transistors are also described.

Abstract: A pixel definition layer and a manufacturing method thereof, a display substrate, and a display panel are provided. The pixel definition layer includes: a lyophilic material layer on a base substrate, which includes a plurality of lyophilic portions spaced in pairs, which being with an annular structure and used to define a pixel region; and a lyophobic material layer on a side of the lyophilic material layer from the base substrate, which being filled between each two adjacent lyophilic portions of the plurality of lyophilic portions, and a distance from a surface of the lyophobic material layer from the base substrate to the base substrate is larger than a distance from a surface of the lyophilic material layer from the base substrate to the base substrate. The pixel definition layer improves the uniformity of films formed in the pixel region by the solution.

Abstract: A thin film transistor and a manufacture method thereof, an array substrate and a manufacture method thereof are provided. The manufacture method of the thin film transistor includes: providing a base substrate; and forming a gate electrode, a first electrode, a second electrode and a semiconductor layer of the thin film transistor on the base substrate. At least one of the gate electrode, the first electrode and the second electrode includes N portions that are stacked in a direction perpendicular to the base substrate, adjacent two of the N portions are in direct contact with each other, and N is a positive integer more than or equal to 2. The method includes: performing N patterning processes to respectively form the N portions.

Abstract: Various embodiments of the present disclosure are directed towards a display device. The display device includes an isolation structure disposed over a semiconductor substrate. An electrode is disposed at least partially over the isolation structure. A light-emitting structure is disposed over the electrode. A conductive reflector is disposed below the isolation structure and electrically coupled to the electrode. The conductive reflector is disposed at least partially between sidewalls of the light-emitting structure. The conductive reflector comprises a non-metal-doped aluminum material.

Abstract: A transistor and a method for manufacturing the same, a display substrate, and a display apparatus are provided. The transistor may include: a substrate; an active region on the substrate and including a polycrystalline silicon region; an etch stop layer at a side of the polycrystalline silicon region distal to the substrate; and a first heavily doped amorphous silicon region and a second heavily doped amorphous silicon region both at a side of the etch stop layer distal to the substrate; the polycrystalline silicon region having a first side surface corresponding to the first heavily doped amorphous silicon region and a second side surface corresponding to the second heavily doped amorphous silicon region; wherein an orthographic projection of the polycrystalline silicon region on a plane in which a lower surface of the etch stop layer lies does not go beyond the lower surface of the etch stop layer.

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

Abstract: It is provided a low-temperature polysilicon thin film transistor formed on a substrate, including: a gate electrode on the substrate; an active layer on the gate electrode, the active layer including a channel region, the channel region having a polysilicon region and amorphous silicon regions respectively on both sides of the polysilicon region; and an etch stop layer on the active layer. An orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the gate electrode on the substrate, and an area of the orthogonal projection the polysilicon region on the substrate is smaller than an area of the orthogonal projection of the gate electrode on the substrate. The orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the etch stop layer on the substrate.

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A semiconductor device comprising a first insulating layer, a first oxide semiconductor layer over the first insulating layer, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer and a drain electrode layer over the second oxide semiconductor layer, a second insulating layer over the first insulating layer, the source electrode layer, and the drain electrode layer, a third insulating layer over the second insulating layer, a third oxide semiconductor layer over the second oxide semiconductor layer, a gate insulating layer over the third oxide semiconductor, and a gate electrode layer over the gate insulating layer. The second insulating layer is an oxygen barrier layer and includes a region in contact with side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer.

Abstract: A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a semiconductor device including the transistor are achieved. A semiconductor and a conductor are formed over a substrate, a sacrificial layer is formed over the conductor, and an insulator is formed to cover the sacrificial layer. After that, a top surface of the insulator is removed to expose a top surface of the sacrificial layer. The sacrificial layer and a region of the conductor overlapping with the sacrificial layer are removed, whereby a source region, a drain region, and an opening are formed. Next, a gate insulator and a gate electrode are formed in the opening.

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

Abstract: A method of manufacturing an array substrate is discussed. The method includes forming a gate line on a substrate including a pixel region, forming a gate electrode on the substrate and connected to the gate line, and forming a gate insulating layer on the gate line and the gate electrode. The method further includes forming a data line on the gate insulating layer and crossing the gate line to define the pixel region, forming a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode, and forming an oxide semiconductor layer on top of the source and drain electrodes.

Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other.

Abstract: A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.

Abstract: An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability.

Abstract: A semiconductor device having high electric characteristics and in which a capacitor is efficiently formed even if the semiconductor device has a miniaturized structure. In a top-gate (also referred to as staggered) transistor using an oxide semiconductor film as its active layer, a source electrode and a drain electrode has a two-layer structure (a first electrode film and a second electrode film). Then, a capacitor is formed using a film formed using a material and a step similar to those of the first electrode film, a gate insulating film, and a gate electrode. Accordingly, the transistor and the capacitor can be formed through the same process efficiently. Further, the second electrode is connected onto the oxide semiconductor film between a first electrode and a channel formation region of the transistor. Accordingly, resistance between source and drain electrodes can be reduced; therefore, electric characteristics of the semiconductor device can be improved.

Abstract: An offset transistor and a non-offset transistor each including an oxide semiconductor are formed over one substrate. An oxide semiconductor layer, a gate insulator, and first layer wirings which serve as gate wirings are formed. After that, the offset transistor is covered with a resist and impurities are mixed into the oxide semiconductor layer, so that an n-type oxide semiconductor region is formed. Then, second layer wirings are formed. Through the above steps, the offset transistor and the non-offset transistor (e.g., aligned transistor) can be formed.

Abstract: By reducing the contact resistance between an oxide semiconductor film and a metal film, a transistor that uses an oxide semiconductor film and has excellent on-state characteristics is provided. A semiconductor device includes a pair of electrodes over an insulating surface; an oxide semiconductor film in contact with the pair of electrodes; a gate insulating film over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film interposed therebetween. In the semiconductor device, the pair of electrodes contains a halogen element in a region in contact with the oxide semiconductor film. Further, plasma treatment in an atmosphere containing fluorine can be performed so that the pair of electrodes contains the halogen element in a region in contact with the oxide semiconductor film.

Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.

Abstract: A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.

Abstract: A thin-film semiconductor device according to the present disclosure includes: a substrate; a gate electrode formed above the substrate; a gate insulating film formed on the gate electrode; a channel layer that is formed of a polycrystalline semiconductor layer on the gate insulating film; an amorphous semiconductor layer formed on the channel layer and having a projecting shape in a surface; and a source electrode and a drain electrode that are formed above the amorphous semiconductor layer, and a first portion included in the amorphous semiconductor layer and located closer to the channel layer has a resistivity lower than a resistivity of a second portion included in the amorphous semiconductor layer and located closer to the source and drain electrodes.

Abstract: An organic light emitting diode (OLED) display includes: a substrate; an organic light emitting element formed on the substrate; a first thin film transistor connected to the organic light emitting element and including an amorphous silicon channel region; and at least one other thin film transistor connected to the first thin film transistor and including a polysilicon channel region.

Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.

Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

Abstract: A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.

Abstract: A photoelectric conversion element including a first gate electrode, a first gate insulating layer, a crystalline semiconductor layer, an amorphous semiconductor layer, an impurity semiconductor layer, a source electrode and a drain electrode in contact with the impurity semiconductor layer, a second gate insulating layer covering a region between the source electrode and the drain electrode, and a second gate electrode over the second gate insulating layer. In the photoelectric conversion element, a light-receiving portion is provided in the region between the source electrode and the drain electrode, the first gate electrode includes a light-shielding material and overlaps with the entire surface of the crystalline semiconductor layer and the amorphous semiconductor layer, the second gate electrode includes a light-transmitting material and overlaps with the light-receiving portion, and the first gate electrode is electrically connected to the source electrode or the drain electrode is provided.

Abstract: An array substrate comprises: a base substrate; a gate scanning line, a data scanning line, a pixel electrode and a thin film transistor, formed on the base substrate; and a light blocking layer, formed on the base substrate and corresponding to the thin film transistor and the data scanning line.

Abstract: A means of forming unevenness for preventing specular reflection of a pixel electrode, without increasing the number of process steps, is provided. In a method of manufacturing a reflecting type liquid crystal display device, the formation of unevenness (having a radius of curvature r in a convex portion) in the surface of a pixel electrode is performed by the same photomask as that used for forming a channel etch type TFT, in which the convex portion is formed in order to provide unevenness to the surface of the pixel electrode and give light scattering characteristics.

Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.

Abstract: Disclosed is a semiconductor device 100A that has first lightly doped drain regions 31A1 and 32A1 between a source region 34A1 and a channel region 33A1 of a first conductive-type driver circuit TFT 10A1 and/or between a drain region 35A1 and the channel region 33A1 of the first conductive-type driver circuit TFT 10A1, and second lightly doped drain regions 31C and 32C between a source region 34C and a channel region 33C of a first conductive-type pixel TFT 10C and/or between a drain region 35C and the channel region 33C of the first conductive-type pixel TFT 10C, in which the first lightly doped drain regions 31A1 and 32A1 have first conductive-type impurities n1 at a first impurity concentration C1, and the second lightly doped drain regions 31C and 32C have first conductive-type impurities n1 at the first impurity concentration C1 and second conductive-type impurities p2 at a second impurity concentration C2.

Abstract: The present application provides a thin film transistor and a method of manufacturing same capable of suppressing diffusion of aluminum to oxide semiconductor and selectively etching oxide semiconductor and aluminum oxide. The thin film transistor includes: a gate electrode; a channel layer whose main component is oxide semiconductor; a gate insulating film provided between the gate electrode and the channel layer; a sealing layer provided on the side opposite to the gate electrode, of the channel layer; and a pair of electrodes which are in contact with the channel layer and serve as a source and a drain. The sealing layer includes at least a first insulating film made of a first insulating material, and a second insulating film made of a second insulting material having etching selectivity to each of the oxide semiconductor and the first insulating material and provided between the first insulating film and the channel layer.

Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.

Abstract: Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.

Abstract: Methods for manufacturing a solar cell are provided. The method may include forming a lower electrode on a substrate, forming a light absorption layer on the lower electrode, forming a buffer layer on the light absorption layer, and forming a window layer on the buffer layer. The window layer may include an intrinsic layer and the transparent electrode which have electric characteristics different from each other, respectively. The intrinsic layer and the transparent electrode may be formed by a sputtering process using a single target formed of metal oxide doped with impurities.

Abstract: Provided are a semiconductor device with less leakage current is reduced, a semiconductor device with both of high field effect mobility and low leakage current, an electronic appliance with low power consumption, and a manufacturing method of a semiconductor device in which leakage current can be reduced without an increase in the number of masks. The side surface of a semiconductor layer formed of a semiconductor film having high carrier mobility is not in contact with any of a source electrode and a drain electrode. Further, such a transistor structure is formed without an increase in the number of photomasks and can be applied to an electronic appliance.

Abstract: To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

Abstract: An organic light-emitting display device includes: a substrate having a transistor region and a thin-film transistor having a gate electrode, a source/drain electrode and an active layer sequentially formed on the transistor region, wherein a portion of the source/drain electrode is between the active layer and substrate.

Abstract: A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Abstract: A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.

Abstract: A thin film transistor according to one or more embodiments of the present invention includes: an insulation substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a semiconductor formed on the gate insulating layer and having a pair of openings facing each other; ohmic contact layers formed in the openings and including a conductive impurity; and a source electrode and a drain electrode in contact with their respective ohmic contact layers. An organic light emitting device in accordance with an embodiment includes: a first signal line and a second signal line intersecting each other on an insulation substrate; a switching thin film transistor connected to the first signal line and the second signal line; a driving thin film transistor connected to the switching thin film transistor; and a light emitting diode (LED) connected to the driving thin film transistor.

Abstract: The present invention relates to a semiconductor device including a thin film transistor comprising a microcrystalline semiconductor which forms a channel formation region and includes an acceptor impurity element, and to a manufacturing method thereof. A gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor layer which is formed over the gate insulating film and is formed of a microcrystalline semiconductor, a second semiconductor layer which is formed over the first semiconductor layer and includes an amorphous semiconductor, and a source region and a drain region which are formed over the second semiconductor layer are provided in the thin film transistor. A channel is formed in the first semiconductor layer when the thin film transistor is placed in an on state.

Abstract: It is an object to provide a light-emitting device in which plural kinds of circuits are formed over one substrate and plural kinds of thin film transistors corresponding to characteristics of the plural kinds of circuits are provided. An inverted coplanar thin film transistor in which an oxide semiconductor layer overlaps with a source electrode layer and a drain electrode layer is used for a pixel, and a channel-etched thin film transistor is used for a driver circuit. A color filter layer is provided between the pixel thin film transistor and a light-emitting element which is electrically connected to the pixel thin film transistor so as to overlap with the light-emitting element.

Abstract: An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a-Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.

Abstract: A semiconductor photovoltaic device comprises a semiconductor substrate having a first surface and a second surface, the first surface and the second surface being opposed to each other, a plurality of trenches extending into the semiconductor substrate from the first surface, the first surface being a substantially planar surface, a dopant region in the semiconductor substrate near the first surface and the plurality of trenches, a first conductive layer over the semiconductor substrate, and a second conductive layer on the second surface of the semiconductor substrate.

Abstract: A display device includes a plurality of thin-film transistors formed on a substrate on which a display area is formed. At least one of the plurality of thin-film transistors includes a gate electrode, agate insulating film formed to cover the gate electrode, an interlayer insulating film formed on an upper surface of the gate insulating film and having an opening formed in an area where the gate electrode is formed in plan view, a pair of heavily-doped semiconductor films arranged on an upper surface of the interlayer insulating film with the opening interposed therebetween, a polycrystalline semiconductor film formed across the opening and formed in the area, the polycrystalline semiconductor film being electrically connected to the pair of heavily-doped semiconductor films, and a pair of electrodes formed to overlap the pair of heavily-doped semiconductor films, respectively, without overlapping the polycrystalline semiconductor film.

Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.

Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

Abstract: A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.

Abstract: An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.