Abstract: A semiconductor device for a TFT includes a first semiconductor layer to be used as a channel, which is formed on a portion of an insulating layer in correspondence with an underlying gate electrode. The semiconductor device further includes a second semiconductor layer, an ohmic contact layer, and a metal layer formed on the insulating layer and the first semiconductor layer and patterned to expose portions of the insulating layer and the first semiconductor layer. The patterned metal layer forms source and drain electrodes. The semiconductor device also includes a passivation layer, which covers the insulating layer, the first semiconductor layer and the source and drain electrodes, and a pixel electrode, which contacts the drain electrode though a contact hole in the passivation layer.

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 .mu.m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: A semiconductor element suitable for use in the display region of a liquid crystal display or for use in the drive circuit region for driving the display region is comprised of first, second, third and fourth electrodes; a pair of first conducting type semiconductor layers separated from each other and connected to the second and the third electrodes, respectively; an intrinsic semiconductor layer connected to the pair of the first conductivity type semiconductor layers; and a second conductivity type semiconductor layer formed on the intrinsic semiconductor layer, wherein an insulating film is interposed between the first electrode and the intrinsic semiconductor layer, and the fourth electrode is formed on the second conductivity type semiconductor layer formed on the intrinsic semiconductor layer.

Abstract: There is provided a semiconductor device in which a semiconductor layer and a gate electrode are formed with a gate insulating layer between then and in which a region of the semiconductor layer opposite to the gate electrode is used as a channel region. On the semiconductor layer, an insulating protection film and an amorphous semiconductor layer are successively formed. The protection film covers at least the channel region of the amorphous semiconductor layer, and annealing is applied to the amorphous semiconductor layer, thereby converting the amorphous semiconductor layer into the polycrystal semiconductor layer. A portion to be the channel region of the amorphous semiconductor layer is covered by the protection film. Therefore, even when exposed to the atmosphere due to annealing, surface contamination can be prevented and a semiconductor device having satisfactory characteristics can be obtained. A thickness d of the protection film is set to be nearly ".lambda./4 n" for a wavelength .lambda.

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.

Abstract: Thin-film transistor display devices include composite electrodes which provide low resistance contacts and paths for electrical signals and are less susceptible to parasitic metal migration which can limit display quality and lifetime. In particular, a thin-film transistor (TFT) display device is provided having an insulated gate electrode on a face of a substrate (e.g., transparent substrate) and a semiconductor layer on the insulated gate electrode, opposite the face of the substrate. Spaced apart source and drain electrodes are also provided on the semiconductor layer. These source and drain electrodes each preferably comprise a composite of at least two layers containing respective metals therein of different element type. Preferably, one of the layers comprises a metal which is capable of forming a low resistance contact with electrodes such as a pixel electrode (e.g.

Abstract: A thin film transistor which includes an oxide layer containing a trench; a semiconductor layer formed on the oxide layer, including the trench; a buffer layer formed on the semiconductor layer in the trench; a gate electrode aligned on the semiconductor layer on one side of the trench; and an impurity region formed in the semiconductor layer adjacent the gate electrode on one side of the trench, and an impurity region also formed in the semiconductor layer on the other side of the trench.

Abstract: The number of mask steps used to fabricate a TFT in an AMLCD is reduced. In particular, source and drain metallizations, as well as doped and undoped semiconductor layers are patterned at the same time, and the source and drain metallizations and the doped semiconductor layer are etched in a single etching step using an insulating passivation layer as a mask to form source and drain electrodes. Manufacturing costs can be reduced and the manufacturing yield can be improved.

Abstract: A thin-film transistor including a gate electrode provided on a substrate, a gate insulation film provided on the gate electrode, an operative semiconductor film provided on the gate insulation film, and a channel protection film provided on the operative semiconductor film. Semiconductor contact portions are disposed so that they are covered by the channel protection film on either side of the operative semiconductor film. A source electrode and a drain electrode are connected to the semiconductor contact portions on either side of the channel protection film. The thin-film transistor can minimize the stray capacitance due to the overlapping of the source and drain electrodes with the gate electrode and is excellent in the contact characteristic. Also, a method for fabricating a thin-film transistor is disclosed.

Abstract: A multilayer solar cell with bypass diodes includes a stack of alternating p and n type semiconductor layers 10, 11, 12, 13, 14 arranged to form a plurality of rectifying photovoltaic junctions 15, 16, 17, 18. Contact is made to underlying layers by way of a buried contact structure comprising grooves extending down through all of the active layers, the walls of each groove being doped 33, 34 with n-or p-type impurities depending upon the layers to which the respective contact is to be connected and the grooves being filled with metal contact material 31, 32. One or more bypass diodes are provided by increasing the doping levels on either side 10, 13 of one or more portions of the junctions 16 of the cell such that quantum mechanical tunnelling provides a reverse bias characteristic whereby conduction occurs under predetermined reverse bias conditions. Ideally, the doping levels in the bypass diodes is 10.sup.18 atoms/cm.sup.3 or greater and the junction area is small.

Abstract: A TFT with a drain-offset structure is provided, which realizes a high ON current while keeping an OFF current at a low level. This TFT includes a substrate and a patterned semiconductor film formed on a main surface of the substrate. At least the main surface of the substrate has an insulating property. The patterned semiconductor film is made of a silicon-system semiconductor material and is not monocrystalline. The patterned semiconductor film includes a source region of a first conductivity type, a channel region of a second conductivity type opposite to the first conductivity type, a first drain region of the first conductivity type, and a second drain region of the second conductivity type. The first drain region serves as an offset region. A gate electrode is formed to be opposite to the channel region through a gate insulating film. The source region is formed on one end of the semiconductor film. The second drain region is formed on an opposite end of the semiconductor film to the source region.

Abstract: A sensor device includes a sensing element and a thin film transistor (TFT), and the TFT's channel leads include semiconductor channel leads formed in a layer of microcrystalline silicon (.mu.c-Si). The sensing element is formed in a semiconductor layer that includes silicon-based material and is over the .mu.c-Si layer. Each of the semiconductor channel leads has a structure that prevents formation of bubbles at the lower and upper sides of the .mu.c-Si layer during production of the sensing element. The TFT's channel can be formed in a layer of intrinsic silicon-based material under the .mu.c-Si layer and the .mu.c-Si layer can be a deposited doped layer; or the TFT's channel can be formed in an intrinsic .mu.c-Si layer in which the leads are formed by implanting a dopant. The .mu.

Abstract: A thin-film transistor includes a substrate and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by about 1 to 4 .mu.m. A method of making such a thin film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layer directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.

Abstract: The present invention discloses a hybrid polysilicon/amorphous silicon TFT device for switching a LCD and a method for fabrication wherein a n.sup.+ doped amorphous silicon layer is advantageously used as a mask during a laser annealing process such that only a selected portion of a hydrogenated amorphous silicon layer is converted to a crystalline structure while other portions retain their amorphous structure. As a result, a polysilicon TFT and at least one amorphous silicon TFT are formed in the same structure and the benefits of both a polysilicon TFT and amorphous silicon TFT such as a high charge current and a low leakage current are retained in the hybrid structure.

Abstract: An electro-optical device having a plurality of pixel electrodes, each with at least one thin film transistor. The channel region of the transistor is spoiled by an impurity such as oxygen, carbon, or nitrogen. The photosensitivity of the channel region is reduced by the spoiling impurity and therefore the transistor includes immunity to illumination incident thereupon, which would otherwise impair the normal operation of the transistor. The spoiling impurity is not introduced into transistors that are located such that they do not receive light rays.

Abstract: A TFT-array including a substrate, a gate electrode, a first and second electrode provided on the substrate simultaneously with the gate electrode, an insulating film formed on the gate electrode, the first and the second electrode, a semiconductor layer formed on the gate electrode in such a manner that the insulating film is interposed between the semiconductor layer and the gate electrode, a pair of electrodes, either of which is connected with the first electrode or the second electrode, said pair of electrodes defining a semiconductor element together with the semiconductor layer.

Abstract: A lightly doped drain thin-film transistor having an inverted staggered structure. The transistor has a glass substrate and a gate formed by a Cr layer on the substrate. An insulating layer and a semiconductor layer are deposited on the substrate and the gate. A first photo-resist layer is coated on top of the semiconductor layer. Back-side exposure and self-aligned technique are used to form an unexposed area slightly smaller than the gate area with high energy light. Low energy ion implantation is then performed on the exposed semiconductor layer to produce the lightly doped region. After removing the first photo-resist layer, another photo-resist process including a second photo-resist coating, back-side exposure and self-aligned technique is performed to form an unexposed area slightly larger than the gate area with low energy light. High energy ion implantation is then performed on the exposed semiconductor layer.

Abstract: The effect of a TFT having a Ge--Si contact layer is that a stable etching of the contact layer, without excessive etching of the semiconductor layer can be made due to a good selectivity when etching. Consequently, a uniform channel after a backetch step is obtained and the device performance can be improved.

Abstract: A thin film transistor which can reduce production of leakage current between the source and drain electrodes and a fabricating method therefor, are disclosed. In the thin film transistor, an insulating film is formed on at least a portion of each side, corresponding to the region between the source and drain electrodes, of the peripheral side surface of the intrinsic semiconductor film, so that no metal silicide is formed thereon.

Abstract: A thin film transistor and method includes a substrate and a first semiconductor layer formed on the substrate. A first insulating layer is formed on the first semiconductor layer, and a doped semiconductor layer is formed on an upper portion of the first semiconductor layer at first and second sides of the first insulating layer. A second insulating layer is formed on the first insulating layer and the doped semiconductor layer, the second insulating layer having contact holes. A gate electrode is formed on a portion of the second insulating layer, and source and drain electrodes are formed on portions of the second insulating layer, the source and drain electrodes contacting the doped semiconductor layer through the contact holes, respectively.

Abstract: A combination of a doping process and the use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.

Abstract: A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 may be silicon, quartz, gallium arsenide, glass, ceramic, metal or polyimide. A neutral (undoped) layer 16 of radiation sensitive material is formed over the doped layer 14. First and second source/drain regions 18 and 20 are formed in the neutral layer 16 and extend to a top portion of the doped layer 14. A gate region 22 is formed in a top portion of the neutral layer 16 between the first source/drain region 18 and second source/drain region 20 such that a channel region 24 is formed in the doped layer 14 beneath the gate region 22.

Abstract: A thin film transistor comprises a gate electrode, an insulating layer and a semiconductor layer formed and laminated on an insulating substrate. The insulating layer and the semiconductor layer have the same planar pattern.

Abstract: A thin-film semiconductor element provided on a channel area with a channel protection layer, characterized by the fact that a source electrode layer and a drain electrode layer respectively have overlapping areas on the channel protection layer, the side walls of the source electrode layer and the drain electrode layer extend in the overlapping areas beyond the side wall of the channel protection layer in at least one direction of the width thereof, and the source electrode layer and the drain electrode layer possess points of overlap intersection with the semiconductor layer at the points of overlap intersection thereof with the channel protection layer. Owing to the construction described above, the leakage current generated by exposure to light can be decreased and the thin-film semiconductor element can be produced by a simple process of manufacture.

Abstract: A transparent insulation film is formed on a glass substrate. Source and drain electrodes are formed on the transparent insulation film with their ends in spaced and opposing relation. The entire face of the substrate is treated with PH.sub.3 plasma to diffuse P atoms to form a doped surface layer. An a-Si semiconductor layer is formed on the doped surface layer so as to span a space between the source and drain electrodes with the opposite end portions of the semiconductor layer overlying those electrodes. A gate insulation film is formed on the semiconductor layer to extend all over the substrate. A gate electrode is formed of metal on the top of the gate insulation film 6 such that the opposite side edges of the gate electrode are recessed inwardly of the edges of the source and drain electrodes. An excimer laser beam is radiated against the face of the substrate with the gate electrode acting as a mask so that the laser-irradiated regions of the semiconductor layer comprise source and drain regions of n.

Abstract: A thin film transistor is disclosed, which comprises a transparent insulating substrate, a gate electrode formed over the transparent insulating substrate, a gate insulating layer formed over the gate electrode in such a way that the gate electrode is overlaid with the gate insulating layer, a semiconductor layer having a source region, a drain region, and a channel region, the source region having an ohmic contact portion at least on the front surface thereof, the drain region having an ohmic contact portion at least on the front surface thereof, the ohmic contact portion being doped with impurities, the channel region being formed between the source region and the drain region, a source electrode made of a transparent electrical conductive film, the source electrode being disposed on the front surface of the source region, the source electrode being ohmic contacted to the front surface of the source region, and a drain electrode made of a transparent electrical conductive film, the drain electrode being dis

Abstract: A shift register comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of register cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be recovered or restored when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the register.

Abstract: A thin film transistor structure for use in driving liquid crystal display elements has a semiconductor active layer, a control electrode layer underlying the active layer with an insulating layer interposed therebetween and first and second main electrode layers formed on or above the active layer in a spaced relation with each other to define a channel in the active layer in cooperation with the control electrode layer between the main electrode layers. The active layer has a first peripheral edge portion generally perpendicular to the direction of the channel and a second peripheral edge portion generally not perpendicular to the direction of the channel. The first and/or second main electrode layer extends over the first and/or second peripheral edge portion of the active layer such that at least a part of the first peripheral edge portion and/or at least part of the second peripheral edge portion of the active layer has its side face directly covered with the main electrode layer.

Abstract: In a semiconductor device comprising a wiring to be connected to the source region or the drain region of a thin film transistor, at least a portion of the wiring comprising a wiring part having the same cross-sectional structure as said source region or said drain region, and said wiring part being formed continuously with said source region or said drain region simultaneously with the respective end portions of said wiring portions, said source region and said drain region formed in such a manner that the edge thereof is set back from the end of the semiconductor layer constituting the thin film transistor.

Abstract: A novel structure of a polycrystalline silicon thin film transistor manifested in a drain offset region and a sub-gate structure. The drain offset region is formed between a channel region and a drain region in the polycrystalline silicon thin film. The sub-gate structure comprises at least one sub-gate, except for a main gate which is provided in a normal field effect transistor. This structure is applicable to either an upper gate type or a bottom gate type thin film transistor. The sub-gate structure may include an upper sub-gate and/or a bottom sub-gate. The upper sub-gate overlays the channel region, drain offset and drain regions through an insulation layer. The bottom sub-gate underlies the channel region, drain offset and drain regions through an insulation layer. The sub-gate is applied with the same voltage or less as the drain voltage thereby permitting a relaxation of a high field concentration caused at a drain junction to be realized.

Abstract: The thin film transistor of the invention includes a substrate; a gate electrode formed on the substrate; a semiconductor layer insulated from the gate electrode, the semiconductor layer being formed on the substrate to cover the gate electrode; a first contact layer and a second contact layer which are made of n-type microcrystalline silicon having a resistivity of 10 .OMEGA.cm or less, the first and second contact layers being in contact with the semiconductor layer so as cover part of the gate electrode; a source electrode which is in contact with part of the first contact layer; and a drain electrode which is in contact with part of the second contact layer.

Abstract: A thin film transistor comprising a gate electrode of electrically conductive material, a semiconducting material, a gate insulating material located between the gate electrode and the semiconducting material, a source electrode of electrically conductive material adjacent to the semiconducting material, a drain electrode of electrically conductive material adjacent to the semiconducting material, and a light intercepting material for preventing the incidence of light on the semiconducting material wherein the light interrupting material layer is formed of the same electrically conductive material as the source electrode and the drain electrode.

Abstract: A thin-film transistor includes a gate electrode and a semiconductor film consisting of amorphous silicon, formed on an insulating substrate to oppose each other through a gate insulating film, ohmic contact layers composed of n-type amorphous silicon doped with an impurity, electrically insulated from each other on the semiconductor film, and electrically connected to the semiconductor film, and source and drain electrodes arranged on the semiconductor film with a predetermined gap to form a channel portion, and electrically connected to the semiconductor film through the ohmic contact layers. The gate electrode and a portion surrounding the gate electrode are entirely formed into a continuous metal oxide film by a chemical reaction.

Abstract: An electrically plastic device comprising an amorphous silicon semiconductor layer including movable dopant formed between a pair of electrodes and; at least one gate electrode formed on said amorphous silicon semiconductor layer through an insulation layer or a high resistance layer; whereby the operation of said gate electrode controls the dopant distribution of said amorphous semiconductor layer, thereby varying the electrical conductivity thereof.

Abstract: The TFT structure formed in accordance with this invention includes a TFT body that has channel plug end sidewalls separated by a distance equal to or less than the width of the source/drain address lines and such that no residual doped semiconductor material adheres to the sidewalls. Similarly, the intrinsic semiconductor material layer is shaped such that no residual doped semiconductor material adheres to the sidewalls of the intrinsic semiconductor material layer underlying the channel plug ends.

Abstract: A thin-film transistor basically comprises an insulating substrate, a gate electrode formed on the substrate, a gate insulating layer covering the gate electrode, a semiconductor layer formed on the gate insulating layer, and source/drain electrodes electrically connected to the semiconductor layer. An insulating layer is interposed between the source/drain electrodes and the semiconductor layer, and the source/drain electrodes are electrically connected to the semiconductor layer through a pair of openings provided in the insulating layer. The connection to the semiconductor layer is made directly or via an electrical connection member.

Abstract: An active-matrix display device having low-resistance added capacitance electrode wires in which single or plural secondary wires connected electrically to the added capacitance electrode wires reduce the apparent electrical resistance of the added capacitance electrode wires, which makes the time constant of the added capacitance electrode wires smaller, so that the charging characteristics of the added capacitance are improved and contrast and other display characteristics of the liquid crystal display device are improved.

Abstract: A thin film transistor of amorphous silicon is supported by an insulated gate on an insulating substrate and has the opposite side covered with a shading layer of amorphous silicon containing germanium in an amount more than 30% atomic density.

Abstract: A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a second semi-conductor region formed primarily of semi-amorphous semiconductor. The second semi-conductor region has a higher degree of conductivity than the first semiconductor region so that a semi-conductor element may be formed.