Abstract: An etching technique for the fabrication of thin (Al, In, Ga)N layers. A suitable template or substrate is selected and implanted with foreign ions over a desired area to create ion implanted material. A regrowth of a device structure is then performed on the implanted template or substrate. The top growth surface of the template is bonded to a carrier wafer to created a bonded template/carrier wafer structure. The substrate is removed, as is any residual material, to expose the ion implanted material. The ion implanted material on the bonded template/carrier wafer structure is then exposed to a suitable etchant for a sufficient time to remove the ion implanted material.

Abstract: This invention provides a selfsupporting substrate which consists of a n-type conductive aluminum nitride semiconductor crystal and is useful for manufacturing the vertical conductive type AlN semiconductor device. The n-type conductive aluminum nitride semiconductor crystal, by which the selfsupporting substrate is made up, contains Si atom at a concentration of 1×1018 to 5×1020 cm?3, is substantially free from halogen atoms, and substantially does not absorb the light having the energy of not more than 5.9 eV. The selfsupporting substrate can be obtained by a method comprising the steps of forming an AlN crystal layer on a single crystal substrate such as a sapphire by the HVPE method, preheating the obtained substrate having the AlN crystal layer to a temperature of 1,200° C. or more, forming a second layer consisting of the n-type conductive aluminum nitride semiconductor crystal is formed on the AlN crystal layer in high rate by the HVPE method and separating the second layer from the obtained laminate.

Abstract: In a separation method of a nitride semiconductor layer, a graphene layer in the form of a single layer or two or more layers is formed on a surface of a first substrate. A nitride semiconductor layer is formed on the graphene layer so that the nitride semiconductor layer is bonded to the graphene layer with a bonding force due to regularity of potential at atomic level at an interface therebetween without utilizing covalent bonding. The nitride semiconductor layer is separated from the first substrate with a force which is greater than the bonding force between the nitride semiconductor layer and the graphene layer, or greater than a bonding force between respective layers of the graphene layer.

Abstract: A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects.

Abstract: A high quality Group III-Nitride semiconductor crystal with ultra-low dislocation density is grown epitaxially on a substrate via a particle film with multiple vertically-arranged layers of spheres with innumerable micro- and/or nano-voids formed among the spheres. The spheres can be composed of a variety of materials, and in particular silica or silicon dioxide (SiO2).

Abstract: The present invention provides a method of manufacturing a semiconductor substrate that includes a substrate, a first semiconductor layer arranged on the substrate, a metallic material layer arranged on the first semiconductor layer, a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer, and a cavity formed in the first semiconductor layer under the metallic material layer.

Abstract: A thin-film LED includes an insulating substrate, an electrode on the insulating substrate, and an epitaxial structure on the electrode.

Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.

Abstract: A semiconductor process for improved etch control in which an anisotropic selective etch is used to better control the shape and depth of trenches formed within a semiconductor material. The etchants exhibit preferential etching along at least one of the crystallographic directions, but exhibit an etch rate that is much slower in a second crystallographic direction. As such, one dimension of the etching process is time controlled, a second dimension of the etching process is self-aligned using sidewall spacers of the gate stack, and a third dimension of the etching process is inherently controlled by the selective etch phenomenon of the selective etchant along the second crystallographic direction. A deeper trench is implemented by first forming a lightly doped drain (LDD) region under the gate stack and using the sidewall spacers in combination with the LDD regions to deepen the trenches formed within the semiconductor material.

Abstract: To produce a Group III nitride-based compound semiconductor having a m-plane main surface and uniformly oriented crystal axes. A mesa having a side surface having an off-angle of 45° or less from c-plane is formed in a a-plane main surface of a sapphire substrate. Subsequently, trimethylaluminum is supplied at 300° C. to 420° C., to thereby form an aluminum layer having a thickness of 40 ? or less. The aluminum layer is nitridated to form an aluminum nitride layer. Through the procedure, a Group III nitride-based compound semiconductor is epitaxially grown only from a side surface of the mesa having an off-angle of 45° or less from c-plane in the sapphire substrate having an a-plane main surface. Thus, a Group III nitride-based compound semiconductor having m-plane which is parallel to the main surface of the sapphire substrate can be formed.

Abstract: A nitride semiconductor chip is provided that offers enhanced luminous efficacy as a result of an improved EL emission pattern. The nitride semiconductor laser chip (nitride semiconductor chip) has an n-type GaN substrate having as a principal growth plane a plane having an off-angle in the a-axis direction relative to the m plane, and a nitride semiconductor layer formed on the principal growth plane of the n-type GaN substrate. The n-type GaN substrate includes a depressed portion (carved region), which is carved from the principal growth plane in the thickness direction, and an uncarved region, which is a region not carved. The nitride semiconductor layer formed on the n-type GaN substrate has a gradient thickness region whose thickness decreases in a gradient fashion toward the depressed portion (carved region) and an emission portion formation region whose thickness varies very little. In the emission portion formation region 6, a ridge portion is formed.

Abstract: The present invention provides semiconductor structures comprising a substrate and at least three III-V and/or II-VI multi junction building blocks, each comprising a p-n junction having at least two alloy layers, formed over the substrate, provided at least one multi-junction building block comprises II-VI alloy layers. Further described are methods for preparing semiconductor structures utilizing a sacrificial or etch-stop ternary III-V alloy layer over an III-V substrate.

Abstract: The present invention provides a method for producing a semiconductor substrate, the method including reacting nitrogen (N) with gallium (Ga), aluminum (Al), or indium (In), which are group III elements, in a flux mixture containing a plurality of metal elements selected from among alkali metals and alkaline earth metals, to thereby grow a group III nitride based compound semiconductor crystal. The group III nitride based compound semiconductor crystal is grown while the flux mixture and the group III element are mixed under stirring. At least a portion of a base substrate on which the group III nitride based compound semiconductor crystal is grown is formed of a flux-soluble material, and the flux-soluble material is dissolved in the flux mixture, at a temperature near the growth temperature of the group III nitride based compound semiconductor crystal, during the course of growth of the semiconductor crystal.

Abstract: A method of forming an iron-doped gallium nitride for a semi-insulating GaN substrate is provided. A substrate (1), such as a (0001)-cut sapphire substrate, is placed on a susceptor of a metalorganic hydrogen chloride vapor phase apparatus (11). Next, gaseous iron compound GFe from a source (13) for an iron compound, such as ferrocene, and hydrogen chloride gas G1HCl from a hydrogen chloride source (15) are caused to react with each other in a mixing container (16) to generate gas GFeComp of an iron-containing reaction product, such as iron chloride (FeCl2). In association with the generation, the iron-containing reaction product GFeComp, first substance gas GN containing elemental nitrogen from a nitrogen source (17), and second substance gas GGa containing elemental gallium are supplied to a reaction tube (21) to form iron-doped gallium nitride (23) on the substrate (1).

Abstract: A semiconductor structure comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first portion of the seed layer is electrically insulated from the second portion of the seed layer. A first semiconductor device is formed in the elemental semiconductor layer. A second semiconductor device is formed in the compound semiconductor layer. The second semiconductor device includes: a first electrode in contact with a first region of the compound semiconductor layer; a second electrode in contact with a second region of the compound semiconductor layer; and a third electrode. The third electrode controls carriers passing in a third region of the compound semiconductor layer disposed between the first region and the second region. A fourth electrode is in electrical contact with the second portion of the seed layer.

Abstract: A GaN layer functions as an electron transit layer and is formed to exhibit, at least at a portion thereof, A/B ratio of 0.2 or less obtained by a photoluminescence measurement, where “A” is the light-emission intensity in the 500-600 nm band, and “B” is the light-emission intensity at the GaN band-edge.

Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.

Abstract: AlxInyGa1-x-yN (0?x?1; 0?x?1; 0?x+y?1) layered device chips are produced by the steps of preparing a defect position controlled substrate of AlxInyGa1-x-yN (0?x?1; 0?y?1; 0?x+y?1) having a closed loop network defect accumulating region H of slow speed growth and low defect density regions ZY of high speed growth enclosed by the closed loop network defect accumulating region H, growing epitaxial upper layers B selectively on the low defect density regions ZY, harmonizing outlines and insides of device chips composed of the upper layers B with the defect accumulating region H and the low defect density regions ZY respectively, forming upper electrodes on the upper layers B or not forming the electrodes, dissolving bottom parts of the upper layers B by laser irradiation or mechanical bombardment, and separating the upper layer parts B as device chips C from each other and from the substrate S.

Abstract: A method and structure for producing lasers having good optical wavefront characteristics, such as are needed for optical storage includes providing a laser wherein an output beam emerging from the laser front facet is essentially unobstructed by the edges of the semiconductor chip in order to prevent detrimental beam distortions. The semiconductor laser structure is epitaxially grown on a substrate with at least a lower cladding layer, an active layer, an upper cladding layer, and a contact layer. Dry etching through a lithographically defined mask produces a laser mesa of length lc and width bm. Another sequence of lithography and etching is used to form a ridge structure with width won top of the mesa. The etching step also forming mirrors, or facets, on the ends of the laser waveguide structures. The length ls and width bs of the chip can be selected as convenient values equal to or longer than the waveguide length lc and mesa width bm, respectively.

Abstract: Various embodiments provide thin-walled structures and methodologies for their formation. In one embodiment, the thin-walled structure can be formed by disposing a semiconductor material in a patterned aperture using a selective growth mask that includes a plurality of patterned apertures, followed by a continuous growth of the semiconductor material using a pulsed growth mode. The patterned aperture can include at least one lateral dimension that is small enough to allow a threading defect termination at sidewall(s) of the formed thin-walled structure. In addition, high-quality III-N substrate structures and core-shell MQW active structures can be formed from the thin-walled structures for use in devices like light emitting diodes (LEDs), lasers, or high electron mobility transistors (HEMTs).

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: High temperature semiconducting materials in a freestanding epitaxial chip enables the use of high temperature interconnect and bonding materials. Process materials can be used which cure, fire, braze, or melt at temperatures greater than 400 degrees C. These include, but are not limited to, brazing alloys, laser welding, high-temperature ceramics and glasses. High temperature interconnect and bonding materials can additionally exhibit an index of refraction intermediate to that of the freestanding epitaxial chip and its surrounding matrix. High index, low melting point glasses provide a hermetic seal of the semiconductor device and also index match the freestanding epitaxial chip thereby increasing extraction efficiency. In this manner, a variety of organic free semiconducting devices, such as solid-sate lighting sources, can be created which exhibit superior life, efficiency, and environmental stability.

Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.

Abstract: A nitride semiconductor substrate is provided, having a concave or convex warpage on a front surface side, wherein when a rear surface side is placed on a flat surface, an average roughness of the rear surface at a part not in contact with the flat surface and at a part where a height from the flat surface to the rear surface is a prescribed value or more is set to be greater than an average roughness of the rear surface at a part where the height from the flat surface including a part in contact with the flat surface to the rear surface is less than the prescribed value.

Abstract: A semi-conductor crystal and method of forming the same. The method includes providing a flow of dopant and column III element containing gases, then stopping flow of dopant and column III element containing gases, reducing the temperature, restarting flow of column III containing gases and then elevating the temperature.

Abstract: A primary surface 23a of a supporting base 23 of a light-emitting diode 21a tilts by an off-angle of 10 degrees or more and less than 80 degrees from the c-plane. A semiconductor stack 25a includes an active layer having an emission peak in a wavelength range from 400 nm to 550 nm. The tilt angle “A” between the (0001) plane (the reference plane SR3 shown in FIG. 5) of the GaN supporting base and the (0001) plane of a buffer layer 33a is 0.05 degree or more and 2 degrees or less. The tilt angle “B” between the (0001) plane of the GaN supporting base (the reference plane SR4 shown in FIG. 5) and the (0001) plane of a well layer 37a is 0.05 degree or more and 2 degrees or less. The tilt angles “A” and “B” are formed in respective directions opposite to each other with reference to the c-plane of the GaN supporting base.

Abstract: An electronic device made of group III/N materials and a method of fabricating the device. The method includes growing by epitaxy on a substrate layer the following successive layers: a layer adapted to contain an electron gas, a barrier layer, and a surface layer. The method also includes an etching step performed on at least part of the surface layer. After the etching step, an epitaxial regrowth is performed to grow a covering layer on the etched surface layer. The material of the surface layer and the material of the covering layer include at least one Group III element and nitrogen.

Abstract: A method of manufacturing a semiconductor layer with which inactivation of impurity is able to be inhibited by a simple method, a semiconductor layer in which inactivation of impurity is inhibited, a method of manufacturing a laser diode with which inactivation of impurity is able to be inhibited by a simple method, and a laser diode including a semiconductor layer in which inactivation of impurity is inhibited are provided. In the method of manufacturing a semiconductor layer, after a semiconductor layer is formed by epitaxial growth with the use of AsH3, supply of AsH3 is stopped without separately supplying new gas when process temperature is 500 deg C. or more.

Abstract: A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C).

Abstract: A group-III nitride structure includes a substrate 102 and a fine wall-shaped structure 110 disposed to stand on the substrate 102 in a vertical direction relative to a surface of the substrate 102 and extending in an in-plane direction of the substrate 102. The fine wall-shaped structure 110 contains a group-III nitride semiconductor crystal, and h is larger than d assuming that the height of the fine wall-shaped structure 110 is h and the width of the fine wall-shaped structure 110 in a direction perpendicular to the height direction and the extending direction is d.

Abstract: A GaN layer is grown on a sapphire substrate, an SiO2 film is formed on the GaN layer, and a GaN semiconductor layer including an MQW active layer is then grown on the GaN layer and the SiO2 film using epitaxial lateral overgrowth. The GaN based semiconductor layer is removed by etching except in a region on the SiO2 film, and a p electrode is then formed on the top surface of the GaN based semiconductor layer on the SiO2 film, to join the p electrode on the GaN based semiconductor layer to an ohmic electrode on a GaAs substrate. An n electrode is formed on the top surface of the GaN based semiconductor layer.

Abstract: During the growth of a nitride semiconductor crystal on a nonpolar face nitride substrate, such as an m-face, the gas that constitutes the main flow in the process of heating up to a relatively high temperature range, before growth of the nitride semiconductor layer, (the atmosphere to which the main nitride face of the substrate is exposed) and the gas that constitutes the main flow until growth of first and second nitride semiconductor layers is completed (the atmosphere to which the main nitride face of the substrate is exposed) are primarily those that will not have an etching effect on the nitride, while no Si source is supplied at the beginning of growth of the nitride semiconductor layer. Therefore, nitrogen atoms are not desorbed from near the nitride surface of the epitaxial substrate, thus suppressing the introduction of defects into the epitaxial film. This also makes epitaxial growth possible with a surface morphology of excellent flatness.

Abstract: A group III nitride semiconductor composite substrate includes a substrate composed of a conductive material having a melting point of not less than 100° C., a group III nitride layer provided on the substrate, and a group III nitride single crystal film provided on the group III nitride layer. The group III nitride layer includes an undulation including a periodic roughness in a surface of the group III nitride layer contacted with the group III nitride single crystal film. The undulation includes a 1-dimensional power spectral density of less than 500 nm3 in the spatial wavelength region of not less than 0.1 (/?m) and less than 1 (/?m).

Abstract: A host substrate and method of making a host substrate for nitride based thin-film semiconductor devices are provided. According to one embodiment, the method includes the steps of providing a silicon layer; etching a pattern of holes in the silicon layer; plating the silicon layer with copper to fill the holes etched in the silicon layer; bonding the silicon layer to a gallium nitride (GaN) layer, the GaN layer attached to a sapphire substrate; and removing the sapphire substrate. The host substrate is configured to address the coefficient of thermal expansion (CTE) mismatch problem and reduce the amount of stress resulting from such CTE mismatch. A combination of metal and semiconductor materials provide for the desired thermal and electrical conductivity while providing for subsequent dicing and incorporation of the finished semiconductor devices into other circuits.

Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

Abstract: An organic thin film transistor substrate includes a gate line formed on a substrate, a data line intersecting the gate line and defining a subpixel area, an organic thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and an organic semiconductor layer forming a channel between the source and drain electrodes, a passivation layer parallel with the gate line, for covering the organic semiconductor layer and peripheral regions of the organic semiconductor layer, and a bank insulating layer for determining the position of the organic semiconductor layer and the passivation layer.

Abstract: In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.

Abstract: An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces.

Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.

Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.

Abstract: A Group III nitride semiconductor substrate is formed of a Group III nitride single crystal, and has a diameter of not less than 25.4 mm and a thickness of not less than 150 ?m. The substrate satisfies that a ratio of ??/? is not more than 0.1, where ? is a thermal expansion coefficient calculated from a temperature change in outside dimension of the substrate, and ?? is a difference (???L) between the thermal expansion coefficient ? and a thermal expansion coefficient ?L calculated from a temperature change in lattice constant of the substrate.

Abstract: Light emitting devices include a gallium nitride-based epitaxial structure that includes an active light emitting region and a gallium nitride-based outer layer, for example gallium nitride. A indium nitride-based layer, such as indium gallium nitride, is provided directly on the outer layer. A reflective metal layer or a transparent conductive oxide layer is provided directly on the indium gallium nitride layer opposite the outer layer. The indium gallium nitride layer forms a direct ohmic contact with the outer layer. An ohmic metal layer need not be used. Related fabrication methods are also disclosed.

Abstract: A method for improving the growth morphology of (Ga,Al,In,B)N thin films on nonpolar or semipolar (Ga,Al,In,B)N substrates, wherein a (Ga,Al,In,B)N thin film is grown directly on a nonpolar or semipolar (Ga,Al,In,B)N substrate or template and a portion of the carrier gas used during growth is comprised of an inert gas. Nonpolar or semipolar nitride LEDs and diode lasers may be grown on the smooth (Ga,Al,In,B)N thin films grown by the present invention.

Abstract: A nitride crystal or wafer with a removable surface layer comprises a high quality nitride base crystal, a release layer, and a high quality epitaxial layer. The release layer has a large optical absorption coefficient at wavelengths where the base crystal is substantially transparent and may be etched under conditions where the nitride base crystal and the high quality epitaxial layer are not. The high quality epitaxial layer may be removed from the nitride base crystal by laser liftoff or by chemical etching after deposition of at least one epitaxial device layer. The nitride crystal with a removable surface layer is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.

Abstract: An active layer of a first conductive-type includes a channel area. A first contact area and a second contact area of a second conductive-type are formed at positions across the channel area. A source electrode is formed on the first contact area. A drain electrode is formed on the second contact area. A gate electrode is formed above the channel area via a gate insulating layer. A reduced surface field zone of the second conductive-type is formed in the channel area at a position close to the second contact area. Thickness of the reduced surface field zone is 30 nanometers to 100 nanometers.

Abstract: Disclosed is a method for producing a group III nitride crystal substrate. A group III nitride crystal is formed by a growth method using a flux. The group III nitride crystal substrate is heat treated at a temperature equal to or higher than the lowest temperature at which the flux contained inside the group III nitride crystal substrate through intrusion into the crystal during the crystal formation can be discharged to outside the group III nitride crystal substrate, and equal to or lower than the highest temperature at which the surface of the group III nitride crystal substrate is not decomposed.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer that comprises composite laminations of which a first semiconductor layer, that is formed of a compound semiconductor of a nitride system, that has a lattice constant to be as smaller than that of such the substrate, and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and a second semiconductor layer that is formed of a compound semiconductor of a nitride system are formed as alternately on to such the substrate; a semiconductor operation layer that is formed of a compound semiconductor of a nitride system and that is formed on to such the buffer layer; and a dislocation reduction layer, which comprises a lower layer region and an upper layer region that are formed at any location at an inner side of such the buffer layer and that comprise an interface of a concave and convex shape therebetween, at which a threading dislocation that draws from such the lower layer region toward such the upper l

Abstract: The invention described herein provides for thin films and methods of making comprising inorganic semiconductor-nanocrystals dispersed in semiconducting-polymers in high loading amounts. The invention also describes photovoltaic devices incorporating the thin films.

Abstract: A group III-V nitride-based semiconductor substrate includes a group III-V nitride-based semiconductor crystal. A surface area of the substrate is greater than or equal to 45 cm2. A thickness of the substrate is greater than or equal to 200 ?m. An in-plane dislocation density of the substrate is less than or equal to 2×107 cm?2 in average. The in-plane dislocation density of the substrate is less than or equal to 150% of the average at maximum.

Abstract: An nitride semiconductor device for the improvement of lower operational voltage or increased emitting output, comprises an active layer comprising quantum well layer or layers and barrier layer or layers between n-type nitride, semiconductor layers and p-type nitride semiconductor layers, wherein said quantum layer in said active layer comprises InxGa1—xN (0<x<1) having a peak wavelength of 450 to 540 nm and said active layer comprises laminating layers of 9 to 13, in which at most 3 layers from the side of said n-type nitride semiconductor layers are doped with an n-type impurity selected from the group consisting of Si, Ge and Sn in a range of 5×1016 to 2×1018/cm3.