Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer.

Abstract: In one embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a partial vacuum atmosphere at a temperature conducive for air adsorbed molecules to desorb, surface molecule groups to decompose, and elemental Sb to evaporate from a surface of the AlSb crystal and exposing the AlSb crystal to an atmosphere comprising oxygen to form a crystalline oxide layer on the surface of the AlSb crystal. In another embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a non-oxidizing atmosphere at a temperature conducive for decomposition of an amorphous oxidized surface layer and evaporation of elemental Sb from the AlSb crystal surface and forming stable oxides of Al and Sb from residual surface oxygen to form a crystalline oxide layer on the surface of the AlSb crystal.

Abstract: Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed exposing the metal material to a temperature sufficient it to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.

Abstract: A laminated semiconductor wafer (10) to be processed is provided with a substrate (110) and a laminated semiconductor layer (100) formed on the substrate (110). The laminated semiconductor wafer (10) is heated to a temperature above the sublimation point of the laminated semiconductor layer (100) and under the melting point of the substrate (110). As a result, in the laminated semiconductor wafer (10), the laminated semiconductor layer (100) sublimes, and the laminated semiconductor layer (100) is eliminated from the substrate (110). In this way, the laminated semiconductor layer is eliminated from the laminated semiconductor wafer while suppressing damage to the substrate.

Abstract: An epitaxial substrate for electronic devices, in which current flows in a lateral direction and of which warpage configuration is properly controlled, and a method of producing the same. The epitaxial substrate for electronic devices is produced by forming a bonded substrate by bonding a low-resistance Si single crystal substrate and a high-resistance Si single crystal substrate together; forming a buffer as an insulating layer on a surface of the bonded substrate on the high-resistance Si single crystal substrate side; and producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate. The resistivity of the low-resistance Si single crystal substrate is 100 ?·cm or less, and the resistivity of the high-resistance Si single crystal substrate is 1000 ?·cm or more.

Abstract: A substrate structure is described, including a starting substrate, crystal piers on the starting substrate, and a mask layer. The mask layer covers an upper portion of the sidewall of each crystal pier, is connected between the crystal piers at its bottom, and is separated from the starting substrate by an empty space between the crystal piers. An epitaxial substrate structure is also described, which can be formed by growing an epitaxial layer over the above substrate structure form the crystal piers. The crystal piers may be broken after the epitaxial layer is grown.

Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.

Abstract: The nitride semiconductor device includes an insulating layer and a metal layer formed on a nitride semiconductor layer. The insulating layer makes contact with the nitride semiconductor layer. A separation preventing layer is formed between the insulating layer and the metal layer so as to make contact with each of these layers. The separation preventing layer includes, as a main component, at least one oxide of a metal selected from a group of metals consisting of tungsten, molybdenum, chromium, titanium, nickel, hafnium, zinc, indium and yttrium.

Abstract: A nitride semiconductor template including a substrate, a mask layer, a first nitride semiconductor layer and a second nitride semiconductor is provided. The substrate has a plurality of trenches, each of the trenches has a bottom surface, a first inclined sidewall and a second inclined sidewall. The mask layer covers the second inclined sidewall and exposes the first inclined sidewall. The first nitride semiconductor layer is disposed over the substrate and the mask layer. The first nitride semiconductor layer fills the trenches and in contact with the first inclined sidewall. The first nitride semiconductor layer has voids located outside the trenches and parts of the mask layer are exposed by the voids. The first nitride semiconductor layer has a plurality of nano-rods. The second nitride semiconductor layer covers the nano-rods. The spaces between the nano-rods are not entirely filled by the second nitride semiconductor layer.

Abstract: Provided is an apparatus for manufacturing a compound semiconductor by use of metal organic chemical vapor deposition including: a reaction container; a holder on which a formed body is to be placed so that a formed surface of the formed body on which layers of a compound semiconductor are to be formed faces upward, the holder being arranged in the reaction container; and a material supply port supplying a material gas of the compound semiconductor into the reaction container from outside, wherein the holder includes a support member supporting the formed body so that an undersurface of the formed body and a top surface of the holder on which the formed body is to be placed keep a predetermined distance.

Abstract: A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0?x1<x2?1” is found when a composition of the first AlGaN layer is represented by Alx1Ga1-x1N, and a composition of the second AlGaN layer is represented by Alx2Ga1-x2N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.

Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (RMS) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers.

Abstract: A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The dopant impurity concentration in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer. The gate electrode has a gate length in a range from 0.2 ?m to 0.6 ?m.

Abstract: A semiconductor device and a method for manufacturing the device are disclosed in which the semiconductor device includes ohmic contacts on different planes and the method for manufacturing the device includes etching a semiconductor stack of different conductivity semiconductor layers in successive steps to create a first opening of a first width in a first semiconductor layer to expose another semiconductor layer, and then a second opening of a narrower width in the another layer, whereby a portion of the another layer remains exposed for receiving an ohmic contact.

Abstract: Material layer structures that have high mobility, a high conduction band barrier and materials that can be implanted to enable higher performance FET device. The structures contain a quantum well layer disposed between two barriers and disposed above a buffer layer and a substrate.

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.

Abstract: A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or stripe masking portions having a width or diameter of 10 to 100 ?m and arranged at a spacing of 250 to 10,000 ?m; growing a nitride semiconductor crystal on the underlying substrate by hydride vapor phase epitaxy (HVPE) at a growth temperature of 1,040° C. to 1,150° C. by supplying a group III source gas, a group V source gas, and a silicon-containing gas in a V/III ratio of 1 to 10; and removing the underlying substrate, thus forming a free-standing conductive nitride semiconductor crystal substrate having a resistivity r of 0.0015 ?cm?r?0.01 ?cm, a thickness of 100 ?m or more, and a radius of bow curvature U of 3.5 m?U?8 m.

Abstract: A III-N layer structure is described that includes a III-N buffer layer on a foreign substrate, an additional III-N layer, a first III-N structure, and a second III-N layer structure. The first III-N structure atop the III-N buffer layer includes at least two III-N layers, each having an aluminum composition, and the III-N layer of the two III-N layers that is closer to the III-N buffer layer having the larger aluminum composition. The second III-N structure includes a III-N superlattice, the III-N superlattice including at least two III-N well layers interleaved with at least two III-N barrier layer. The first III-N structure and the second III-N structure are between the additional III-N layer and the foreign substrate.

Abstract: Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.

Abstract: A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m3/2.

Abstract: A nitride light emitting diode, on a patterned substrate, comprising a nitride interlayer having at least two periods of alternating layers of InxGa1?xN and InyGa1?yN where 0<x<1 and 0?y<1, and a nitride based active region having at least one quantum well structure on the nitride interlayer.

Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: There is provided a compound semiconductor substrate prepared by forming a point defect in an inside structure thereof by implanting an electrically-neutral impurity with energy of 0.1 to 10 MeV on a surface of the substrate. When the compound semiconductor is undoped, electrical resistance increases to increase insulating properties, and when the compound semiconductor is doped with an n-type dopant, the impurity is implanted and charge concentration of the substrate increases to increase conductive properties. In accordance with the present invention, the various electrical properties needed for the compound semiconductor can be effectively controlled by increasing the insulating properties of the undoped compound semiconductor or by increasing the charge concentration of the n-type compound semiconductor, and the application range to various devices can be expanded.

Abstract: Provided is a Group III nitride semiconductor device, which comprises an electrically conductive substrate including a primary surface comprised of a first gallium nitride based semiconductor, and a Group III nitride semiconductor region including a first p-type gallium nitride based semiconductor layer and provided on the primary surface. The primary surface of the substrate is inclined at an angle in the range of not less than 50 degrees, and less than 130 degrees from a plane perpendicular to a reference axis extending along the c-axis of the first gallium nitride based semiconductor, an oxygen concentration Noxg of the first p-type gallium nitride based semiconductor layer is not more than 5×1017 cm?3, and a ratio (Noxg/Npd) of the oxygen concentration Noxg to a p-type dopant concentration Npd of the first p-type gallium nitride based semiconductor layer is not more than 1/10.

Abstract: A production process for a nitride semiconductor crystal, comprising growing a semiconductor layer on a seed substrate to obtain a nitride semiconductor crystal, wherein the seed substrate comprises a plurality of seed substrates made of the same material, at least one of the plurality of seed substrates differs in the off-angle from the other seed substrates, and a single semiconductor layer is grown by disposing the plurality of seed substrates in a semiconductor crystal production apparatus, such that when the single semiconductor layer is grown on the plurality of seed substrates, the off-angle distribution in the single semiconductor layer becomes smaller than the off-angle distribution in the plurality of seed substrates.

Abstract: An optoelectronic semiconductor chip is specified, which has an active zone (20) containing a multi quantum well structure provided for generating electromagnetic radiation, which comprises a plurality of successive quantum well layers (210, 220, 230). The multi quantum well structure comprises at least one first quantum well layer (210), which is n-conductively doped and which is arranged between two n-conductively doped barrier layers (250) adjoining the first quantum well layer. It comprises a second quantum well layer (220), which is undoped and is arranged between two barrier layers (250, 260) adjoining the second quantum well layer, of which one is n-conductively doped and the other is undoped. In addition, the multi quantum well structure comprises at least one third quantum well layer (230), which is undoped and which is arranged between two undoped barrier layers (260) adjoining the third quantum well layer.

Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.

Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12. By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10, and improve the crystal quality of the epitaxial layer 22. Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.

Abstract: The present power device includes a metal-made support substrate, and a group III nitride conductive layer, a group III nitride active layer and an electrode successively formed on one main surface side of the metal-made support substrate. In addition, the present method for manufacturing a power device includes the steps of preparing a conductive-layer-joined metal-made support substrate in which a group III nitride conductive layer is joined to a metal-made support substrate, forming a group III nitride active layer on the group III nitride conductive layer, and forming an electrode on the group III nitride active layer. Thus, an inexpensive power device low in on-resistance and a method for manufacturing the same can be provided.

Abstract: A method for manufacturing a group III nitride crystal includes a step of mixing a group III source material and ammonia in a reactor including quartz, and growing a group III nitride crystal on a support substrate by a vapor deposition. The group III source material is an organic metal source material containing Al. The organic metal source material is mixed with a hydrogen halide gas and the mixture of the organic metal source material and the hydrogen halide gas is supplied to the reactor.

Abstract: A method of fabricating a III-nitride power semiconductor device which includes selective prevention of the growth of III-nitride semiconductor bodies to selected areas on a substrate in order to reduce stresses and prevent cracking.

Abstract: A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.

Abstract: A method of fabricating a substrate for a semipolar III-nitride device, comprising patterning and forming one or more mesas on a surface of a semipolar III-nitride substrate or epilayer, thereby forming a patterned surface of the semipolar III-nitride substrate or epilayer including each of the mesas with a dimension/along a direction of a threading dislocation glide, wherein the threading dislocation glide results from a III-nitride layer deposited heteroepitaxially and coherently on a non-patterned surface of the substrate or epilayer.

Abstract: A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiNx) nanomask layer over a GaN template, and (b) growing a thickness of a GaN film on top of the SiNx nanomask layer.

Abstract: A method for fabricating a high quality freestanding nonpolar and semipolar nitride substrate with increased surface area, comprising stacking multiple films by growing the films one on top of each other with different and non-orthogonal growth directions.

Abstract: There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity.

Abstract: A nitride crystal or wafer with a removable surface layer comprises a high quality nitride base crystal, a release layer, and a high quality epitaxial layer. The release layer has a large optical absorption coefficient at wavelengths where the base crystal is substantially transparent and may be etched under conditions where the nitride base crystal and the high quality epitaxial layer are not. The high quality epitaxial layer may be removed from the nitride base crystal by laser liftoff or by chemical etching after deposition of at least one epitaxial device layer. The nitride crystal with a removable surface layer is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.

Abstract: The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces.

Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.

Abstract: A lateral growth method for defect reduction of semipolar nitride films. The process steps include selecting a semipolar nitride plane and composition, selecting a suitable substrate for growth of the semipolar nitride plane and composition, and applying a selective growth process in which the semipolar nitride nucleates on some areas of the substrate at the exclusion of other areas of the substrate, wherein the selective growth process includes lateral growth of nitride material by a lateral epitaxial overgrowth (LEO), sidewall lateral epitaxial overgrowth (SLEO), cantilever epitaxy or nanomasking.

Abstract: A method for forming a laser diode structure. The method includes providing a laser diode material having a surface region. A multilayer dielectric mask structure comprising alternating first and second dielectric layers is formed overlying the surface region. The method forms a laser diode structure using the multilayer dielectric mask structure as a mask. The method selectively removes a portion of the first dielectric layer to form one or more undercut regions between the second dielectric layers. A passivation layer overlies the multilayer dielectric mask structure and the undercut region remained intact. The dielectric mask structure is selectively removed, exposing a top surface region of the laser diode structure. A contact structure is formed overlying at least the exposed top surface region.

Abstract: A group III-V nitride-based semiconductor substrate includes a group III-V nitride-based semiconductor crystal. A surface area of the substrate is greater than or equal to 45 cm2. A thickness of the substrate is greater than or equal to 200 ?m. An in-plane dislocation density of the substrate is less than or equal to 2×107 cm?2 in average. The in-plane dislocation density of the substrate is less than or equal to 150% of the average at maximum.

Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

Abstract: In one aspect, the present invention provides a method of processing a substrate, e.g., a semiconductor substrate, by irradiating a surface of the substrate (or at least a portion of the surface) with a first set of polarized short laser pulses while exposing the surface to a fluid to generate a plurality of structures on the surface, e.g., within a top layer of the surface. Subsequently, the structured surface can be irradiated with another set of polarized short laser pulses having a different polarization than that of the initial set while exposing the structured surface to a fluid, e.g., the same fluid initially utilized to form the structured surface or a different fluid. In many embodiments, the second set of polarized laser pulses cause the surface structures formed by the first set to break up into smaller-sized structures, e.g., nano-sized features such as nano-sized rods.

Abstract: A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.

Abstract: An object of the present invention is to provide a Group III nitride semiconductor epitaxial substrate, a Group III nitride semiconductor element, and a Group III nitride semiconductor free-standing substrate, which have good crystallinity, with not only AlGaN, GaN, and GaInN the growth temperature of which is 1050° C. or less, but also with AlxGa1-xN having a high Al composition, the growth temperature of which is high; a Group III nitride semiconductor growth substrate used for producing these, and a method for efficiently producing those. The present invention provides a Group III nitride semiconductor growth substrate comprising a crystal growth substrate including a surface portion composed of a Group III nitride semiconductor which contains at least Al, and a scandium nitride film formed on the surface portion are provided.

Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.

Abstract: A semiconductor compound structure and a method of fabricating the semiconductor compound structure using graphene or carbon nanotubes, and a semiconductor device including the semiconductor compound structure. The semiconductor compound structure includes a substrate; a buffer layer disposed on the substrate, and formed of a material including carbons having hexagonal crystal structures; and a semiconductor compound layer grown and formed on the buffer layer.