Abstract: An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer.

Abstract: A Group-III nitride semiconductor substrate having a flat surface with a dangling bond density of higher than 14.0 nm?2 is produced by cleaning the surface having a dangling bond density of higher than 14.0 nm?2 with a cleaning agent containing an ammonium salt.

Abstract: A nitride-based semiconductor device includes a substrate, a first step portion formed on a main surface side of a first side end surface of the substrate, a second step portion formed on the main surface side of a second side end surface substantially parallel to the first side end surface on an opposite side of the first side end surface and a nitride-based semiconductor layer whose first side surface is a (000-1) plane starting from a first side wall of the first step portion and a second side surface starting from a second side wall of the second step portion on the main surface.

Abstract: An epitaxial article includes a substrate having a substrate surface having a substrate surface composition including crystalline defect or amorphous regions and crystalline non-defect regions. The crystalline defect or amorphous regions are recessed from the substrate surface by surface recess regions. A capping material fills the surface recess regions to provide capped defects that extend from a top of the defect regions to the substrate surface. The capping material is compositionally different from the substrate surface composition. An epitaxial layer over the substrate surface provides an average crystalline defect density in at least one area having a size ?0.5 ?m2 that is ? two times lower than an average crystalline defect density in that area at or below the substrate surface.

Abstract: A gallium nitride-based epitaxial wafer for a nitride light-emitting device comprises a gallium nitride substrate having a primary surface, a gallium nitride-based semiconductor film provided on the primary surface, and, an active layer provided on the semiconductor film, the active layer having a quantum well structure. A normal line of the primary surface and a C-axis of the gallium nitride substrate form an off angle with each other. The off angle monotonically increases on the line that extends from one point to another point through a center point of the primary surface. The one point and the other point are on an edge of the primary surface, and indium contents of the well layer defined at n points on the line monotonically decrease in a direction from the one point to the other point. The thickness values of the well layer defined at the n points monotonically increase in the direction.

Abstract: An epitaxial growth substrate includes: a surface not roughening over a surface roughness of 10 nm during a temperature-rise process by which a temperature increases until reaching a growth temperature of a nitride-based compound semiconductor layer, the growth temperature being 900° C. to 1050° C., wherein the nitride-based compound semiconductor layer is epitaxially grown directly on the epitaxial growth substrate at the growth temperature.

Abstract: Affords III-nitride crystals having a major surface whose variance in crystallographic plane orientation with respect to an {hkil} plane chosen exclusive of the {0001} form is minimal. A method of manufacturing the III-nitride crystal is one of: conditioning a plurality of crystal plates (10) in which the deviation in crystallographic plane orientation in any given point on the major face (10m) of the crystal plates (10), with respect to an {hkil} plane chosen exclusive of the {0001} form, is not greater than 0.5?; arranging the plurality of crystal plates (10) in a manner such that the plane-orientation deviation, with respect to the {hkil} plane, in any given point on the major-face (10m) collective surface (10a) of the plurality of crystal plates (10) will be not greater than 0.

Abstract: Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described.

Abstract: A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

Abstract: A nanodevice including a nanorod and a method for manufacturing the same is provided. The nanodevice according to an embodiment of the present invention includes i) a substrate; ii) at least one crystal that is located on the substrate and includes a plurality of side surfaces forming an angle with each other; and iii) at least one nanorod that is located on the crystal and extends along a direction that is substantially perpendicular to a surface of the substrate.

Abstract: A nitride semiconductor includes: a substrate having a major surface including a first crystal polarity surface and a second crystal polarity surface different from the first crystal polarity surface; and a single polarity layer provided above the major surface and having a single crystal polarity.

Abstract: An electronic device having a plurality of electronic components placed on a substrate, each component being constituted by a portion of a layer of active material joined mechanically to the substrate by an electrically conductive joining element pertinent to it, the layer of active material having at least one trench delimiting, at least in part, groups of electronic components each having at least two components and forming successive strips, two successive strips having a common boundary.

Abstract: To provide a nitride semiconductor crystal, comprising: laminated homogeneous nitride semiconductor layers, with a thickness of 2 mm or more, wherein the laminated homogeneous nitride semiconductor layers are constituted so that a nitride semiconductor layer with low dopant concentration and a nitride semiconductor layer with high dopant concentration are alternately laminated by two cycles or more.

Abstract: Affords methods of manufacturing InP substrates, methods of manufacturing epitaxial wafers, InP substrates, and eptiaxial wafers whereby deterioration of the electrical characteristics can be kept under control, and at the same time, deterioration of the PL characteristics can be kept under control. An InP substrate manufacturing method of the present invention is provided with the following steps. An InP substrate is prepared (Steps S1 through S3). The InP substrate is washed with sulfuric acid/hydrogen peroxide (Step S5). After the step of washing with sulfuric acid/hydrogen peroxide (Step S5), the InP substrate is washed with phosphoric acid (Step S6).

Abstract: A virtual substrate includes a handle support and a strain-relieved single crystalline layer on the handle support. A method of making the virtual substrate includes growing a coherently-strained single crystalline layer on an initial growth substrate, removing the initial growth substrate to relieve the strain on the single crystalline layer, and applying the strain-relieved single crystalline layer on a handle support.

Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.

Abstract: A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAs devices, the copper contact layer is isolated from the GaAs substrate using a barrier layer. The barrier layer may be, for example, a layer of nickel vanadium (NiV). This nickel vanadium (NiV) barrier protects the gallium arsenide substrate from the diffusion effects of the copper contact layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. In some cases, a gold or copper seed layer may be deposited on the GaAs substrate prior to depositing the copper contact layer.

Abstract: A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer is formed of a cubic crystal stoichiometrically containing silicon copiously and the surface thereof has a (3×3) reconstruction structure.

Abstract: Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 ?mol/cm2 of one or more organometallic compounds containing Al, in a flow of less than 5 ?mol/min. The preferred embodiments are equally related to the semiconductor structure obtained by the method, and to a device comprising said structure.

Abstract: There is provided a semiconductor wafer having a base wafer, an insulating layer, and a SixGe1-x crystal layer (0?x<1) in the stated order. Here, at least a partial region of the SixGe1-x crystal layer (0?x<1) has been subjected to annealing, and the semiconductor wafer comprises a compound semiconductor that has a lattice match or a pseudo lattice match with the at least partial region of the SixGe1-x crystal layer (0?x<1). Furthermore, there is provided an electronic device including a substrate, an insulating layer disposed on the substrate, a SixGe1-x crystal layer (0?x<1) disposed on the insulating layer, at least a partial region of the SixGe1-x crystal layer (0?x<1) having been subjected to annealing, a compound semiconductor that has a lattice match or a pseudo lattice match with the at least partial region of the SixGe1-x crystal layer (0?x<1), and a semiconductor device formed using the compound semiconductor.

Abstract: A Group-III nitride semiconductor substrate having a flat surface with a dangling bond density of higher than 14.0 nm?2 is produced by cleaning the surface having a dangling bond density of higher than 14.0 nm?2 with a cleaning agent containing an ammonium salt.

Abstract: A nitride semiconductor substrate has a first surface forming a principal surface of the substrate. A first edge is formed by beveling at least a portion of an edge of the first surface of the substrate. A scattering region is formed in at least a portion of the first edge. The scattering region scatters more external incident light than the first surface.

Abstract: To provide a group III nitride crystal having sufficient conductivity and capable of growing in a short time, for growing the group III nitride crystal on a base substrate by vapor deposition at a growth rate of greater than 450 ?m/hour and 2 mm/hour or less, by using a group III halogenated gas and NH3 gas, wherein Ge is doped into the group III nitride crystal by suing GeCl4 as a doping source, so that resistivity of the group III nitride crystal is 1×10?3 ?cm or more and 1×10?2 ?cm or less.

Abstract: A Group III nitride semiconductor device has a semiconductor region, a metal electrode, and a transition layer. The semiconductor region has a surface comprised of a Group III nitride crystal. The semiconductor region is doped with a p-type dopant. The surface is one of a semipolar surface and a nonpolar surface. The metal electrode is provided on the surface. The transition layer is formed between the Group III nitride crystal of the semiconductor region and the metal electrode. The transition layer is made by interdiffusion of a metal of the metal electrode and a Group III nitride of the semiconductor region.

Abstract: A method of fabricating a p-type contact on a nonpolar or semipolar (Al,Ga,In)N device, includes the steps of growing a p-type layer on an (Al,Ga,In)N device, wherein the (Al,Ga,In)N device is a nonpolar or semipolar (Al,Ga,In)N device, and the p-type layer is a nonpolar or semipolar (Al,Ga,In)N layer; and cooling the p-type layer down, in the presence of Bis(Cyclopentadienyl)Magnesium (Cp2Mg), to form a magnesium-nitride (MgxNy) layer on the p-type layer. A metal deposition is performed to fabricate a p-type contact on the p-type layer of the (Al,Ga,In)N device, after the cooling step, wherein the p-type contact has a contact resistivity lower than a p-type contact of a polar (Al,Ga,In)N device with substantially similar composition. A hydrogen chloride (HCl) pre-treatment of the p-type layer may be performed, after the cooling step and before the metal deposition step.

Abstract: A method of fabricating a vertical structure opto-electronic device includes fabricating a plurality of vertical structure opto-electronic devices on a crystal substrate, and then removing the substrate using a laser lift-off process. The method then fabricates a metal support structure in place of the substrate. In one aspects the step of fabricating a metal support structure in place of the substrate includes the step of plating the metal support structure using at least one of electroplating and electro-less plating. In one aspect, the vertical structure is a GaN-based vertical structure, the crystal substrate includes sapphire and the metal support structure includes copper. Advantages of the invention include fabricating vertical structure LEDs suitable for mass production with high reliability and high yield.

Abstract: A method of manufacturing a nitride substrate includes the following steps. Firstly, a nitride crystal is grown. Then, the nitride substrate including a front surface is cut from the nitride crystal. In the step of cutting, the nitride substrate is cut such that an off angle formed between an axis orthogonal to the front surface and an m-axis or an a-axis is greater than zero. When the nitride crystal is grown in a c-axis direction, in the step of cutting, the nitride substrate is cut from the nitride crystal along a flat plane which passes through a front surface and a rear surface of the nitride crystal and does not pass through a line segment connecting a center of a radius of curvature of the front surface with a center of a radius of curvature of the rear surface of the nitride crystal.

Abstract: Provided are a nitride thin film structure and a method of forming the same. If a nitride thin film is formed on a substrate that is not a nitride, many defects are generated by a difference in lattice constants between the substrate and the nitride thin film. Also, there is a problem of warping the substrate by a difference in thermal expansion coefficients between the substrate and the nitride thin film. In order to solve the problems, the present invention suggests a thin film structure in which after coating hollow particles, i.e. hollow structures on the substrate, the nitride thin film is grown thereon and the method of forming the thin film structure. According to the present invention, since an epitaxial lateral overgrowth (ELO) effect can be obtained by the hollow structures, high-quality nitride thin film can be formed.

Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32, which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 20.

Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.

Abstract: A Group III nitride semiconductor substrate is provided, with diameter of 25 mm or more and thickness of 250 ?m or more, wherein in at least an outer edge side part of an outer edge part within 5 mm from an outer edge of the group III nitride semiconductor substrate, stress within a main surface of the group III nitride semiconductor substrate works as a tensile stress, with the tensile stress becoming relatively greater compared to that of a center side part from the outer edge side part of the group III nitride semiconductor substrate.

Abstract: The present invention provides a method for depositing or growing a group III-nitride layer, e.g. GaN layer (5), on a substrate (1), the substrate (1) comprising at least a Ge surface (3), preferably with hexagonal symmetry. The method comprises heating the substrate (1) to a nitridation temperature between 400° C. and 940° C. while exposing the substrate (1) to a nitrogen gas flow and subsequently depositing the group III-nitride layer, e.g. GaN layer (5), onto the Ge surface (3) at a deposition temperature between 100° C. and 940° C. By a method according to embodiments of the invention, a group III-nitride layer, e.g. GaN layer (5), with good crystal quality may be obtained. The present invention furthermore provides a group III-nitride/substrate structure formed by the method according to embodiments of the present invention and a semiconductor device comprising at least one such structure.

Abstract: A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation.

Abstract: An apparatus includes a substrate, a Group III-nitride layer over the substrate, and an electrical contact over the Group III-nitride layer. The electrical contact includes a stack having multiple layers of conductive material, and at least one of the layers in the stack includes germanium. The layers in the stack may include a contact layer, where the contact layer includes aluminum copper. The stack could include a titanium or titanium alloy layer, an aluminum or aluminum alloy layer, and a germanium or germanium alloy layer. At least one of the layers in the stack could include an aluminum or titanium alloy having a germanium content between about 1% and about 5%.

Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract: A method of manufacturing a semiconductor laser having an end surface window structure includes the steps of forming a groove near at least the formation position of the end surface window structure of a substrate, and growing a nitride-based group III-V compound semiconductor layer including an active layer formed of a nitride-based group III-V compound semiconductor including at least In and Ga on the substrate.

Abstract: A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.

Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.

Abstract: Disclosed are polymer nanoparticle compositions comprising a film comprising an at least partially electrically conductive oligomer, polymer, or copolymer, and at least one nanoparticle at least partially disposed therein, wherein the at least partially electrically conductive oligomer, polymer, or copolymer is in electrical communication with the nanoparticle. Also disclosed are methods of making and using the polymer nanoparticle compositions.

Abstract: Light emitting devices include a gallium nitride-based epitaxial structure that includes an active light emitting region and a gallium nitride-based outer layer, for example gallium nitride. A indium nitride-based layer, such as indium gallium nitride, is provided directly on the outer layer. A reflective metal layer or a transparent conductive oxide layer is provided directly on the indium gallium nitride layer opposite the outer layer. The indium gallium nitride layer forms a direct ohmic contact with the outer layer. An ohmic metal layer need not be used. Related fabrication methods are also disclosed.

Abstract: An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm?2 and at most 1×106 cm?2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.

Abstract: A method of growing planar non-polar m-plane III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane Sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in the ambient of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE. Various alternative methods are disclosed.

Abstract: The present invention relates to a device (10) comprising a substrate (12) having a front surface (14) and a back surface (24); a semiconductor element (16) provided on the front surface of the substrate; a first passivation layer (18); and a second passivation layer (22) provided on the back surface of the substrate. The present invention also relates to a method of manufacturing such a device.

Abstract: The present invention provides an applications-oriented nitride compound semiconductor substrate, and devices based on it, whose lattice constant can be tuned to closely match that of any nitride thin film or films deposited on it for specific electronic or optoelectronic device applications. Such application-oriented nitride substrates, which can be composed of ternary InxGa1-xN, AlyIn1-yN, AlzGa1-zN, or quaternary AlaInbGa1-a-bN alloy compounds, minimize lattice-mismatch-induced dislocations and defects between the epitaxial films and the substrate on which the device layers are grown, leading to substantially improved device performance.

Abstract: A composite wafer comprises a single crystal substrate having first and second sides; a first III-nitride single crystal layer disposed on the first side of the substrate and being defined by a thickness; and a second III-nitride single crystal layer disposed on the second side of the single crystal substrate and being defined by a thickness. The thickness of each III-nitride single crystal layer is substantially the same. The composite wafer may be used in the manufacture of a semiconductor device or a freestanding wafer.

Abstract: A process for obtaining a hybrid substrate that includes at least one active layer of Group III/N material for applications in the field of electronics, optics, photovoltaics or optoelectronics. The method includes selecting a source substrate of Group III/N material having a hexagonal single crystal crystallographic structure; carrying out an implantation of He+ helium ions into the source substrate through an implantation face which lies in a plane approximately parallel with the “c” crystallographic axis of the material, at an implantation dose equal to or greater than 1×1016 He+/cm2 and 1×1017 He+/cm2, to form therein a number of nanocavities defining a weakened zone which delimits the active layer; and transferring the active layer by applying an overall energy budget capable of causing detachment of the layer from the source substrate, wherein the budget also causes the nanocavities to grow into cavities.

Abstract: In a method for manufacturing a semiconductor device, the method includes the step of growing a nitride-based III-V compound semiconductor layer, which forms a device structure, directly on a substrate without growing a buffer layer, the substrate being made of a material with a hexagonal crystal structure and having a principal surface that is oriented off at an angle of not less than ?0.5° and not more than 0° from an R-plane with respect to a direction of a C-axis.

Abstract: The invention concerns a method for preparing a NIII-V semiconductor. According to the invention, the method includes at least one step of doping a semiconductor of general formula AlxGa1-xN, wherein the atomic number x represents the number between 0 and 1 with a p-type electron-accepting dopant, as well as a co-doping step with a codopant capable of modifying the structure of the valency band. The invention also concerns a semiconductor as well as its use in electronics or optoelectronics. The invention further concerns a device as well as a diode using such a semiconductor.

Abstract: The present invention relates a method for forming a monocrystalline GeN layer (4) on a substrate (1) comprising at least a Ge surface (3). The method comprises, while heating the substrate (1) to a temperature between 550° C. and 940° C., exposing the substrate (1) to a nitrogen gas flow. The present invention furthermore provides a structure comprising a monocrystalline GeN layer (4) on a substrate (1). The monocrystalline GeN formed by the method according to embodiments of the invention allows passivation of surface states present at the Ge surface (3).