Abstract: A MOS bipolar transistor is provide which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer a p-type base layer. Preferably the base layer is formed by epitaxial growth and formed as a mesa. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also included are means for converting electron current flowing between the source and the drain into hole current for injection into the p-type base layer. Means for reducing field crowding associated with an insulating layer of said nMOSFET may also be provided.

Abstract: A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The transfer device includes a mesa structure having a first end, a second end opposite the first end, a top, a first side, and a second side opposite the first side. A bit-line diffusion region couples the first end of the mesa structure to a bit-line contact. A storage node diffusion region couples the second end of the mesa structure to the signal storage node. The word line controls a channel formed in the mesa structure through a gate which is formed upon the first side, the second side, and the top of the mesa structure. A sub-minimum width of the mesa structure allows full depletion to be easily achieved, resulting in volume inversion in the channel.

Abstract: To obtain a small contact-less memory device, a memory device includes a semiconductor chip having a first surface and a second surface located at a level lower than that of the first surface, a memory cell array formed on the second surface, a peripheral circuit, for operating the memory cell array, formed on the first surface, and a connecting portion, for electrically connecting the memory cell array to the peripheral circuit, formed on the first surface.

Abstract: An improved structure and method are provided for signal processing. The structure includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The body region of the dual-gated MOSFET is a fully depleted structure. The structure includes two gates which are positioned on opposite sides of the opposing sides of the body region. Further, the structure operates as one device where the threshold voltage of one gate depends on the bias of the other gate. Thus, the structure yields a small signal component in analog circuit applications which depends on the product of the signals applied to the gates, and not simply one which depends on the sum of the two signals.

Abstract: An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in first alternating trenches orthogonal to the bit lines. The buried word lines interconnect ones of the gates. Buried body lines extend in second alternating trenches orthogonal to the bit lines. The buried body lines interconnect body regions of adjacent access transistors. Unitary and split-conductor gate and body lines are provided for shared or independent signals to access transistors on either side of the trenches. In one embodiment, the memory cell has a surface area that is approximately 4 F.sup.2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Abstract: A high breakdown voltage HFET includes a reduced surface field (RESURF) layer of p-type conductivity GaN positioned on a substrate with a channel layer of n-type conductivity GaN positioned thereon. A barrier layer of n-type conductivity Al.sub.x Ga.sub.1-x N is positioned on the channel layer to form a lateral channel adjacent to and parallel with the interface. A gate electrode is positioned on the barrier layer overlying the lateral channel and a drain electrode is positioned on the channel layer in contact with the lateral channel and spaced to one side of the gate electrode a distance which determines the breakdown voltage. A source electrode is positioned on the channel layer to the opposite side of the gate electrode, in contact with the lateral channel and also in contact with the RESURF layer.

Abstract: A gallium nitride type compound semiconductor light-emitting device of the present invention includes: a substrate; a buffer layer, formed on the substrate, having a thick region and a thin region in terms of a thickness taking a surface of the substrate as a reference level; and a semiconductor layered structure, formed on the buffer layer, at least including an undoped gallium nitride type compound semiconductor layer, a gallium nitride type compound semiconductor active layer, and a P-type gallium nitride type compound semiconductor cladding layer.

Abstract: A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. An embodiment is disclosed in which a plurality of active devices are formed in the mesa region and electrically connected thereby.

Abstract: A semiconductor device includes a substrate having a first principal surface carrying thereon a first wiring pattern and a semiconductor chip having a second principal surface carrying a second wiring pattern thereon. The semiconductor chip is disposed on the substrate such that said second principal surface faces the first principal surface and a conductor is used for connecting the first wiring pattern and the second wiring pattern electrically and mechanically. The second wiring pattern includes a power conductor pattern, wherein a distance between the first principal surface and the second principal surface is increased selectively in correspondence to a part of the second principal surface on which the power conductor pattern is provided.

Abstract: A heterojunction bipolar transistor has a mesa including collector 604, base 603, and emitter 602 layers. The mesa has first and second sidewalls 606. An improved heat dissipation structure comprises a layer of electrically insulative and thermally conductive material 607 disposed on one of the sidewalls. A thermal path metal 600 is electrically connected to the emitter 602 and is disposed on the layer of electrically insulative and thermally conductive material 607. The thermal path metal 600 extends from the emitter 602 to the substrate 608 providing for efficient dissipation of heat that is generated by the HBT device.

Abstract: A micromachined insulative carrier substrate preferably formed of silicon and a multi-chip module formed from the micromachined substrate. The micromachined substrate is fabricated by forming mesas across the surface of the substrate, forming an insulating layer on the substrate, and forming conductive traces on the insulating layer to route signals between semiconductor dice and/or to external circuitry. A variety of semiconductor dice and/or integrated circuitry-bearing wafer configurations (collectively, "semiconductor elements") may be attached to the semiconductor substrate. Electrical contact between the carrier substrate and semiconductor element is achieved with conductive connectors formed on either the semiconductor element or the carrier substrate. The conductive connectors each preferably make contact with both a portion of the conductive trace extending down the sidewall of the mesa and a portion of the conductive trace on the substrate between the mesas to form a more effective bond.

Abstract: A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends out from the surface. A second substrate portion is disposed on the insulator region, and a second active region is disposed in the second substrate portion. Thus, by disposing a portion of the substrate on the isolation region, the usable substrate area is dramatically increased.

Abstract: A power distribution structure for a multichip module including, a base plate, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is formed over the exposed side surfaces of the mesas and the exposed surfaces of the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material.

Abstract: The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions.

Abstract: A semiconductor structure having: semiconductor devices formed in an inner region of a semiconductor chip; a seal ring formed in the chip and disposed about the inner region; and, a plurality of trenches formed along a surface of the chip. The trenches are disposed in a corner region of the chip. A portion of the seal ring is disposed between the trenches and the inner region of the chip. The trenches are disposed along axes oblique to outer edges of the chip. A method is provided for encapsulating a semiconductor chip. The method includes the steps of: providing a semiconductor chip having active semiconductor devices in an inner region of the semiconductor chip and a seal ring in the chip about the inner region; and, forming a plurality of trenches in the chip, a portion of the seal ring being formed between the trenches and the inner region of the chip. A cover is formed having bottom portions in the trenches and on the passivation layer.

Abstract: A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.

Abstract: A high voltage semiconductor device such as a gate turn-off thyristor, reduces surface field concentration of a main P-N junction part and attains withstand voltage increase.

Abstract: The present invention includes a gate oxide. A gate is formed on the gate oxide. Undercut portions, formed under the gate. The substrate has recessed portions are adjacent to the gate. A silicon oxynitride layer is formed on the side walls of the gate and refilled into the undercut portions to be used as a portion of the gate oxide. Side wall spacers are formed on the side walls of the gate. A polycide layer is formed at the top of the gate to reduce the electrical resistance. Source and drain regions are formed in the recessed portions of the substrate. Lightly doped drain (LDD) structures are formed in the substrate adjacent to the gate and under the gate oxide. Extended source and drain are formed between the source and drain and the LDD structure to suppress the short channel effect. Self-aligned silicide (SALICIDE) layers are formed at top of the source and drain.

Abstract: A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size. Two floating gates per pillar may be used for EEPROM or flash memory application.

Abstract: A spike electrostatic discharge (ESD) cavity structure includes an etching stop layer including, for example, polysilicon or metal material. The etching stop layer is used as the etching stop to form an opening in the dielectric layer, inside of which a number of discharging layer pairs are formed. The opening exposes the end portions of the discharge layer pairs. The opening is a cavity and can be vacuumed or filled with air.

Abstract: An optoelectronic apparatus has, a die having a mesa (103) with a surface emitting optical device and a metallized p-type contact (209), a planar pad (201) adjacent the mesa for Z-height registration with an optical bench, a first notch (206) having been provided by a first etch and having thereon a metallized n-type contact (208) that is coplanar with the p-type contact (209), a second notch having a side surface (204) having been provided by a second etch, the second notch to abut the optical bench along an x-axis, the first notch (206) extending to the second notch, and the die having side surfaces (207) to abut the optical bench along a y-axis, and the second notch extending to the side surfaces (207).

Abstract: A dummy gate is removed together with an SiO.sub.2 film thereon by lift-off to form a reverse dummy-gate pattern with the SiO.sub.2 film. A photoresist pattern is formed to cover the reverse dummy-gate pattern and an SiN protection film therebetween, and a mesa pattern is formed by mesa etching. The photoresist pattern is etched so that the edge of the photoresist pattern is located between the edge of the mesa pattern and the edge of the reverse dummy-gate pattern and the exposed part of the SiN protection film is etched. The edge of the SiN protection film is thus located inside the edge of the mesa pattern.

Abstract: Buried layers are formed within a semiconductor. Metallic or insulating buried layers are produced several microns within a semiconductor substrate. The buried layer can confine current to the buried layer itself by using a conductive material to create the buried layer. The buried layer can also confine current to a specified area of the semiconductor, by using an insulating material inside of the buried layer or by leaving a created void within the material. The buried layer is useful in the construction of a semiconductor Vertical Cavity Laser (VCL). A buried isolation layer confines the current to a narrow active region increasing efficiency of the VCL. The buried layer is also useful in fabricating discrete devices, such as diodes, transistors, and photodetectors, as well as fabricating integrated circuits.

Abstract: A method of fabricating a flash memory having a vertical floating gate terminal layer and controlling gate terminal layer structure, which is suitable for use in ultra-high density IC circuits, and which has two separate tunneling layers, one used for data programming and the other used for data erasure. The fabrication method includes a number of steps. A protruding plateau is first formed on the surface of a silicon substrate. Then, ions are implanted to form a drain region on the top surface of the protruding plateau, as well as to form source regions in the substrate on each side of and adjacent to the base of the protruding plateau. A gate oxide layer is formed on each side wall of the protruding plateau; exposing only part of the side wall of the drain region. A tunnel oxide layer that is thinner than the gate oxide layer, is formed above the surface of the silicon substrate so as to cover the source regions and drain region.

Abstract: A ridge type laser diode with a stabilized horizontal transverse mode and little variation in peak output power and a method for producing the laser. The ridge type laser diode includes a semiconductor substrate; an active layer on the semiconductor substrate, the active layer being interposed between a lower cladding layer and an upper cladding layer; and a ridge waveguide having a width, the ridge waveguide being part of the upper cladding layer so that the active layer located directly opposite the ridge waveguide is a first high refractive index region having a first refractive index; and a second high refractive index region in the central part of the first high refractive index region, having a second, higher refractive index than the first refractive index, and formed by disordering a region other than the central part and having a width less than the width of the ridge waveguide.

Abstract: A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to the mesa so that a perpendicular discontinuity is produced in the layers at the mesa sidewall and the first layer overlying the mesa is in contact with the last layer overlying the substrate adjacent the mesa. A spacer of nonconductive material is formed on the discontinuity and the plurality of overlying layers are etched, using the spacer as a mask, so as to form a contact area overlying the mesa and a contact area overlying the substrate adjacent the mesa, and a semiconductor device positioned adjacent the sidewall beneath the spacer and between the contact areas.

Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

Abstract: A method for fabricating a bipolar transistor comprising the steps of: implanting portions 320 of a semiconductor material structure with ions to render the portions semi-insulating; forming an emitter contact region 332 at an exposed surface of a base layer 308 in a non-implanted portion of the material structure; forming an epitaxial layer of semiconductor material 322 over the exposed surface in an implanted portion of the material structure; and forming a base contact 330 over said epitaxial layer. In accordance with one embodiment of the invention, the method includes the further step of forming a second epitaxial layer of semiconductor material 324 over the first epitaxial layer 322 and then forming the base contact 330 on the second epitaxial layer 324. In accordance with another embodiment, the method includes the further step of forming a second layer of epitaxial material over the exposed surface prior to forming the epitaxial layer of semiconductor material.

Abstract: The invention relates to a method of manufacturing a semiconductor device whereby an upper side of a wafer of semiconductor material (12) is provided with semiconductor elements in passivated mesa structures (2), which semiconductor elements are provided each with a connection electrode (7') in that according to the invention conductive contact bodies (3') are provided on upper sides (7) of the mesa structures (2), and an insulating material (18) is provided in spaces (17) between the contact bodies, whereupon the wafer (1) is split up into individual semiconductor bodies (10) which comprise passivated mesa structures (2) and contact bodies (3') surrounded by insulation. The contact bodies (3') have dimensions such that the semiconductor bodies (10) are suitable for surface mounting. The semiconductor devices made by the method according to the invention are resistant to comparatively high voltages between the connection electrodes (7', 4).

Abstract: A semiconductor device has a flexible structure bonded to a semiconductor substructure to form a cavity. The flexible structure is bonded over a conducting feed-through without the feed-through interfering with a hermetic seal formed by bonding. One embodiment of the device includes depressions that contain edges of a diffused feed-through so that imperfections at the edge of the diffusion do not interfere with bonding. The flexible structure is bonded to elevated areas thus hiding the imperfections. In one embodiment, a first elevated region is surrounded by a second elevated region, and diffusion for the feed-through extends from an active region in the cavity across the first elevated region with edges of the diffusion being between the first and second elevated regions. The flexible structure can thus bond to the first and second elevated regions without interference from the edge of the diffused feed-through.

Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying an epitaxial layer (12) and a semiconductor substrate (11). The semiconductor device (10) includes a doped region (13) that forms a PN junction with the epitaxial layer (12). The semiconductor device (10) also includes a dielectric layer (22) that has an opening (23) that exposes a portion of the doped region (13) and an opening (24) that exposes a portion of the epitaxial layer (12). The openings (23, 24) are filled with a conductive material (36, 37) to provide contacts (100, 101). Due to the presence of the PN junction, the contacts (100, 101) are capacitively coupled to each other.

Abstract: An integrated circuit technology combines heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs) and other components along with interconnect metallization on a single substrate. In a preferred embodiment a flat substrate is patterned, using dry etching, to provide one or more mesas in locations which will eventually support HEMTs. A device stack including HEMT and HBT layers is built up over the substrate by molecular beam epitaxy, with the active HEMT devices located on the mesas within openings in the HBT layer. In this way the active HEMT is aligned with the HBT layer to planarize the finished integrated circuit.

Abstract: The present invention is directed to a semiconductor device and method wherein a vertical opening is provided or formed completely through a semiconductor substrate of the semiconductor device to print an external electrical contact to be made to one of the semiconductor regions of the semiconductor substrate. In the disclosed embodiment an electrical contact is also provided to the bottom portion of the semiconductor substrate.

Abstract: The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd-Pt-Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.

Abstract: A field-effect transistor includes a semiconductor substrate including a source region, a drain region and a channel region located between the source and drain regions; a gate insulating film formed on at least the channel region of the semiconductor substrate; and a gate electrode formed on the gate insulating film. The surface the semiconductor substrate includes a plural of terraces having crystallographically smooth planes and at least one step located in a boundary portion of the plurality of terraces. The step extends substantially along a channel length direction.

Abstract: A non-volatile semiconductor memory device formed on a semiconductor substrate of a first conductivity type. The semiconductor memory including a plurality of recessed portions formed on a surface of the semiconductor substrate. The recessed portions having a sidewall and a bottom at which the semiconductor substrate is exposed. A gate oxide film is also directly formed on a surface of the semiconductor substrate other than the recessed portions. A floating gate electrode is formed on the gate oxide film. A source region and a drain region of a second conductivity type is formed in the semiconductor substrate at the bottom of the recessed portion and on opposing sides of the floating gate electrode. An intergate insulation film is formed on the semiconductor substrate to cover a top surface and sidewalls of the floating gate electrode, a sidewall of the recessed portion, the source region and drain region. A control gate electrode is further formed on the intergate insulation film.

Abstract: A process for manufacturing a field emission element including a substrate, and an emitter and a gate each arranged on the substrate is provided. The emitter is formed at at least a tip portion thereof with an electron discharge section, which is formed of metal or semiconductor into a monocrystalline structure or a polycrystalline structure preferentially oriented in at least a direction perpendicular to the substrate by deposition.

Abstract: A process for stripping the outer edge of a bonded BESOI wafer. The bonded BESOI wafer comprises a handle wafer, an oxide layer on one surface of the handle wafer, a device layer bonded to the oxide layer, and a p.sup.+ etch-stop layer on the device layer having an exposed face. The process comprises masking the exposed face of the p.sup.+ etch-stop layer, and abrading the periphery of the BESOI wafer to remove edge margins of the p.sup.+ etch-stop layer and device layer.

Abstract: An asymmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes first and second main planar surfaces with the second main planar surface parallel to and positioned at a height lower that the first main planar surface. A third planar surface, generally normal to the first and second main planar surfaces, connects the first and second main planar surfaces on the drain region side of the channel region. The source region is formed in a portion of the first main planar surface, and the drain region is formed in the third planar surfaces and portions of the first and second main planar surfaces. Contours of equal ion concentration in the drain region are non-Gaussian and an interface between the channel region and drain region is generally linear beneath the gate electrode adjacent the generally normal third planar surface.

Abstract: Defect density of amorphous silicon layers is increased from the lowest layer toward the highest layer by controlling one of or both of the pressure of gaseous mixture containing silane and hydrogen and the flow rate of the hydrogen, and a dry etching tapers both end portions of the amorphous silicon layers so as to improve the step coverage of a metal layer formed into source and drain electrodes.

Abstract: A semiconductor laser includes a patterned semiconductor substrate including a lower flat plane portion, an upper flat plane portion, and a stripe-shaped slant plane portion connecting the lower flat plane portion and the upper flat plane portion, an active layer formed on the semiconductor substrate, an upper cladding layer formed on the active layer, current blocking layers formed on portions of the cladding layer, the portions respectively corresponding to the lower flat plane portion to the upper flat plane portion; and a current channel region formed on a portion of the upper cladding layer corresponding to the slant plane portion. There are satisfied relations t1>t2 and tan.sup.-1 (2t1/W).ltoreq..theta.+.phi.<90.degree., where t2 is thickness of the flat plane portions of the upper cladding layer, t1 is thickness of the slant plane portion of the upper cladding layer, .theta.

Abstract: A symmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes a first region having a generally planar upper surface and a second region, projecting upwardly from the first region and having a generally planar upper surface, the second substrate region having opposed sidewalls generally normal to the upper surface of the first substrate region. A gate electrode is formed through an insulating film on the upper surface of the second substrate region, source/drain impurity regions are formed in the substrate on opposite sides of said gate electrode, and a channel region is formed under the gate electrode between the source/drain regions. Contours of equal ion concentration in the source/drain regions are non-Gaussian and an interface between the channel region and each source/drain region is generally linear beneath the gate electrode adjacent the opposing sidewalls of the second substrate region.

Abstract: The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a gate that is provided on both sides with an insulating spacer to electrically isolate it from the source and drain. The planarized tungsten layer comprises a first portion whose lower surface is in contact with a polysilicon layer of the gate. The lower surface of each of the second and third portions of the tungsten layer is in contact with the source and drain, respectively. The second and third portions are insulated from the first portion by the insulating spacers, and the upper surfaces of all the portions comprise a coplanar surface. Planarization of the deposited metal layer thus provides ohmic contact at substantially the same level to the source, drain, and gate.

Abstract: In a semiconductor device having a polycide structure located on a stepped portion, halation during formation of a resist pattern is prevented, and oxidation of an upper surface of a high-melting-point metal silicide layer is prevented during formation of an interlayer insulating film on the polycide structure. In this semiconductor device, an upper layer which is formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer is formed on the high-melting-point metal silicide layer forming the polycide structure. This effectively suppresses reflection of light beams by the upper layer located at the stepped portion during exposure for forming the resist pattern on the upper layer. Thereby, formation of a notch at the resist pattern is prevented, and the resist pattern is accurately formed to have a designed pattern.

Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A transistor encapsulated in a dielectric is formed over a substrate. First source and drain regions are formed in the substrate adjacent the transistor. Conductive raised second source and drain regions are formed which overly exposed portions of the first substrate source and drain regions adjacent the transistor. The raised second source and drain regions are formed such that an upper surface of the raised second source and drain regions are substantially planar with an upper surface of the transistor. The dielectric encapsulating the transistor electrically isolates the transistor from the raised second source and drain regions.

Abstract: A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a width of 2 to 10 micrometers. A layer of dielectric material is deposited on the substrate overlying and surrounding the mesa, to a height approximately equal to the height of the mesa and the dielectric material is etched from atop the mesa and from a surrounding area. Layers of spin on glass are deposited to fill the surrounding area and etched to achieve a planar surface including the mesa and the layer of dielectric material.

Abstract: A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high plateau on which superconductors, preferably of niobium, are applied.

Abstract: A method for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the microstructure becomes integral with the substrate 20, 70, 90, 120, 200. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then poured evenly over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.

Abstract: A semiconductor device comprises a monocrystalline silicon wafer having a major surface lying in the <100> crystal plane. Disposed on the surface is a mesa having a generally square cross-section with generally rounded corners. The mesa has four main side walls each having a slope of around 45 degrees with respect to the base plane of the mesa, and the horizontal edges of the main side walls are disposed at an angle of at least around 12 degrees to the <110> directions on the wafer surface. The corners of the mesa each comprises a number of surfaces also having slopes of around 45 degrees and one surface having a slope of around 54 degrees. A high-low (N.sup.+ N.sup.- or P.sup.+ P.sup.-) junction is disposed within the mesa and makes a continuous line intercept with the mesa side walls around the entire periphery of the mesa. Except for exceptionally small deviations of no great significance, the high low junction intercept is at a constant height location entirely around the mesa periphery.

Abstract: A hetero-junction bipolar transistor comprising a collector layer, a base layer and an emitter layer formed stepwise in this order wherein the emitter layer comprises a plurality of layers including an AlGaAs layer, and a passivation layer is formed at a stepwise portion between the base layer and the emitter layer, and of a material having a bandgap larger than that of the base layer, and provided with a phosphide layer on the surface thereof.