Combined With Passivating Coating Patents (Class 257/626)
  • Patent number: 10036675
    Abstract: The present disclosure provides a piezoelectric film sensor, a piezoelectric film sensor circuit and methods for manufacturing the same. The method for manufacturing the piezoelectric film sensor comprises: a step of forming a piezoelectric film on a substrate, and a step of subjecting the piezoelectric film to laser annealing using a laser annealing process so as to complete phase-forming transition of the piezoelectric film. Since the annealing temperature in the laser annealing process can be controlled in a range of 300° C. to 400° C., the manufacturing process can be not only applied to ensure a good performance of a piezoelectric film, but also can be used for manufacturing a flexible piezoelectric film sensor.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 31, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xueyan Tian
  • Patent number: 9941264
    Abstract: In one embodiment, an overvoltage protection device may include a semiconductor substrate comprising an n-type body region. The overvoltage protection device may further include a first p-type region disposed in a first surface region of the semiconductor substrate, and forming a first P/N junction with the n-type body region, and a second p-type region disposed in a second surface region of the semiconductor substrate opposite the first surface, and forming a second P/N junction with the n-type body region, wherein the n-type body region, first p-type region, and second p-type region form a breakdown device having a breakdown voltage greater than 100 V when an external voltage is applied between the first surface region and second surface region.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: April 10, 2018
    Assignee: Littelfuse, Inc.
    Inventors: Gary Mark Bentley, James Allan Peters, Steve Wilton Byatt
  • Patent number: 9831193
    Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: November 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ricky Alan Jackson, Erika Lynn Mazotti, Sudtida Lavangkul
  • Patent number: 9761504
    Abstract: A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chi Chuang, Kun-Ming Huang, Hsuan-Hui Hung, Ming-Yi Lin
  • Patent number: 9147757
    Abstract: There is provided a power semiconductor device, including: a first conductive type drift layer, a second conductive type termination layer formed on an upper portion of an edge of the drift layer, and a high concentration first conductive type channel stop layer formed on a side surface of the edge of the drift layer.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 29, 2015
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kee Ju Um, Dong Soo Seo, Chang Su Jang, In Hyuk Song, Jaehoon Park
  • Patent number: 9041164
    Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 26, 2015
    Assignee: IMEC
    Inventors: Roel Gronheid, Christoph Adelmann, Annelies Delabie, Gustaf Winroth
  • Patent number: 9029986
    Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Haldane S. Henry
  • Patent number: 8981536
    Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: March 17, 2015
    Assignee: Chipbond Technology Corporation
    Inventors: Chin-Tang Hsieh, You-Ming Hsu, Ming-Sheng Liu, Chih-Ping Wang
  • Patent number: 8970013
    Abstract: A semiconductor light-receiving element includes: a light-receiving portion that is provided on a semi-insulating substrate and has a mesa shape in which semiconductor layers are laminated; a lamination structure of insulating films that is provided on a part of a side face of the light-receiving portion and has a structure in which a first insulating film comprised of a silicon nitride film, a second insulating film comprised of a silicon oxynitride film and a third insulating film comprised of a silicon nitride film are laminated in contact with each other; and a resin film that is provided adjacent to the light-receiving portion, the resin film being sandwiched in or between any of the first insulating film, the second insulating film and the third insulating film.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 3, 2015
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Ryuji Yamabi, Yoshifumi Nishimoto
  • Patent number: 8896123
    Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehun Jeong, Hansoo Kim, Jaehoon Jang, Hoosung Cho, Kyoung-Hoon Kim
  • Patent number: 8884405
    Abstract: An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chi Chuang, Kun-Ming Huang, Hsuan-Hui Hung, Ming-Yi Lin
  • Patent number: 8853057
    Abstract: A method for fabricating semiconductor devices includes: (a) forming a layered structure that includes a temporary substrate, a plurality of spaced apart sacrificial film regions on the temporary substrate, and a plurality of valley-and-peak areas among the sacrificial film regions; (b) growing laterally and epitaxially an epitaxial film layer over the sacrificial film regions and the valley-and-peak areas, wherein gaps are formed among the epitaxial film layer and the valley-and-peak areas; (c) forming a conductive layer to contact the epitaxial film layer; (d) forming a plurality of grooves to divide the epitaxial film layer and the conductive layer into a plurality of epitaxial structures on the temporary substrate; and (e) removing the temporary substrate and the sacrificial film regions from the epitaxial structures by etching the sacrificial film regions through the gaps and the grooves.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 7, 2014
    Assignee: National Chung-Hsing University
    Inventors: Dong-Sing Wuu, Ray-Hua Horng
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8796824
    Abstract: A semiconductor structure having a first corner includes a carrier, a first protective layer, a second protective layer, and a third protective layer. The carrier comprises a carrier surface having a protection-layered disposing zone. The first protective layer comprises a first surface having a first disposing zone, a first anti-stress zone and a first exposing zone, the first anti-stress zone is located at a corner of the first disposing zone, the second protective layer is disposed at the first disposing zone. The second protective layer comprises a second surface having a second disposing zone, a second anti-stress zone and a second exposing zone, the second anti-stress zone is located at a corner of the second disposing zone. The first anti-stress zone and the second anti-stress zone are located at the first corner. An area of the first anti-stress zone is not smaller than that of the second anti-stress zone.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 5, 2014
    Assignee: Chipbond Technology Corporation
    Inventors: Chin-Tang Hsieh, Shyh-Jen Guo, You-Ming Hsu
  • Patent number: 8787419
    Abstract: Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: July 22, 2014
    Assignee: Binoptics Corporation
    Inventor: Alex A. Behfar
  • Patent number: 8765580
    Abstract: A method for fabricating semiconductor devices includes: (a) forming a layered structure that includes a temporary substrate, a plurality of spaced apart sacrificial film regions on the temporary substrate, and a plurality of valley-and-peak areas among the sacrificial film regions; (b) growing laterally and epitaxially an epitaxial film layer over the sacrificial film regions and the valley-and-peak areas, wherein gaps are formed among the epitaxial film layer and the valley-and-peak areas; (c) forming a conductive layer to contact the epitaxial film layer; (d) forming a plurality of grooves to divide the epitaxial film layer and the conductive layer into a plurality of epitaxial structures on the temporary substrate; and (e) removing the temporary substrate and the sacrificial film regions from the epitaxial structures by etching the sacrificial film regions through the gaps and the grooves.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 1, 2014
    Assignee: National Chung-Hsing University
    Inventors: Dong-Sing Wuu, Ray-Hua Horng
  • Patent number: 8759163
    Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow Peng, Wen-Shen Chou, Jui-Cheng Huang
  • Patent number: 8754507
    Abstract: The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and silicon wafers. Each wafer has one or more integrated circuits formed thereon. One or more through-vias are formed in each silicon wafer followed by oxide formation on at least an upper and lower surface of the silicon wafer. The wafers are aligned such that each wafer through via is aligned with a corresponding through via in adjacent stacked wafers. Wafers are bonded to form a three-dimensional wafer stack having one or more stack vias formed from the alignment of individual wafer vias. Via metallization is performed by depositing a seed layer in each of the stack vias followed by copper electroplating to form a continuous and homogeneous metallization path through the three-dimensional wafer stack.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: June 17, 2014
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Bin Xie, Pui Chung Simon Law, Yat Kit Tsui
  • Patent number: 8749029
    Abstract: The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Joachim Mahler
  • Patent number: 8692357
    Abstract: A semiconductor wafer and a method which are capable of reducing chippings or cracks generated during the die sawing process. The semiconductor wafer comprises a plurality of dies formed on the semiconductor wafer in row and column directions and separated from each other by scribe lane areas, and a passivation layer formed on the plurality of dies and the scribe lane areas, wherein a groove structure is formed in the passivation layer. The groove structure includes grooves formed along the scribe lane areas, and corners of the passivation layer at intersections of the grooves being removed.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Mnaufacturing International (Beijing) Corporation
    Inventor: Xianjie Ning
  • Patent number: 8664115
    Abstract: A passivation layer is formed on inlaid Cu for protection against oxidation and removal during subsequent removal of an overlying metal hardmask. Embodiments include treating an exposed upper surface of inlaid Cu with hydrofluoric acid and a copper complexing agent, such as benzene triazole, to form a passivation monolayer of a copper complex, etching to remove the metal hardmask, removing the passivation layer by heating to at least 300° C., and forming a barrier layer on the exposed upper surface of the inlaid Cu.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 4, 2014
    Inventors: Christin Bartsch, Susanne Leppack
  • Patent number: 8653631
    Abstract: Provided are a transferred thin film transistor and a method of manufacturing the same. The method includes: forming a source region and a drain region that extend in a first direction in a first substrate and a channel region between the source region and the drain region; forming trenches that extend in a second direction in the first substrate to define an active layer between the trenches, the second direction intersecting the first direction; separating the active layer between the trenches from the first substrate by performing an anisotropic etching process on the first substrate inside the trenches; attaching the active layer on a second substrate; and forming a gate electrode in the first direction on the channel region of the active layer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 18, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Bon Koo, Jong-Hyun Ahn, Seung Youl Kang, Hasan Musarrat, In-Kyu You, Kyoung Ik Cho
  • Patent number: 8647920
    Abstract: Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: February 11, 2014
    Assignee: IMEC VZW
    Inventors: Deniz Sabuncuoglu Tezcan, Yann Civale, Eric Beyne
  • Patent number: 8648368
    Abstract: An optoelectronic component, includes a carrier, a metallic mirror layer arranged on the carrier, a first passivation layer arranged on a region of the metallic mirror layer, a semiconductor layer that generates an active region during electrical operation arranged on the first passivation layer, a second passivation layer including two regions, wherein the first region is arranged on a top face of the semiconductor layer, and the second region which is free of the semiconductor layer is arranged on the metallic mirror layer, and wherein the first and second regions are separated from one another by a region which surrounds the first passivation layer and which is free of the second passivation layer.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: February 11, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andreas Weimar
  • Patent number: 8618638
    Abstract: A process to manufacture a semiconductor optical modulator is disclosed, in which the process easily forms a metal film including AuZn for the p-ohmic metal even a contact hole has an enhanced aspect ration. The process forms a mesa including semiconductor layers first, then, buries the mesa by a resin layer sandwiched by insulating films. The resin layer provides an opening reaching the top of the mesa, into which the p-ohmic metal is formed. Another metal film including Ti is formed on the upper insulating film along the opening.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: December 31, 2013
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Yoshihiro Yoneda, Kenji Koyama, Hirohiko Kobayashi
  • Patent number: 8592953
    Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the germanium material. A semiconductor device structure having the passivated germanium having germanium carbide material on the substrate surface is also disclosed.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: November 26, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8592955
    Abstract: The invention notably concerns a method for depositing nano-objects on a surface. The method includes: providing a substrate with surface patterns on one face thereof; providing a transfer layer on said face of the substrate; functionalizing areas on a surface of the transfer layer parallel to said face of the substrate, at locations defined with respect to said surface patterns, such as to exhibit enhanced binding interactions with nano-objects; depositing nano-objects and letting them get captured at the functionalized areas; and thinning down the transfer layer by energetic stimulation to decompose the polymer into evaporating units, until the nano-objects reach the surface of the substrate. The invention also provides a semiconductor device which includes a substrate and nano-objects accurately disposed on the substrate.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Urs T Duerig, Felix Holzner, Cyrill Kuemin, Armin W. Knoll, Philip Paul, Heiko Wolf
  • Patent number: 8580657
    Abstract: A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom no higher than a top surface of a semiconductor substrate in the wafer; forming a first insulation film over the wafer, wherein the first insulation film extends into the notch; removing a portion of the first insulation film from a center of the notch, wherein a remaining portion of the first insulation film comprises an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yian-Liang Kuo, Chien-Yi Chen, Yu-Ting Lin, Yung-Sheng Huang
  • Publication number: 20130207243
    Abstract: The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 15, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Edward Fuergut, Joachim Mahler
  • Patent number: 8482105
    Abstract: A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 9, 2013
    Assignees: Headway Technologies, Inc., Sae Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8362595
    Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the end portion of the anode electrode. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: January 29, 2013
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Akira Suzuki, Katsuyuki Seki, Keita Odajima
  • Patent number: 8354738
    Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the termanium material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the passivated germanium having germanium carbide material thereon, are also disclosed.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: January 15, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 8338911
    Abstract: In one embodiment, a semiconductor device including a substrate provided with a semiconductor element, and first and second interconnects provided above the substrate, each of the first and second interconnects having a line shape in a plan view, and the first and second interconnects being substantially parallel to each other. The device further includes a first via plug provided above the substrate, electrically connected to a lower surface of the first interconnect on a second interconnect side, and including a first recess part at an upper end of the first via plug under a first region between interconnects, the first region between interconnects being a region between the first interconnect and the second interconnect.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroko Miki, Makoto Wada, Yumi Hayashi
  • Patent number: 8299581
    Abstract: Embodiments of the invention provide a semiconductor chip having a passivation layer extending along a surface of a semiconductor substrate to an edge of the semiconductor substrate, and methods for their formation. One aspect of the invention provides a semiconductor chip comprising: a semiconductor substrate; a passivation layer including a photosensitive polyimide disposed along a surface of the semiconductor substrate and extending to at least one edge of the semiconductor substrate; and a channel extending through the passivation layer to the surface of the semiconductor substrate.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Ekta Misra, Marie-Claude Paquet, Francis Santerre, Wolfgang Sauter
  • Patent number: 8294246
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
  • Patent number: 8288843
    Abstract: A semiconductor light-emitting device includes: a first semiconductor layer having a first major surface, a second major surface which is an opposite side from the first major surface, and a side surface; a second semiconductor layer provided on the second major surface of the first semiconductor layer and including a light-emitting layer; electrodes provided on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer; an insulating layer having a first surface formed on the second major surface side of the first semiconductor layer and a second surface which is an opposite side from the first surface; an external terminal which is a conductor provided on the second surface side of the insulating layer; and a phosphor layer provided on the first major surface of the first semiconductor layer and on a portion of the first surface of the insulating layer, the portion being adjacent to the side surface of t
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 16, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki
  • Patent number: 8283754
    Abstract: A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: October 9, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsin-Hui Lee, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 8242004
    Abstract: A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A first spin-on-dielectric layer is formed over a semiconductor substrate. An abnormal oxidation of the first spin-on-dielectric layer is carried out. A surface of the first spin-on-dielectric layer is removed. A second spin-on-dielectric layer is formed over the first spin-on-dielectric layer. A non-abnormal oxidation of the first and second spin-on-dielectric layers is carried out to modify the second spin-on-dielectric layer without modifying the first spin-on-dielectric layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: August 14, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Jiro Miyahara
  • Patent number: 8236705
    Abstract: Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nitin H. Parbhoo, Spyridon Skordas
  • Patent number: 8203211
    Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: June 19, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehun Jeong, Hansoo Kim, Jaehoon Jang, Hoosung Cho, Kyoung-Hoon Kim
  • Patent number: 8203207
    Abstract: Provided are electronic device packages and their methods of formation. The electronic device packages include an electronic device mounted on a substrate, a conductive via and a locally thinned region in the substrate. The invention finds application, for example, in the electronics industry for hermetic packages containing an electronic device such as an IC, optoelectronic or MEMS device.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: June 19, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: James W. Getz, David W. Sherrer, John J. Fisher
  • Patent number: 8193591
    Abstract: Semiconductor devices (61) and methods (80-89, 100) are provided with dual passivation layers (56, 59). A semiconductor layer (34) is formed on a substrate (32) and covered by a first passivation layer (PL-1) (56). PL-1 (56) and part (341) of the semiconductor layer (34) are etched to form a device mesa (35). A second passivation layer (PL-2) (59) is formed over PL-1 (56) and exposed edges (44) of the mesa (35). Vias (90, 92, 93) are etched through PL-1 (56) and PL-2 (59) to the semiconductor layer (34) where source (40), drain (42) and gate are to be formed. Conductors (41, 43, 39) are applied in the vias (90, 92, 93) for ohmic contacts for the source-drain (40, 42) and a Schottky contact (39) for the gate. Interconnections (45, 47) over the edges (44) of the mesa (35) couple other circuit elements. PL-1 (56) avoids adverse surface states (52) near the gate and PL-2 (59) insulates edges (44) of the mesa (35) from overlying interconnections (45, 47) to avoid leakage currents (46).
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: June 5, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Haldane S. Henry
  • Patent number: 8193015
    Abstract: A method for forming a light-emitting-diode (LED) array is disclosed includes forming an LED structure on a substrate. The LED structure is divided into at least a first LED device and a second LED device with a gap between the first LED device and the second LED device. At least one polymer material is deposited over the LED structure to substantially fill the gap with the at least one polymer material. Portions of the at least one polymer material are removed to expose a first electrode of the first LED device and a second electrode of the second LED device. An interconnect is formed on top of the at least one polymer material electrically connecting the first and second electrode.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 5, 2012
    Assignee: Pinecone Energies, Inc.
    Inventors: Ray-Hua Horng, Yi-An Lu, Heng Liu
  • Patent number: 8193546
    Abstract: A light-emitting-diode (LED) array includes a first LED device having a first electrode and a second LED device having a second electrode. The first and the second LED device are formed on a common substrate and are separated by a gap. At least one polymer material substantially fills the gap. An interconnect, formed on top of the at least one polymer material, electrically connects the first electrode and the second electrode.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: June 5, 2012
    Assignee: Pinecone Energies, Inc.
    Inventors: Ray-Hua Horng, Yi-An Lu, Heng Liu
  • Patent number: 8120073
    Abstract: A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Titash Rakshit, Stephen M. Cea, Jack T Kavalieros, Ravi Pillarisetty
  • Patent number: 8105925
    Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: January 31, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8084845
    Abstract: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Mark Fischer, Robert J. Hanson
  • Patent number: 8084694
    Abstract: An electrical contact device comprising a first contact assemblage having multiple contact pads disposed in a row which are allocated to different connection types, and having a second contact assemblage having multiple contact pads disposed in a row in accordance with a predetermined sequence, which are allocated to different connection types and having bonding wire connections that electrically connect at least some of the contact pads of the first contact assemblage to contact pads of the second contact assemblage.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: December 27, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Juergen Stegmaier, Markus Ledermann
  • Patent number: 8062931
    Abstract: In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: November 22, 2011
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Anne Lorenz, Joff Derluyn, Joachim John
  • Patent number: 7973388
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: July 5, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Whonchee Lee, Janos Fucsko, David H. Wells