Abstract: Via-shaped copper interconnect lines (2) buried in an interlayer insulating film (8) are connected to gate interconnect lines (1) in the lowermost layer. A copper interconnect line (6) of a shield ring (5) is buried in the interlayer insulating film (8), closer to outside than the copper interconnect lines (2). A silicon nitride film (9) is provided on the via-shaped copper interconnect lines (2), on the copper interconnect line (6) of the shield ring (5), and on the interlayer insulating film (8). Provided on the silicon nitride film (9) is a silicon oxide film (10) which holds therein a fuse line (3) for connecting different ones of copper interconnect lines (2). The silicon oxide film (10) is also provided on the upper surfaces of the fuse line (3) and the aluminum interconnect line (7). A silicon nitride film (11) is provided on the silicon oxide film (10). The silicon nitride film (11) defined over the fuse line (3) is removed, thereby creating an opening (4).

Abstract: An apparatus and method for protecting die corners in a semiconductor integrated circuit. At least one irregular seal ring having two sides can be configured, wherein the irregular seal ring is located at a corner of a die utilized in fabricating a semiconductor integrated circuit. A dummy configuration for stress relief can then be arranged, wherein the dummy configuration is located at the two sides of the at least one irregular seal ring, thereby protecting the corner of the die against thermal stress and the semiconductor integrated circuit against moisture and metallic impurities. The irregular seal ring can be configured to generally comprise a non-rectangular seal ring. The irregular seal preferably comprises an octangular seal ring.

Abstract: A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is made according to the method. The package provides improved electrical performance particularly for devices used in RF applications.

Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the semiconductor wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate and establishing an electrical connection between the bond pad and the terminal.

Abstract: A physically robust light emitting diode is disclosed that offers high-reliability in standard packaging and that will withstand high temperature and high humidity condition. The diode comprises a Group III nitride heterojunction diode with a p-type Group III nitride contract layer, an ohmic contact to the p-type contact layer, and a sputter-deposited silicon nitride composition passivation layer on the ohmic contact. A method of manufacturing a light emitting diode and an LED lamp incorporating the diode are also disclosed.

Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

Abstract: A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The invention also includes an alignment device that secures the semiconductor device perpendicularly upon a carrier substrate. The alignment device includes intermediate conductive elements which correspond to the bond pads of the semiconductor device. Upon insertion of the semiconductor device into the alignment device, the notches facilitate alignment of the bond pads with their corresponding intermediate conductive elements. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate.

Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} surface by an angle in an range of 13° to 90° inclusive.

Abstract: An abrasive for a semiconductor device comprises cerium oxide particles and coating materials. The cerium oxide particles are made principally of cerium oxide (CeO2). The coating materials cover the surface of the cerium oxide particles.

Abstract: A power semiconductor component having a mesa edge termination is described. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed in the semiconductor body and is connected to the inner zone. An edge area outside of the first zone has areas etched out. A second zone of a second conductivity type is disposed in the semiconductor body and is connected to the inner zone, and a boundary area between the second zone and the inner zone defines a pn junction. A field stop zone is adjacent the first surface in the edge area. The field stop zone is formed of the first conductivity type and is embedded in the semiconductor body, and the field stop zone is connected to the first zone and to the inner zone.

Abstract: A structure includes holes formed in a layer of tape. The holes are aligned over active areas on chips formed in a wafer. A custom vacuum chuck with a plurality of suction ports is aligned on the tape such that the suction ports contact only the tape and not the hole portions. Flats of the custom vacuum chuck are formed so that a perimeter of the flats contacts, and rests on, the tape. In addition, the flats of the custom vacuum chuck are formed so that the flats cover the entire active area on the first surface of each of the chips. Consequently, the combination of the custom vacuum chuck and the single layer of tape form a protective cavity over the active areas of the chips during singulation from the wafer.

Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.

Abstract: An exemplary implementation of the invention is a process for forming passivation protection on a semiconductor assembly by the steps of: forming a layer of oxide over patterned metal lines having sidewalls; forming a first passivation layer of silicon nitride over the layer of oxide such that the first passivation layer of silicon nitride resides along the sidewalls of metal lines and pinches off a gap between the metal lines; performing a facet etch to remove material from the edges of the first passivation layer of silicon nitride and re-deposits some of removed material across a pinch-off junction; forming a second passivation layer of silicon nitride on the first passivation layer of silicon nitride.

Abstract: A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.

Abstract: A photomask and method of patterning a photosensitive layer using a photomask, the photomask including a substrate and a film coupled to substrate. The film is etched with a phase shifted assist feature, a low aspect ratio assist feature or phase shifted low aspect primary features.

Abstract: A method used during the manufacture of a semiconductor device comprises providing a semiconductor wafer assembly, the assembly including a plurality of unsegmented semiconductor dice. A coating layer is formed over the semiconductor wafer assembly which causes the wafer to warp, for example through a surface tension exerted on the wafer assembly by the coating layer. To reduce wafer warp a series of grooves is etched or cut into the coating layer. The grooves are believed to relieve surface tension exerted on the wafer by the coating layer. An inventive structure resulting from the method is also described.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: A protective layer includes a polymerized region, which forms a cavity in an interior surface of the protective layer. The protective layer is mounted to a micromachine chip such that an active area of the micromachine chip is located within the cavity of the protective layer. The protective layer protects the active area during front-side or back-side singulation of the micromachine chip from a micromachine substrate.

Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.

Abstract: Moisture seal apparatus and methodologies are disclosed for protecting semiconductor devices from moisture. An upper seal layer, such as SiN is formed over an upper insulator layer and an exposed portion of a die seal metal structure so as to form a vertical moisture seal between electrical components in the semiconductor device and the ambient environment. A lateral seal may be formed from the die seal metal structure in an upper metal layer in the device and one or more contacts extending downward from the die seal metal to the substrate or to a lower die seal metal structure.

Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided.

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.

Abstract: A conductor layer is patterned into flat portions, for example of a fingerprint sensor that effects capacitive measurement. The conductor layer is fragmented in a lattice-like manner by cutouts so that an applied passivation layer rests on a base layer that is present beneath the conductor layer. The interlaminar shear strength of the passivation is increased in this way.

Abstract: A method and structure for reducing mechanical shear stresses induced in an IC chip by metal interconnect lines that interconnect the chip with its surrounding substrate. A dielectric layer overlies at least a portion of the substrate and a peripheral surface region of the chip. The lines are formed on the dielectric layer and are electrically interconnected with contact pads on the peripheral surface region of the chip, i.e., beneath the dielectric layer. At least one trench is formed in the dielectric layer and surrounds the peripheral surface region of the chip. The lines traverse the trench so as to have nonplanar portions within the trench. The trenches and the nonplanar portions of the lines increase the expansion/contraction capability of the dielectric layer and lines in a region sufficiently close to where the lines are interconnected to the contact pads, such that shear stresses at critical points near the line-pad connections are significantly reduced.

Abstract: Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.

Abstract: A polyamic ester prepared by partially substituting hydrogen atoms of carboxylic groups of a polyamic acid with acid-dissociable groups, the polyamic ester comprising one or more repeating units represented by Formula 1, and each of at least one terminal of the polyamic ester molecule terminates with the same or different reactive end-capping monomer: 1

Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the semiconductor wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate, and establishing an electrical connection between the bond pad and the terminal.

Abstract: A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include silicon nitride, prevents hydrogen species from escaping therethrough as high temperature processes are subsequently conducted. Once high temperature processes have been completed, portions of the encapsulant layer may be removed, as needed, to provide access to features of the semiconductor device structure that underlie the encapsulant layer. Semiconductor device structures that have been passivated in such a manner are also disclosed.

Abstract: A plurality of metal interconnects are formed on a lower interlayer insulating film provided on a semiconductor substrate. An upper interlayer insulating film is formed so as to cover the plural metal interconnects. The upper interlayer insulating film has an air gap between the plural metal interconnects, and a top portion of the air gap is positioned at a level higher than the plural metal interconnects.

Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer.

Abstract: A semiconductor device comprises a semiconductor substrate having an area in which a circuit element is formed, and a passivation film formed on an upper surface of the semiconductor substrate, at least part of the passivation film being uneven shaped film, an upper surface of which is formed into an uneven shape independent of a shape of a lower surface of the passivation film layer.

Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate, and establishing an electrical connection between the bond pad and the terminal.

Abstract: A wafer level package structure. The method of forming the wafer level package structure includes covering a silicon chip having a plurality of integrated circuit devices thereon with an insulation layer. Next, a plurality of bonding pads is formed on the periphery of the silicon chip above the insulation layer. The bonding pads are formed such that each bonding pad is electrically connected to the terminal of an integrated circuit device. Thereafter, a passivation layer is deposited over the insulation layer and the bonding pads, and then openings that expose a portion of the bonding pad are formed. Subsequently, a metallic layer is formed on the sidewalls and the exposed bonding pad area. The metallic layer also extends over the passivation layer in the neighborhood of the opening and towards the edge of the wafer chip. Next, a layer of packaging material is deposited over the passivation layer. Finally, a metallic bump is formed over the exposed metallic layer lying above each opening.

Abstract: A method of manufacturing a PIN (positive-intrinsic-negative) diode structure includes depositing an insulation or dielectric layer over the bottom PIN diode electrodes, prior to depositing the PIN semiconductor layers. The insulation layer results in a PIN diode structure with reduced leakage current, reduced RIE (reactive ion etching) chamber contamination, the reduction or elimination of post RIE processing, improved yields, and/or expands the potential materials that may be used for the bottom electrode. A corresponding PIN diode structure is also disclosed. The resulting PIN diode structures may be used in, for example, LCD (liquid crystal display) and solid state imager applications.

Abstract: The present invention is directed to methods of creating a cavity to contain an interconnect leading to a location within a substrate. The substrate has a first dielectric layer of a first etch rate over the location, and a semiconductor device containing the interconnect. One of the methods includes the steps of: forming a second dielectric layer on the first dielectric layer wherein the second dielectric layer has a second etch rate that is slower than the first etch rate, forming a photoresist layer on the second dielectric layer and etching into the first and second dielectric layers to form the cavity leading to the location. The second dielectric layer acts as a profile guiding layer to form a plug and runner simultaneously in a single etching step while controlling relative size of the plug and runner.

Abstract: A miniaturized contact in a semiconductor substrate is provided. The contact comprises a diffused layer formed at a surface of the substrate, an interlayer film for covering the diffused layer, a plurality of lower interconnections buried within the interlayer film, an upper interconnection disposed on the interlayer film and a contact hole passing through the interlayer film for connecting the diffused layer with the upper interconnection. The contact hole has an aperture diameter equivalent to a space interval between the lower interconnections. The contact further comprises a first buried conductor disposed only from the bottom of the contact hole to a height lower than that of the lower interconnections, a side-wall insulator disposed on a side-wall of the contact hole above the first buried conductor, and a second buried conductor disposed on the first buried conductor within the contact hole.

Abstract: Disclosed is a method for fabricating an array of electromagnetic radiation responsive photodiodes, and an array fabricated in accordance with the method. The method includes steps of (a) providing a transparent substrate (12); (b) growing on the substrate an electrically conductive buffer layer (14), an n-type radiation absorbing layer (16), and a p-type cap layer (18) forming a p-n junction; and (c) etching first trenches through the cap layer, the radiation absorbing layer, and partially through the buffer layer for forming initial mesa structures each having a top surface, a base, and sloping sidewalls that terminate in the buffer layer. The method further (d) forms a passivating layer (22) on the sloping side walls; (e) forms an electrical contact (24) that surrounds the bases of the initial mesa structures and that makes an ohmic contact with a surrounding portion of the buffer layer; and (f) etches a plurality of second trenches through exposed portions of the buffer layer and into the substrate.

Abstract: An electronic device includes one or more semiconductor chips interconnected to a next level substrate in a flip chip mode using flexible conductive adhesive having a low modulus of elasticity. The flexible conductive adhesive is applied as conductive bumps on the contact pads of the substrate or on the contact pads of the semiconductor chips and is a flexible thermoplastic or thermosetting resin filled with electrically-conductive particles. Other electronic devices, such as packaged components including resistors, capacitors and the like, are bonded with the same flexible conductive adhesive bump approach as is employed for the semiconductor chips. The contact pads of both the chip and the next level substrate are preferably passivated with a metallic coating, preferably a precious metal, prior to interconnection to inhibit oxidation of the pads.

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: A method is disclosed for forming Y-shaped holes in semiconductor substrates by using Y-contact etching. The hole is formed with a single, two-step dry-etching process in a single chamber with one masking step for the whole hole. The upper portion of the Y-shaped hole is formed by means of an isotropic tapered dry-etching process while the lower portion is formed by means of a straight anisotropic recipe of the same dry-etching process. The result is a Y-shaped hole formed with fewer process steps and with maximized contact area for improved reliability.

Abstract: A method of forming an isolation region in an integrated circuit and an integrated circuit formed thereby. A method preferably includes forming at least one trench in a semiconductor substrate, forming an insulation layer of material in the at least one trench and on peripheral regions of the at least one trench of the semiconductor substrate, forming a sacrificial layer of material on the insulation layer having a different polishing rate than the insulation layer, and polishing the layer having the different polishing rate and portions of the insulation layer so that the sacrificial layer having the different polishing rate and portions of the insulation layer are removed, so that other portions of the insulation layer remain in the at least one trench of the substrate, and so that the upper surface of the at least one trench and the peripheral regions thereof in combination provide a substantially planar surface.

Abstract: A heterojunction bipolar transistor has a mesa including collector 604, base 603, and emitter 602 layers. The mesa has first and second sidewalls 606. An improved heat dissipation structure comprises a layer of electrically insulative and thermally conductive material 607 disposed on one of the sidewalls. A thermal path metal 600 is electrically connected to the emitter 602 and is disposed on the layer of electrically insulative and thermally conductive material 607. The thermal path metal 600 extends from the emitter 602 to the substrate 608 providing for efficient dissipation of heat that is generated by the HBT device.

Abstract: A semiconductor structure having: semiconductor devices formed in an inner region of a semiconductor chip; a seal ring formed in the chip and disposed about the inner region; and, a plurality of trenches formed along a surface of the chip. The trenches are disposed in a corner region of the chip. A portion of the seal ring is disposed between the trenches and the inner region of the chip. The trenches are disposed along axes oblique to outer edges of the chip. A method is provided for encapsulating a semiconductor chip. The method includes the steps of: providing a semiconductor chip having active semiconductor devices in an inner region of the semiconductor chip and a seal ring in the chip about the inner region; and, forming a plurality of trenches in the chip, a portion of the seal ring being formed between the trenches and the inner region of the chip. A cover is formed having bottom portions in the trenches and on the passivation layer.

Abstract: A semiconductor memory device with a capacitor-over-bitline (COB) structure and a method for fabricating the same. The semiconductor memory device includes a transistor having a gate electrode formed on a gate insulating layer on a semiconductor substrate and having source and drain regions formed on the surface of the substrate and separated from each other by the gate electrode, a first interlayer insulating layer formed over the substrate including the transistor; a bitline formed over the first interlayer insulating layer; and a second interlayer insulating layer formed over the substrate including the bitline, for insulating the bitline from a storage node of a capacitor. A surface of the second interlayer insulating layer is planarized by a chemical-mechanical polishing (CMP) process so as to be substantially parallel to a surface of the substrate including the bitline.

Abstract: A dummy gate is removed together with an SiO.sub.2 film thereon by lift-off to form a reverse dummy-gate pattern with the SiO.sub.2 film. A photoresist pattern is formed to cover the reverse dummy-gate pattern and an SiN protection film therebetween, and a mesa pattern is formed by mesa etching. The photoresist pattern is etched so that the edge of the photoresist pattern is located between the edge of the mesa pattern and the edge of the reverse dummy-gate pattern and the exposed part of the SiN protection film is etched. The edge of the SiN protection film is thus located inside the edge of the mesa pattern.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

Abstract: A semiconductor device in accordance with the present invention has a passivation film. The passivation film is provided on the entire surface of a substrate provided with a bonding pad and a scribe line. After applying a photoresist on the entire surface of the passivation film, a photoresist pattern is contoured. The photoresist pattern thus contoured is exposed and developed so as to be patterned. The photoresist is patterned so as to (1) provide an opening which is a connected region of a region to be the bonding pad and a region to be the scribe line, and (2) make angles of the patterning obtuse angles. Then, the passivation film is etched, and the photoresist is removed. With this arrangement, a removing solution and a resist residue do not remain in the opening section provided on a portion of the passivation film corresponding to the bonding pad, thereby preventing a quality deterioration such as corrosion of the bonding pad and breakage of wire bonding.

Abstract: A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a width of 2 to 10 micrometers. A layer of dielectric material is deposited on the substrate overlying and surrounding the mesa, to a height approximately equal to the height of the mesa and the dielectric material is etched from atop the mesa and from a surrounding area. Layers of spin on glass are deposited to fill the surrounding area and etched to achieve a planar surface including the mesa and the layer of dielectric material.

Abstract: To enhance an electric characteristic of a capacitor by decreasing a leak current, and by eliminating a recess formed in the middle of a lower electrode. In order to cover a transistor, a first interlayer insulating film (10), and a second interlayer insulating film (11) as a stopper member of a CMP method thereon are sequentially formed, a contact hole (12) is formed, and the contact hole (12) is filled in by forming a polysilicon film. Polishing the polysilicon film by the CMP method, the second interlayer insulating film (11) is formed in a thickness of 30 to 100 nm. As a result, a polysilicon plug (14) with a flat upper surface free from recess is formed, and lower electrodes (15, 16) formed thereon are also films of uniform thickness without recess, so that recess is not formed either in the middle of a ferrodielectric film (21).

Abstract: A pin type light-receiving device according to the present invention comprises (a) a semiconductor substrate, (b) a first semiconductor layer formed on a semiconductor substrate and doped with an impurity of a first conduction type, (c) a second semiconductor layer formed in a mesa shape on the first semiconductor layer and made of a first semiconductor material without intentionally doping the first semiconductor material with an impurity, (d) a third semiconductor layer formed in a mesa shape on the second semiconductor layer and made of the first semiconductor material doped with an impurity of a second conduction type different from the first conduction type, (e) a first electrode layer formed in ohmic contact on the first semiconductor layer, (f) a second electrode layer formed in ohmic contact on the third semiconductor layer, and (g) a fourth semiconductor layer formed around the first to the third semiconductor layers and made of a second semiconductor material having a band gap energy greater than th