Combined With Passivating Coating Patents (Class 257/626)
  • Patent number: 5521422
    Abstract: A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: May 28, 1996
    Assignee: International Business Machines Corporation
    Inventors: Jack A. Mandelman, Brian J. Machesney, Hing Wong, Michael D. Armacost, Pai-Hung Pan
  • Patent number: 5506421
    Abstract: The power metal oxide semiconductor field effect transistor (MOSFET) has a drain region, a channel region, and a source region formed of silicon carbide. The drain region has a substrate of silicon carbide of a first conductivity type and a drain-drift region of silicon carbide adjacent the substrate having the same conductivity type. The channel region is adjacent the drain-drift region and has the opposite conductivity type from the drain-drift region. The source region is adjacent the channel region and has the same conductivity type as the drain-drift region. The MOSFET also has a gate region having a gate electrode formed on a first portion of the source region, a first portion of the channel region, and a first portion of the drain region. A source electrode is formed on a second portion of the source region and a second portion of the channel region. Also, a drain electrode is formed on a second portion of the drain region.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: April 9, 1996
    Assignee: Cree Research, Inc.
    Inventor: John W. Palmour
  • Patent number: 5463245
    Abstract: A semiconductor integrated circuit device of this invention includes a semiconductor substrate having an active region arranged in a main surface area and an inactive region arranged in a peripheral portion of the main surface area. A semiconductor integrated circuit is formed in the active region in the main surface area of the semiconductor substrate. A connection electrode is formed on the inactive region. One end of a lead is connected to the connection electrode and the other end thereof is arranged to extend to the exterior of the semiconductor substrate. The semiconductor integrated circuit and the connection electrode are electrically connected to each other via an impurity diffusion region. At least the active region of the semiconductor substrate, the connection electrode, part of the lead arranged on the main surface of the semiconductor substrate, and the impurity diffusion region are covered with a sealing body having a sealing substrate.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: October 31, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoichi Hiruta
  • Patent number: 5438018
    Abstract: A selective growth mask having a plurality of openings is formed on a semiconductor substrate. Desired epitaxially grown regions are formed on the openings by controlling the upward epitaxial growth from the openings. Two resonance tunnel barrier diodes are formed on respective separated two epitaxially grown regions and connected together. Thereafter, a tunnel barrier diode is formed on the connected two resonance tunnel barrier diodes to form a composite element having an SRAM function. A number of composite functional elements can be integrally formed on a semiconductor substrate by selective growth and a small number of fine processes.
    Type: Grant
    Filed: December 7, 1993
    Date of Patent: August 1, 1995
    Assignee: Fujitsu Limited
    Inventors: Toshihiko Mori, Yoshiki Sakuma
  • Patent number: 5432366
    Abstract: A MOSFET device for ULSI circuits includes a semiconductor body having first and second spaced doped regions of a first conductivity type which function as source and drain regions, a third doped region between the first and second regions of a second conductivity type, and a first intrinsic region between the third doped region and the drain region, a channel of said MOSFET device including the third doped region and said first intrinsic region. Preferably the device further includes a second intrinsic region between the third doped region and the source region, the channel region of the MOSFET device including the third doped region, the first intrinsic region, and the second intrinsic region. The device further includes an insulating layer over the channel region and a gate electrode formed on the insulating layer over the channel region. A source electrode contact, the first doped region, and a drain electrode contact the second doped region. Several processes are described for fabricating the device.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: July 11, 1995
    Assignee: Board of Regents of the University of Texas System
    Inventors: Sanjay K. Banerjee, Suryanarayana Bhattacharya, William T. Lynch
  • Patent number: 5420418
    Abstract: This invention relates to a light detecting device comprising a first conduction-type semiconductor substrate, a first conduction-type semiconductor crystal layer formed on the surface of the substrate, and a second conduction-type first region formed in the semiconductor crystal layer. The first region is surrounded by a second conduction-type second region. On the surface of the semiconductor crystal layer, an electrode is formed on the first region, and a reflection preventing layer is formed on that part of the first region inside the electrode, and a device protecting film is formed on that part of the first region outside the electrode. On the semiconductor crystal layer, a metal film is formed in contact both with the semiconductor crystal layer and with the second region. This structure enables the second region to capture unnecessary charges and further to recombine and extinguish them.
    Type: Grant
    Filed: May 6, 1994
    Date of Patent: May 30, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yasushi Fujimura, Ichiro Tonai
  • Patent number: 5343070
    Abstract: A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.
    Type: Grant
    Filed: August 2, 1993
    Date of Patent: August 30, 1994
    Assignee: M/A-COM, Inc.
    Inventors: Joel L. Goodrich, Christopher C. Souchuns
  • Patent number: 5313092
    Abstract: A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.
    Type: Grant
    Filed: March 3, 1992
    Date of Patent: May 17, 1994
    Assignee: Nippon Soken, Inc.
    Inventors: Kazuhiro Tsuruta, Mitutaka Katada, Seiji Fujino, Masami Yamaoka
  • Patent number: 5281847
    Abstract: A semiconductor structure comprises a gate-turn-off thyristor region (GR) and a diode region (DR) with an isolation area (SR) therebetween. The isolation area is provided with a multistage groove (30) having step structures (34,35). The multistage groove is formed through a two-stage etching process, and over-etched regions in the bottom corners of the multistage groove are relatively shallow ones. This structure is effective for increasing the breakdown voltage of the semiconductor structure and isolations between a the gate-turnoff thyristor region and the diode region.
    Type: Grant
    Filed: January 25, 1993
    Date of Patent: January 25, 1994
    Assignee: Mitsubishi Denki Kabushik Kaisha
    Inventor: Futoshi Tokunoh
  • Patent number: 5233219
    Abstract: A semiconductor device and a method of manufacture thereof by which circuit elements are readily formed as a three-dimensional structure without increasing the device size are provided. An N.sup.31 type epitaxially grown layer (4) is first formed on a P.sup.30 type silicon substrate (2), and then a P.sup.30 type diffusion layer (31), an emitter layer (32) (P.sup.30 type) and an N.sup.30 type diffusion layer (33) are formed in the N.sup.31 type epitaxially grown layer (4). Next, an underside of the substrate (2) is etched to form a bottom recessed part (6), from which a collector region (8) (P.sup.+ type) is formed in such a manner that it reaches the P.sup.+ type diffusion layer (31). Thus, a vertical PNP type transistor is obtained readily. In this method, the collector region (8) is formed at a latter step, so that redistribution of the collector region (8) due to epitaxial growth can be avoided.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: August 3, 1993
    Assignee: Rohm Co., Ltd.
    Inventors: Noriyuki Shimoji, Hidemi Takasu
  • Patent number: 5166769
    Abstract: A process for forming a semiconductor device begins by diffusing an N layer having a relatively high concentration into a P wafer having a relatively low concentration. Next, the wafer is etched to yield a plurality of mesa semiconductor structures, each having a P-N junction intersecting a sidewall of the mesa structure. Then, a layer of oxide is grown on the sidewalls of the mesas, which oxide layer passivates the device. The oxidizing step curves the P-N junction toward the P layer in the vicinity of the oxide layer. Then, the P-N junction is diffused deeper into the P layer with a diffusion front which tends to curve the P-N junction back toward the N layer in the vicinity of the oxide layer. This diffusion is carried out to such an extent as to compensate for the curvature caused by the oxidizing step and thereby substantially flatten the P-N junction. A plurality of successive oxidation/diffusion steps can be undertaken to further flatten the junction adjacent the mesa sidewall.
    Type: Grant
    Filed: May 11, 1992
    Date of Patent: November 24, 1992
    Assignee: General Instrument Corporation
    Inventors: Willem G. Einthoven, Linda J. Down