Abstract: Thin-film transistors (TFTs) of peripheral logic circuits and TFTs of an active matrix circuit (pixel circuit) are formed on a single substrate by using a crystalline silicon film. The crystalline silicon film is obtained by introducing a catalyst element, such as nickel, for accelerating crystallization into an amorphous silicon film and heating it. In doing so, the catalyst element is introduced into regions for the peripheral logic circuits in a nonselective manner, and is selectively introduced into regions for the active matrix circuit. As a result, vertical crystal growth and lateral crystal growth are effected in the former regions and the latter regions, respectively. Particularly in the latter regions, the off-current and its variation can be reduced. The vertical growth and the lateral growth have a difference in the degree of crystal orientation.

Abstract: A ferroelectric thin film device comprises an Si substrate; a TiN thin film whose Ti component is partially replaced with Al, the TiN thin film being formed on the Si substrate; and a ferroelectric thin film of an oxide with a perovskite structure formed on the TiN thin film, wherein the amount of Al atoms present at Ti sites of the TiN thin film after partially replacing Ti with Al is within the range from about 1% to 30% and the oxygen atomic content of the TiN thin film is equal to or less than about 5%.

Abstract: A semiconductor device and method of forming a current block layer structure includes the steps of providing dielectric stripe masks defining at least a stripe-shaped opening on a surface of a compound semiconductor region having a hexagonal crystal structure, and selectively growing at least a current block layer of a compound semiconductor having the hexagonal crystal structure on the surface of the compound semiconductor region by use of the dielectric stripe masks.

Abstract: An optical integrated oxide device uses a silicon-based functional matrix substrate on which both an oxide device and a semiconductor light emitting device can be commonly integrated with an optimum structure and a high density. A single-crystal Si substrate has formed on its surface a first region where a cleaned surface of the single-crystal Si substrate itself appears, and a second region in which a CeO.sub.2 thin film is preferentially (100)-oriented or epitaxially grown on the single-crystal Si substrate. A semiconductor laser is integrated in the first region by epitaxial growth or atomic layer bonding, and an optical modulation device or optical detection device made of oxides are formed in the second region, to make up an optical integrated oxide device. A MgAl.sub.2 O.sub.4 thin film may be used instead of CeO.sub.2 thin film.

Abstract: A light emitting device employing gallium nitride type compound semiconductor which generates no crystal defect, dislocation and can be separated easily to chips by cleavage and a method for producing the same are provided. As a substrate on which gallium nitride type compound semiconductor layers are stacked, a gallium nitride type compound semiconductor substrate, a single-crystal silicon, a group II-VI compound semiconductor substrate, or a group III-IV compound semiconductur substrate is employed.

Abstract: A field effect transistor and a method for forming the field effect transistor are made up of a source region which is formed on the substrate, a drain region which is formed on the substrate, a stepped portion which is formed in the substrate between the source region and the drain region, a gate insulating film which is formed on the stepped portion of the substrate, and a gate electrode which is formed on the gate insulating film, wherein, a thickness of the gate insulating film near the drain region, which is less than that of the gate insulating film on a channel region defined in the substrate between the source region and the drain region. Accordingly, the field effect transistor and a method for forming the field effect transistor can prevent degradation of transistor characteristics because of a hot carrier effect.

Abstract: A semiconductor light emitting device includes a second semiconductor layer, an active layer, a third semiconductor layer and a pair of electrodes. The second semiconductor layer is formed directly on the principal pane of a substrate or via a first semiconductor layer. The active layer is formed on the second semiconductor layer and has an energy band gap which is smaller than the energy band gap of the second semiconductor layer. The active layer is made of a semiconductor having an uniaxial anisotropy. The third semiconductor layer is formed on the active layer and has the energy band gap which is larger than the energy band gap of the active layer. The pair of electrodes supplies current to the second semiconductor layer, the active layer, and the third semiconductor layer in the film thickness direction. The film thickness direction of at least the active layer is different from the axis of the uniaxial anisotropy.

Abstract: A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of the photoresist layer to ultraviolet light to establish a desired groove pattern in the photoresist layer. A dry etching process is then used to remove the nitride and/or oxide layers beneath the groove pattern of the photoresist layer to thereby expose portions of the substrate. Next, the wafer is disposed in a wet etching solution such as potassium hydroxide to form grooves in the exposed portions of the silicon substrate. The wafer is oriented and disposed in the bath as appropriate for forming V-shaped grooves, such that after etching, the angled walls of the grooves can be easily exposed to a dopant beam directly above the wafer, without having to tilt the wafer or beam source. Thereby, the walls of the grooves are easily implanted with dopant.

Abstract: A semiconductor device having high carrier mobility, which comprises a substrate provided thereon a base film and further thereon a crystalline non-single crystal silicon film by crystal growth, wherein, the crystals are grown along the crystallographic [110] axis, and source/drain regions are provided approximately along the direction of carrier movement which coincides to the direction of crystal growth. Moreover, the electric conductivity along this direction of crystal growth is higher than any in other directions.

Abstract: A crystalline structure and a semiconductor device includes a substrate of a semiconductor-based material and a thin film of an anisotropic crystalline material epitaxially arranged upon the surface of the substrate so that the thin film couples to the underlying substrate and so that the geometries of substantially all of the unit cells of the thin film are arranged in a predisposed orientation relative to the substrate surface. The predisposition of the geometries of the unit cells of the thin film is responsible for a predisposed orientation of a directional-dependent quality, such as the dipole moment, of the unit cells. The predisposed orientation of the unit cell geometries are influenced by either a stressed or strained condition of the lattice at the interface between the thin film material and the substrate surface.

Abstract: Any oxide superconductor Josephson junction element having an oxide superconductor oriented in the c-axis direction with respect to a substrate, and a needle-like, a-axis (or b-axis) oriented oxide superconductor. Both sides of the needle-like, a-axis (or b-axis) oriented oxide superconductor are sandwiched between the c-axis oriented superconductors. The crystal boundary sections between the needle-like, a-axis (or b-axis) oriented oxide superconductor and each of the c-axis oriented superconductors form a weak link of the Josephson junction. The needle-like, a-axis (or b-axis) oriented oxide superconductor is grown such that the c-axis direction thereof is oriented in the (110) direction which is inclined at an angle of 45 degrees with respect to the (100) direction or (010) direction of the c-axis oriented superconductors.

Abstract: A semiconductor light emitting element exhibiting a characteristic of deflected luminous intensity distribution, a semiconductor light emitting device capable of making, even when the element is off the center, a luminous center close to the center, and an element scribing method having a high element separation rate without causing a crack and chipping of pellet edges. The semiconductor light emitting element involves the use of a scribed pellet 10 into which a wafer including a semiconductor layer such as a luminous layer that is stacked on a compound semiconductor substrate inclined at 5.degree. through 20.degree. to a surface (100) in a orientation [011], is subjected to an element separation process by a scribing method.

Abstract: A diffusion gauge is formed in a surface of a silicon substrate which has a plane orientation of (110). The diffusion gauge is disposed so that a main current thereof flows along a <110> direction perpendicular to a direction in which large stress biased in one direction generates in the surface of the silicon substrate due to distortion of a base for fixing the silicon substrate. Therefore, even when the large biased stress generates in the surface of the silicon substrate, because the <110> direction in which the main current of the diffusion gauge flows is perpendicular to the direction in which the biased stress generates, there is a little change in a resistance value of the diffusion gauge. As a result, a detection error caused by the distortion of the base can be reduced.

Abstract: To provide a semiconductor laminating structure in which an epitaxial growth of a GaN system material is achieved on a substrate with an excellent matching property with the substrate. The semiconductor laminating structure includes the substrate having a perovskite structure and at least one GaN system chemical compound semiconductor layer formed on the substrate, wherein a major surface of the substrate is formed of a (111) crystal surface.

Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an area 100 where nickel serving as a crystallization-promoting catalyst is introduced.

Abstract: A semiconductor device having: a support substrate having an upper surface; a HgTe layer formed on the support substrate; and a HgCdTe layer directly formed on the HgTe layer. A semiconductor device of another type having: a support substrate having an exposed upper surface tilted from the (100) plane of a single crystal with a diamond structure by a certain angle, along a direction offset by an angle larger than 0.degree. and smaller than 45.degree. from the ?011! direction in the (100) plane; a group III-V compound semiconductor layer formed on the support substrate; and a group II-VI compound semiconductor layer formed on the group III-V compound semiconductor layer.

Abstract: The present invention includes a process of growing a compound semiconductor layer locally, after applying radical particles that do not become an etchant of a compound semiconductor layer to an insulating mask so as to terminate the surface of the insulating mask in a state that the compound semiconductor layer is covered with the insulating mask, on the surface of the compound semiconductor layer exposed from the insulating mask.

Abstract: TFTs of peripheral logic circuits and TFTs of an active matrix circuit (pixel circuit) are formed on a single substrate by using a crystalline silicon film. The crystalline silicon film is obtained by introducing a catalyst element, such as nickel, for accelerating crystallization into an amorphous silicon film and heating it. In doing so, the catalyst element is introduced into regions for the peripheral logic circuits in a non-selective manner, and is selectively introduced into regions for the active matrix circuit. As a result, vertical crystal growth and lateral crystal growth are effected in the former regions and the latter regions, respectively. Particularly in the latter regions, the off-current and its variation can be reduced.

Abstract: A method of fabricating a semiconductor light emitting device includes fabricating, semiconductor light emitting devices on a large scale by forming desirable end surfaces of resonators using an etching process. The method includes the steps of forming, on a base body, semiconductor layers for constituting a plurality of semiconductor light emitting devices; grooving the semiconductor layers formed on the base body in the direction from a front surface of the semiconductor layers to the base body, to form stripe-like grooves; and forming a semiconductor film in the grooves by epitaxial growth; wherein a side surface of each of the grooves, which side surface finally forms an end surface of a resonator of each of the semiconductor light emitting devices, is a crystal plane being later in epitaxial growth rate than a bottom surface of the groove.

Abstract: In a light-emitting diode, which comprises epitaxial wafer where a gallium phosphide or a gallium phosphide arsenide mixed crystal epitaxial layer is grown on a III-V family compound single crystal substrate having zinc blende type crystal structure, the surface of said substrate has a plane tilted by 5 to 16.degree. from a (100) plane toward ?010!, ?001!, ?0-10! or ?00-1!, or a plane having crystallographically equivalent crystal plane orientation to this plane. As a result, it is possible to improve light emitting output and to ensure longer service life.

Abstract: Prevention of reduction in the production yield due to the increase in the area of a semiconductor chip permits a sophisticated-performance single-chip semiconductor device to be fabricated. This also permits a many-kind small-amount production of semiconductor devices to be implemented. After plural semiconductor chips 2 and 3 are fabricated separately, only defect-free chips of them are selected. The selected defect-free chips are connected in contact between their side walls of their densest faces of atoms of their substrates so that the surfaces 4a and 4b where elements are to be formed are located in the same plane. Thus, even when the chip area is increased, reduction of the production yield can be prevented, thereby permitting a large-area sophisticated-performance single chip semiconductor device to be fabricated.

Abstract: A semiconductor integrated circuit device including: an off-substrate having a semiconductor surface with a plurality of steps each having a height of one monolayer and extending in one direction; a wiring layer formed on the semiconductor surface of the off-substrate and made of semiconductor material, the wiring layer including a plurality of conductive stripe regions and high resistance strip regions disposed in a stripe pattern, each stripe region extending in a direction parallel with the steps, and the conductive stripe regions and the high resistance stripe regions both having lattice structures identical to those of underlying surfaces; and semiconductor elements formed on the wiring layer and electrically connected to the conductive stripe regions, the semiconductor elements including semiconductor regions with lattice structures identical to those of the conductive stripe regions.

Abstract: A semiconductor device and a method for manufacturing the same, in which a leak current generated in a pn junction formed between a silicon substrate and an epitaxial layer can be reduced. A silicon oxide film is formed on a silicon substrate having a (100) crystal plane. The silicon oxide film is patterned to form an opened portion and an inclined surface on a pattern edge of the silicon oxide film. The inclined surface forms an angle of 54.74.+-.5.degree. with the silicon substrate. An epitaxial layer is formed in the opened portion by selective epitaxial growth.

Abstract: A silicon wafer has a polycrystalline silicon film formed on one main surface. The polycrystalline silicon film has a multilayer structure composed of X layers (X is an integer equal to or greater than two) containing <220> oriented components in different proportions. The proportion of the <220> oriented component in the first polycrystalline silicon layer in contact with the silicon wafer is larger than the respective proportions of the <220> oriented components in the second to X-th polycrystalline silicon layers superposed on the first polycrystalline silicon layer. It becomes possible to provide a silicon wafer whose polycrystalline silicon film possesses high gettering capability and in which stress acting on the silicon wafer is decreased.

Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.

Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

Abstract: A semiconductor device having high carrier mobility, which comprises a substrate provided thereon a base film and further thereon a crystalline non-single crystal silicon film by crystal growth, wherein, the crystals are grown along the crystallographic ?110! axis, and source/drain regions are provided approximately along the direction of carrier movement which coincides to the direction of crystal growth. Moreover, the electric conductivity along this direction of crystal growth is higher than any in other directions.

Abstract: A plurality of transistors according to the present invention formed on a semiconductor wafer including a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors. Further, the plurality of ESD transistors include the spacer regions and impurity implant regions encroaching the spacer regions further than the impurity implant regions of the non-ESD transistors.

Abstract: A semiconductor thin film sensor device including a semiconductor body formed of silicon having a (110) plane; a depression formed by an anisotropic etch applied to a first surface of the semiconductor body, wherein the first surface is substantially parallel to the (110) plane; and a thin film insulation member having a predetermined configuration suspended over the depression, and having substantially opposing ends connected to the first surface of the semiconductor body so that the thin film insulation member is bridged across the depression. Preferably, the depth of the depression is over 200 .mu.m. In one embodiment, the predetermined configuration of the thin film insulation member is oriented substantially parallel to a <100> direction of the semiconductor body.

Abstract: A technique for manufacturing a semiconductor device includes the steps of preparing a stepped substrate made of a group III-V compound semiconductor and having a flat surface exposing a (1 0 0) plane and a slanted surface exposing an (n 1 1)B plane whrerein n is a real number of about 1.ltoreq.n, and epitaxially growing the group III-V compound semiconductor to form an epitaxial layer on the surface of the stepped substrate while doping p- and n-type impurities, selectively at the same time or, alternatively, under conditions such that the grown epitaxial layer has an n-type region on the slanted surface and a p-type region on the flat surface.

Abstract: A method for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the microstructure becomes integral with the substrate 20, 70, 90, 120, 200. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then poured evenly over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.

Abstract: A semiconductor light-emitting device comprises a semiconductor light-emitting device section of a hexagonal type; and an electrically conductive semiconductor substrate of a cubic type combined into the semiconductor light-emitting device, and having an orientation of its cleavage facet conformed to an orientation of the cleavage facet of one of semiconductor layers forming the semiconductor light-emitting device section. The substrate of the cubic type is cleaved so that the semiconductor light-emitting device section of the hexagonal type is induced to be cleaved, and that a mirror surface can be easily formed.

Abstract: A semiconductor light emitting device is prepared by the steps of forming a semiconductor layer 2 having a laminated structure containing at least a first cladding layer 6, a light emitting layer 7, and a second cladding layer 8 on a substrate 1 having {11-20} plane (plane a) as the main plane; and breaking integrally the semiconductor layer 2 and the substrate 1 under a heating condition to form a pair of facets on the above described substrate due to the plane which was cleaved in {1-102} plane (plane r) and at the same time, to form a pair of facets 3 extending along the above described pair of facets of the substrate 1 on the semiconductor layer 2.

Abstract: A compound semiconductor device includes a compound semiconductor layer having an upper major surface formed with a multi-step structure, wherein said multi-step structure includes a plurality of steps each having a step height of at least 5 atomic layers and a step width of 300 nm or more.

Abstract: A method of increasing the performance of an FET device by aligning the channel of the FET with the ?110! crystal direction of a {100} silicon wafer. The {100} silicon wafer and the image of a lithographic mask are rotated 45 cc.degree. relative to each other so that, instead of the channel being aligned parallel with the ?100! crystal direction in the conventional fabrication, the channel is aligned approximately parallel with the ?110! crystal direction. The mobility of the carriers is higher in the ?110! crystal direction thereby increasing the performance of the FET with only a minor modification in the lithographic process. The novel FET results with its channel aligned approximately parallel with the ?110! crystal direction.

Abstract: A photoelectric conversion semiconductor device is characterized in that a second conductivity type impurity region is formed in a first conductivity type semiconductor substrate, the second conductivity type impurity region having a depth of 0.1 .mu.m or less and a peak density of 1.times.10.sup.19 atoms/cm.sup.3 or more. A method of manufacturing a photoelectric conversion semiconductor device is characterized by a step of ion-injecting boron or boron fluoride with a dose amount of 1.times.10.sup.16 to 5.times.10.sup.16 atoms/cm.sup.2 into a semiconductor substrate as an impurity.

Abstract: A method of fabricating a compositional semiconductor device comprising a antum well wire or quantum dot superlattice structure, in particular a device selected from the group comprising lasers, photodiodes, resonant tunneling transistors, resonant tunneling diodes, far infrared detectors, far infrared emitters, high electron mobility transistors, solar cells, optical modulators, optically bistable devices and bipolar transistors, by epitaxial growth of the superlattice structure on a semiconductor substrate, is characterised in that the epitaxial growth is effected on a {311}, {211}, {111} or {110} substrate, and that the devices preferably have length and width dimensions less than 500 .ANG. and especially less than 300 .ANG..

Abstract: Variations in the waveform of high-frequency signals amplified by a field-effect transistor (FET) in a power amplification circuit due to changes in temperature are reduced. A FET having an n-type active layer, a source electrode, a drain electrode and a gate electrode is formed on a (1 0 0)-crystal plane of a semi-insulating GaAs substrate. The FET is protected by a passivation film. The angle .theta., formed between the longitudinal axial direction of the gate electrode and the <0 -1 -1>-direction, is set at an angle of from 0.degree. to 90.degree. corresponding to the impurity concentration of the n-type active layer, in order that the temperature coefficient of the FET threshold voltage becomes substantially equal to the temperature coefficient of the gate bias voltage applied from a power supply to the gate electrode. If the angle .theta. is set at 45.degree., then the temperature coefficient of the FET threshold voltage becomes zero.

Abstract: A static-random-access memory (SRAM) cell has been devised which contains an access transistor having a first channel region with a first surface that lies along a first crystal plane; and a trench driver transistor having a second channel region with a second surface that lies along a second crystal plane. The first and second crystal planes belong to a single family of equivalent crystal planes, for example, the {100} family of planes. Orienting the surfaces of the channel regions of the two transistors in this fashion improves the beta ratio of the driver and access transistors and thus greatly improves the cell stability. The .beta. ratio is the ratio of the transconductances of the driver and access MOSFETs, or ##EQU1## and preferably has a value of at least three. Using a trench driver transistor improves the bit cell capacitance.

Abstract: A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well.

Abstract: In an active matrix type liquid-crystal display device, in a peripheral circuit portion, there is arranged a TFT having a high mobility and capable of allowing a large amount of on-state current to flow. In a pixel portion, there is arranged a TFT having a small off-state current. These TFTs having different characteristics are constituted by using crystalline silicon film whose crystal has grown in a direction parallel with a substrate. That is, an angle formed between a crystal growing direction and a carrier moving direction are made different from each other, thereby to control a resistance imposed on the carriers when moving to determine the characteristics of the TFT. For example, when the crystal growing direction coincides with the carrier moving direction, high mobility can be given to the carriers. Further, when the crystal growing direction is arranged perpendicular to the carrier moving direction, the off-state current can be lowered.

Abstract: A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

Abstract: A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.

Abstract: A semiconductor device has a substrate composed of a semiconductor which has one of sphalerite and diamond crystal structures. The substrate has a plane orientation inclined at 0.5.degree. to 15.degree. with respect to one of {111} and {110} planes indicated by Miller indices. A first semiconductor layer is formed on the substrate. The first semiconductor layer has a sawtooth-shaped first periodic structure consisting of one of the {111} and {110} planes indicated by the Miller indices and at least one plane indicated by another index. A second semiconductor layer is formed on the first semiconductor layer. The second semiconductor layer has a second periodic structure having a phase shifted from a phase of the first periodic structure.

Abstract: A semiconductor device comprising at least two thin film transistors on a substrate having an insulating surface thereon, provided that the thin film transistors are isolated by oxidizing the outer periphery of the active layer of each of the thin film transistors to the bottom to provide an oxide insulating film.

Abstract: A method for forming an ohmic interface between unipolar (isotype) compound semiconductor wafers without a metallic interlayer and the semiconductor devices formed with these ohmic interfaces are disclosed. The ohmic interface is formed by simultaneously matching the crystallographic orientation of the wafer surfaces and the rotational alignment within the surfaces of the two wafers and then subjecting them to applied uniaxial pressure under high temperatures to form the bonded ohmic interface. Such an ohmic interface is required for the practical implementation of devices wherein electrical current is passed from one bonded wafer to another.

Abstract: A semiconductor device is provided, including a semiconductor substrate of zinc blend structure, defined by a principal surface substantially coinciding to a {111}A-oriented crystal surface; an etch pit of the shape of a triangular pyramid, formed on the principal surface of the substrate, the etch pit being defined by side walls merging at an apex of said triangular pyramid, each two of the side walls merging at a valley of the triangular pyramid; and an active part formed on the etch pit; wherein the active part includes a quantum well layer having a first bandgap and provided along the side walls of the etch pit, and a pair of barrier layers having a second, larger bandgap and provided so as to sandwich the quantum well layer.

Abstract: The semiconductor device has a semiconductor structure directly bonded onto another semiconductor structure of a different kind from the former. These two semiconductor structures are arranged in such a way that their crystal structures in a cross section perpendicular to the bonded interface of the two semiconductor structures are different from each other or that their lattice orders are not equivalent. This can be applied to direct bonding of any combination of semiconductor structures in any crystallographic orientation relation. This also allows bonding of three or more kinds of semiconductor structures.

Abstract: The absolute value of the threshold voltage of a P-channel TFT is reduced by making its channel length shorter than that of an N-channel TFT by at least 20%, to thereby approximately equalize the threshold voltage absolute values of those TFTs.

Abstract: A Hall device consists of a single-crystal semiconductor substrate of (110) orientation, an active region formed on the substrate, a pair of input current terminals for passing a predetermined current through the active region, and a pair of output voltage terminals for measuring a potential difference to be produced in a direction orthogonal to the predetermined current flowing between the input current terminals. The surface of the active region is in a (110) plane, to minimize a fluctuation in the offset output of the device due to internal stress and precisely measure a magnetic field. This device is resistive against heat caused by soldering when mounting the device on a system.