With High Resistivity (e.g., "intrinsic") Layer Between P And N Layers (e.g., Pin Diode) Patents (Class 257/656)
  • Patent number: 5616944
    Abstract: A diode is provided comprising first and second semiconductor regions. The first semiconductor region is of one conductivity type and the second is of the opposite conductivity type. A third region is provided which is either an intrinsic semiconductor region or a low concentration region. The low concentration region has an impurity concentration lower than that of the first and second semiconductor layers. The third region is arranged to separate the first and second semiconductor regions. A control electrode region is provided over the third region through an insulative film.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: April 1, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hidemasa Mizutani, Toru Koizumi
  • Patent number: 5600156
    Abstract: A diamond semiconductor device of the present invention comprises an n-type diamond layer to which an n-type dopant is doped at high concentration so that metal conduction dominates, a p-type diamond layer to which a p-type dopant is doped at high concentration so that metal conduction dominates, and a high resistance diamond layer formed between the n-type diamond layer and the p-type diamond layer. Here, the thickness and the doping concentration of the high resistance diamond layer are values at which semiconductor conduction dominates. Then, in a case that an applied voltage is forward bias, electrons are injected from the n-type region to the p-type region through the conduction band of the high resistance region, and holes are injected from the p-type region to the n-type region through the valance band of the high resistance region, so that a current flows.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: February 4, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Nishibayashi, Tadashi Tomikawa, Shin-ichi Shikata
  • Patent number: 5563425
    Abstract: An object of the present invention is to provide a photoelectrical conversion device in which recombination of carriers excited by light is prevented and the open voltage and the carrier range of positive holes are improved and to provide a generating system using the photoelectrical conversion device. The photoelectrical conversion device includes a p-layer, an i-layer, and an n-layer, wherein the photoelectrical conversion device being formed by stacking the p-layer, the i-layer and the n-layer each of which is made of non-single-crystal silicon semiconductor, the i-layer contains germanium atoms, the band gap of the i-layer is smoothly changed in a direction of the thickness of the i-layer, the minimum value of the band gap is positioned adjacent to the p-layer from the central position of the i-layer and both of a valence control agent to serve as a donor and another valence control agent to serve as an acceptor are doped into the i-layer.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: October 8, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keishi Saito, Tatsuyuki Aoike, Masafumi Sano, Mitsuyuki Niwa, Ryo Hayashi, Masahiko Tonogaki
  • Patent number: 5557131
    Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: September 17, 1996
    Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.
    Inventor: Steven Lee
  • Patent number: 5554882
    Abstract: An avalanche semiconductor switch device utilizes trigger input. The integrated trigger input is a charge carrier injector which injects charge carriers directly into the avalanche semiconductor switch device. The avalanche semiconductor switch device includes: an active, semi-insulating layer; an anode; a cathode; and an injector disposed on the anode contact. The injector serves to switch the device into a state of very high conductance when a positive bias is applied to the injector. The integrated trigger input allows low power optical sources to be used with the avalanche semiconductor switch device further back in the trigger chain. The injector may inject holes or electrons. The injector may be integrated on one side of the substrate.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: September 10, 1996
    Assignee: The Boeing Company
    Inventor: R. Aaron Falk
  • Patent number: 5550670
    Abstract: An optoelectronic semiconductor component (1) for modulating a supplied light beam is described, where the optoelectronic semiconductor component has a pin-structure (2, 3, 4). The invention provides that M semiconductor structures with carriers localized in at least one dimension (Q1-Q20; CB1-CB10) are arranged in at least two groups (G1-G10), where the semiconductor structures with carriers localized in at least one dimension belonging to one group (G1-G10), are separated by barriers (CB1-CB10), which essentially allow Starkladder transitions between the individual semiconductor structures (Q1-Q20; CB1-CB10) of each group (G1-G10), and the individual groups (G1-G10) of such coupled semiconductor structures (Q1-Q20; CB1-CB10) are separated by other barriers (B1-B11), which essentially prevent Stark-ladder transitions between the active layers (Q1-Q20) of the semiconductor structures (Q1-Q20; CB1-CB10) of a group (G1-G10) and an active layer (Q1-Q20) of another group.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: August 27, 1996
    Assignee: Alcatel N.V.
    Inventors: Erich Zielinski, Gerhard Weiser
  • Patent number: 5479043
    Abstract: Component comprising a stack of at least two associated elementary cells (1, 2) with different spectral response features, characterized in that at least one of the elementary cells is capable of being mechanically deformed. The flexibility of this cell is sufficiently high that it can adhere directly to the other cell simply by van der Waals' interaction between the two surfaces opposite the elementary cells. The interface (20) separating the two opposite surfaces can be either sufficiently thin to form a tunnel junction electrically coupling both elementary cells to one another, the opposite layers of the elementary cells then being layers of degenerated semiconductor material p.sup.+ and n.sup.+, sufficiently high to prevent any coupling between the two elementary cells, said cells then each having its own pairs of electrodes leading to separate terminals of the component.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: December 26, 1995
    Assignee: Picogiga Societe Anonyme
    Inventor: Linh T. Nuyen
  • Patent number: 5436756
    Abstract: Photocurrent suppression is achieved without deleteriously affecting modulation performance in a surface normal, electro-absorption, quantum well modulator by introducing a sufficient number of non-radiative recombination centers in the quantum well region of the modulator. The presence of the non-radiative recombination centers significantly shortens the lifetime of photogenerated carriers and, thereby, suppresses the photocurrent. Modulation performance characteristics such as contrast ratio are maintained at acceptable levels even though exciton broadening occurs in the quantum wells. The present modulator exhibits a careful balance between defect density in the quantum wells and the acceptable degree of exciton broadening necessary to preserve quantum effects.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: July 25, 1995
    Assignee: AT&T Bell Laboratories
    Inventors: Wayne H. Knox, Jason B. Stark, Benjamin Tell, Ted K. Woodward
  • Patent number: 5424565
    Abstract: A position-sensitive semiconductor detector is provided having a completely depleted primary area of a first conductivity and insulation layers on the two main surfaces as well as conductive electrodes on the insulation layers (MIS structure).
    Type: Grant
    Filed: November 4, 1993
    Date of Patent: June 13, 1995
    Assignee: Josef Kemmer
    Inventor: Josef Kemmer
  • Patent number: 5412499
    Abstract: A spatial light modulator includes a multiple quantum well (MQW) device. Unlike MQWs of the prior art, this MQW is made semi-insulating. As a result, individual picture elements can be defined entirely by the placement of electrodes in an array on a surface of the device. Them is no need to etch trenches for electrical isolation of the picture elements.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: May 2, 1995
    Assignee: AT&T Corp.
    Inventors: Tien-Heng Chiu, Alastair M. Glass, Afshin Partovi
  • Patent number: 5391910
    Abstract: A light absorbing layer, and a window layer formed thereon constitutes a first conduction-type semiconductor layer. In a part of this first conduction-type semiconductor layer there is provided a second conduction-type region extending to the light absorbing layer through the window layer. A part of the window layer around the second conduction region is selectively removed. Consequently even when light intended to enter a light detecting region is incident outside of the light detecting region, most of the carriers generated there are recombined at a surface level of the light absorbing layer before diffusing in a depletion layer. This light detecting device therefor does not substantially detect sensitivity to light incident outside the light detecting region.
    Type: Grant
    Filed: December 16, 1991
    Date of Patent: February 21, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yasushi Fujimura, Ichiro Tonai, Hiroshi Okuda
  • Patent number: 5373186
    Abstract: A semiconductor device consisting of epitaxial material is provided with at least one monoatomic layer of doping atoms, i.e. with a layer which is just one atom thick. A preferred device is a bipolar transistor in which case the Dirac-delta doped p-type layer 38 is directly between n-type collector and emitter layers (32, 33). The bipolar transistor described herein has an extremely low base width and is capable of operating at high frequencies.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: December 13, 1994
    Assignee: Max-Planck Gesellschaft zur Foerderung der Wissenschaften e.V.
    Inventors: Erdmann Schubert, Klaus Ploog, Albrecht Fischer
  • Patent number: 5360990
    Abstract: In a semiconductor P/N junction device, a porous emitter is provided which has high saturation current to limit injected charge when the device is conducting. The porous emitter includes a lightly doped region abutting a contact on the surface of the device to regulate minority carrier injection under forward bias and shield the contact from stand-off field when the device is not conducting. One or more heavily doped regions are provided in the first region to provide low contact resistance for the flow of majority carriers into the emitter.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: November 1, 1994
    Assignee: Sunpower Corporation
    Inventor: Richard M. Swanson
  • Patent number: 5350940
    Abstract: This invention relates to a process for fabricating a metal-oxide-semiconductor device and to the semiconductor device which has enhanced charge mobility due to the inclusion of a thin layer of intrinsic semiconductor which provides a "fast track" charge channel directly at the accumulated inversion layer. The particular semiconductor device described is the enhanced mobility metal-oxide-semiconductor field effect transistor EMMOSFET having the intrinsic layer from about 100 .ANG. to about 1000 .ANG. thick. The intrinsic layer provides a low resistivity channel between the source and drain of the EMMOSFET resulting in an increase in device speed and a decrease in device heat generation.
    Type: Grant
    Filed: December 6, 1991
    Date of Patent: September 27, 1994
    Assignee: Fastran, Inc.
    Inventor: Mehmet Rona
  • Patent number: 5343070
    Abstract: A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.
    Type: Grant
    Filed: August 2, 1993
    Date of Patent: August 30, 1994
    Assignee: M/A-COM, Inc.
    Inventors: Joel L. Goodrich, Christopher C. Souchuns
  • Patent number: 5329141
    Abstract: A light emitting diode of silicon carbide having a p-n junction comprising an n-type layer doped with donor impurities, a first p-type layer doped with acceptor impurities, and a second p-type layer doped with acceptor impurities and donor impurities. The first p-type layer has a thickness less than the diffusion length of electrons having flowed from the n-type layer. In this way, the first p-type layer effects light emission related to the acceptor impurities which recombine with the electrons having flowed from the n-type layer, and the second p-type layer effects light emission by donor-acceptor pairs which recombine with the electrons having flowed from the n-type layer.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: July 12, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akira Suzuki, Yoshihisa Fujii, Hajime Saito, Katsuki Furukawa, Yoshimitsu Tajima
  • Patent number: 5329150
    Abstract: A semiconductor light wave detector which has a first layer of a highly doped n-type semiconducting substrate, a second layer of a highly doped n-type semiconducting material, a third layer of a distinct intrinsic semiconducting material and a fourth layer of a highly doped n-type semiconducting material similar to the second layer. First and second electrical connections are provided to the fourth layer and to at least one of the first and second layers. A plurality of pairs of Dirac-delta doped monoatomic layers are in the third layer, with the first monoatomic layer of each pair being a layer of donors and with the second monoatomic layer of each pair being acceptors spaced from the donor layer and positioned on the side thereof facing the fourth layer.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: July 12, 1994
    Assignee: Max Planck Gesellschaft zur Foerderung der Wissenschaften e.V.
    Inventors: Erdmann Schubert, Klaus Ploog, Albrecht Fischer
  • Patent number: 5313087
    Abstract: A polysilicon layer is provided with a p-type impurity, and masked with an oxide mask to define a p-type region of the polysilicon layer. A second impurity is then provided into first unmasked regions of the polysilicon layer. A second oxide mask is deposited and anisotropically etched to form spacers adjacent to the first oxide mask. The spacers define two diffusion barrier regions of the polysilicon layer adjacent to the p-type region. An n-type impurity is then provided into second unmasked regions of the polysilicon layer to form two n-type regions adjacent the diffusion barrier regions. The diffusion barrier regions prevent cross diffusion of the p-type and the n-type impurities within the polysilicon layer, while also being of sufficient dimensions to permit normal p/n operations.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: May 17, 1994
    Assignee: Micron Technology, Inc.
    Inventors: Hiang C. Chan, Pierre C. Fazan, Bohr-Winn Shih
  • Patent number: 5306925
    Abstract: According to the present invention, there is provided a nonlinear optical element including a p-i-n type photodiode (i layer is a light absorbing layer) provided with a barrier layer preventing the going-through of a majority carrier. In the nonlinear optical element of the present invention, since the charges are accumulated with the stop of carrier moving, there occur a deformation in energy band and change in internal electric field. Optical bistability can be attained even without an external circuit. Further, with a plurality of incident light, only one element can exhibit optical bistability therefor because there is no need to dispose an external circuit. According to a method of the present invention, it is possible to control bistability for one light by overlapping another light input to a carrier diffusing region generated by the one light.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: April 26, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuji Abe, Yasunori Tokuda
  • Patent number: 5300791
    Abstract: A light emitting diode is provided with a window layer of ZnSSe semiconductor material having a second conductivity type. The second conductivity type ZnSSe window layer has a low electrical resistivity so that it can be used as a current spreading layer, and a bandgap higher than that of the active layer so that it is transparent to light emitted from the active layers. The second conductivity type ZnSSe window layer can be doped with a donor concentration of more than 10.sup.18 cm.sup.-3. Furthermore, its lattice constant is close to that of the active layers and confining layers so that deterioration in optical characteristic due to lattice mismatch is minimized.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: April 5, 1994
    Assignee: Industrial Technology Research Institute
    Inventors: Tzer-Perng Chen, Chin-Yuan Chen, Jyi-Ren Deng, Ming-Jiunn Jou, Biing-Jye Lee, Jenn-Yu Kao
  • Patent number: 5294843
    Abstract: A freewheeling diode device (10) for a commutation branch includes a first diode (12) with a soft recovery behavior and a second diode (14) with a snappy recovery behavior. The second diode (14) is connected in parallel to the first diode (12).
    Type: Grant
    Filed: October 26, 1992
    Date of Patent: March 15, 1994
    Assignee: Semikron Elektronik GmbH
    Inventors: Werner Tursky, Josef Lutz
  • Patent number: 5270556
    Abstract: A semiconductor device includes a layer on a substrate in which a two-dimensional electron gas is produced, source and drain electrodes disposed opposite each other on the substrate, and a gate electrode including a plurality of lower gate electrodes and an upper gate electrode. The lower gate electrodes are spaced at prescribed intervals in a direction perpendicular to a direction connecting the source and drain electrodes and connected to the layer only at their bottom surfaces. The upper gate electrode is disposed on the lower gate electrodes and electrically connects the lower gate electrodes to each other. When a bias voltage is applied to the gate electrode, a depletion layer spreads below the lower gate electrodes and the two-dimensional electron gas is concentrated beneath regions where the lower gate electrodes are absent, producing a quasi one-dimensional electron gas.
    Type: Grant
    Filed: July 30, 1992
    Date of Patent: December 14, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Teruyuki Shimura
  • Patent number: 5256887
    Abstract: A photovoltaic cell for use in a single junction or multijunction photovoltaic device, which includes a p-type layer of a semiconductor compound including silicon, an i-type layer of an amorphous semiconductor compound including silicon, and an n-type layer of a semiconductor compound including silicon formed on the i-type layer. The i-type layer including an undoped first sublayer formed on the p-type layer, and a boron-doped second sublayer formed on the first sublayer.
    Type: Grant
    Filed: July 19, 1991
    Date of Patent: October 26, 1993
    Assignee: Solarex Corporation
    Inventor: Liyou Yang
  • Patent number: 5243204
    Abstract: There are provided silicon carbide light emitting diodes having a p-n junction which is constituted by a p-type silicon carbide single-crystal layer and an n-type silicon carbide single-crystal layer formed thereon. In cases where light emission caused by recombination of free excitons is substantially utilized, at least a part of the n-type silicon carbide layer adjacent to the interface of the p-n junction is doped with a donor impurity at a concentration of 5.times.10.sup.16 cm.sup.-3 or lower. In cases where light emission caused by acceptor-associated recombination is substantially utilized, the p-type silicon carbide layer is doped with an acceptor impurity and at least a part of the n-type silicon carbide layer adjacent to the interface of the p-n junction is doped with a donor impurity at a concentration of 1.times.10.sup.18 cm.sup.-3 or higher. Also provided are a method for producing such silicon carbide light emitting diodes and a method for producting another silicon carbide light emitting diode.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: September 7, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akira Suzuki, Katsuki Furukawa, Yoshihisa Fujii
  • Patent number: 5237197
    Abstract: A VLSI radiation/particle detector includes detecting elements based on one or more PIN diodes which are biased for collecting the charge generated by incident radiation or ionizing particles, and readout circuitry integrated on the same chip for detecting the collected charge. The junction of the PIN diode and the well containing the readout circuitry are separated far from each other such that the bias voltage required on the well to direct most generated charge to the collection electrodes can be reduced, and these can be made smaller to improve the detector's spatial resolution.
    Type: Grant
    Filed: September 23, 1991
    Date of Patent: August 17, 1993
    Assignee: University of Hawaii
    Inventors: Walter Snoeys, Sherwood I. Parker
  • Patent number: 5225706
    Abstract: In a matrix array of photosensitive elements, each photosensitive point is provided with a photosensitive element (pin photodiode) in series with a capacitor between a row lead and a column lead. It is proposed to make use of a simplified photosensitive element in which an end semiconductor layer is suppressed such as, for example, the n-layer of a pin photodiode or the n-layer of a five-layer phototransistor of the nipin type. The dielectric of the capacitor then comes directly into contact with an intrinsic semiconductor layer in which electrons accumulate. These electrons reconstitute the equivalent of an n-type doped layer.
    Type: Grant
    Filed: February 25, 1991
    Date of Patent: July 6, 1993
    Assignee: Thomson-CSF
    Inventors: Jean L. Berger, Marc Arques
  • Patent number: 5216260
    Abstract: An optically bistable semiconductor device which has a doped or undoped gallium arsenide substrate and a series of alternating n-type and p-type Dirac-delta doped monoatomic layers formed on the substrate. Each Dirac-delta doped monoatomic layer is separated from the next adjacent Dirac-delta doped monoatomic layer by a layer of pure, undoped intrinsic semiconductor material such as gallium arsenide.
    Type: Grant
    Filed: June 27, 1991
    Date of Patent: June 1, 1993
    Assignee: Max-Planck Gesellschaft zur Foerderung der Wissenschaften e.V.
    Inventors: Erdmann Schubert, Klaus Ploog, Albrecht Fischer
  • Patent number: 5216275
    Abstract: A semiconductor power device wherein the reverse voltage across the p.sup.+ -regions(s) and the n.sup.+ -regions(s) is sustained by a composite buffer layer, shortly as CB-layer. The CB-layer contains two kinds of semiconductor regions with opposite types of conduction. These two kinds of regions are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n.sup.+ (or p.sup.+)-region. Whereas the hitherto-used voltage sustaining layer contains only one kind of semiconductor with single type of conduction in the same sectional view. Design guidelines are also provided in this invention. The relation between the on-resistance in unit area Ron and the breakdown voltage V.sub.B of the CB-layer invented is Ron ocV.sub.B.sup.113 which represents a breakthrough to the conventional voltage sustaining layer, whereas the other performances of the power devices remain almost unchanged.
    Type: Grant
    Filed: September 17, 1991
    Date of Patent: June 1, 1993
    Assignee: University of Electronic Science and Technology of China
    Inventor: Xingbi Chen
  • Patent number: 5212398
    Abstract: In an integrated circuit device including a bipolar transistor, MOSFET, and protective diode for the MOSFET, all formed over a semiconductor substrate, the protective diode for holding an adequate electrostatic breakdown voltage for a gate oxide layer of the MOSFET is provided by forming a second conductivity type buried area continuous with, and in contact with, a second conductivity type region at a boundary between the first conductivity type semiconductor substrate and a first conductivity type second semiconductor layer. By doing so, a substantive junction depth Xj is made deeper as a whole with respect to the second conductivity type region. It is, therefore, possible to obtain a protective diode of adequate electrostatic breakdown-voltage characteristic which does not adversely affect the operation of the MOSFET even if a relatively thin semiconductor layer is employed.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: May 18, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taira Matsunaga, Bunshiro Yamaki
  • Patent number: 5181083
    Abstract: A PIN diode with a low voltage peak at the switching on comprises a P-type anode region (4) formed on a first surface of a low doped N-type substrate (1) and a cathode region (2) formed on the second surface of the substrate. The PIN diode comprises on a portion of the first surface an additional N.sup.+ -type region (7) in contact with the anode region for forming a junction with the latter. The additional region is connected to the cathode region.
    Type: Grant
    Filed: July 15, 1991
    Date of Patent: January 19, 1993
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Robert Pezzani