On Insulating Carrier Other Than A Printed Circuit Board Patents (Class 257/668)
  • Patent number: 11145639
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Wei Cheng, Chien-Hsun Lee, Chi-Yang Yu, Hao-Cheng Hou, Hsin-Yu Pan, Tsung-Ding Wang
  • Patent number: 11145637
    Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yanggyoo Jung, Chulwoo Kim, Hyo-Chang Ryu, Yun Seok Choi
  • Patent number: 11121119
    Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a flexible substrate, a driving circuit, and a memory. The substrate has a first surface and a second surface opposite to each other, and the first surface has a display region and a bonding region. The display unit is disposed on the display region of the first surface. The flexible substrate is disposed below the second surface and has a connection portion extended to the bonding region of the first surface. The driving circuit is disposed on the flexible substrate and electrically connects with the display unit. The memory is disposed on the flexible substrate and electrically connects with the driving circuit.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 14, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Liang Chen, Hann-Jye Hsu
  • Patent number: 11121090
    Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changbo Lee, Joonseok Oh, Byunglyul Park
  • Patent number: 11121064
    Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Park, Da Hye Kim, Jin-Woo Park, Jae Gwon Jang
  • Patent number: 11116087
    Abstract: Disclosed are a display module and a display device. The display module includes a display panel having a light emitting surface and a back surface opposite to the light emitting surface; a drive circuit board disposed adjacent to an edge at a side of the display panel, and a wiring gap is formed between the drive circuit board and the display panel; a chip-on-film, a first connecting end of which is disposed on the light emitting surface and connected to the display panel, and a second connecting end of which passes through the wiring gap and extends to the back surface of the display panel; and an adapter structure disposed on a side of the second connecting end of the chip-on-film facing away from the display panel, connected between the chip-on-film and the drive circuit board.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: September 7, 2021
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiaoxia Huang, Shuang Zhang, Bing Ji, Chang Zhang
  • Patent number: 11107771
    Abstract: A method includes encapsulating a plurality of package components in an encapsulant, and forming a first plurality of redistribution layers over and electrically coupling to the plurality of package components. The first plurality of redistribution layers have a plurality of power/ground pad stacks, with each of the plurality of power/ground pad stacks having a pad in each of the first plurality of redistribution layers. The plurality of power/ground pad stacks include a plurality of power pad stacks, and a plurality of ground pad stacks. At least one second redistribution layer is formed over the first plurality of redistribution layers. The second redistribution layer(s) include power lines and electrical grounding lines electrically connecting to the plurality of power/ground pad stacks.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Rong Chun, Tin-Hao Kuo, Chi-Hui Lai, Kuo Lung Pan, Yu-Chia Lai, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11108028
    Abstract: A manufacturing method for an organic electronic device according to a mode includes a device substrate manufacturing step S01 of manufacturing a device substrate 12 in which a first electrode layer 18, a device function portion 20 including an organic layer, and a second electrode layer 22 are sequentially laminated in each of a plurality of device formation regions DA virtually set in a flexible support substrate 16 and having at least one corner, a bonding step S02 of bonding a sealing member 14 including a sealing base 24 and an adhesive layer 26 laminated on the sealing base to a side of the second electrode layer of the device substrate via the adhesive layer such that the sealing member is not disposed at corners c1 to c4 of the device formation region, and a dicing step S03 of dicing the device substrate, to which the sealing member is bonded, for each of the device formation regions to obtain an organic electronic device 10.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 31, 2021
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Takashi Fujii, Shinichi Morishima, Yasuo Matsumoto
  • Patent number: 11107743
    Abstract: A chip on film package includes; a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Tae Hwang, Jae-Choon Kim, Kyung-Suk Oh, Woon-Bae Kim, Jae-Min Jung
  • Patent number: 11094634
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Chung-Shi Liu, Chih-Yuan Chang, Jiun-Yi Wu, Jeng-Shien Hsieh, Tin-Hao Kuo
  • Patent number: 11088045
    Abstract: A semiconductor device includes a semiconductor module having a heat conductive portion formed of metal and also having a molded resin having a surface at which the heat conductive portion is exposed, a cooling body secured to the semiconductor module by means of bonding material, and heat conductive material formed between and thermally coupling the heat conductive portion and the cooling body.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: August 10, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noboru Miyamoto, Masao Kikuchi
  • Patent number: 11075156
    Abstract: A substrate having an electronic component embedded therein includes a core structure including a first insulating body and first wiring layers and having a cavity, an electronic component embedded in the cavity, a build-up structure including a second insulating body, covering at least a portion of each of the core structure and the electronic component and filling a portion of the cavity, and second wiring layers, a first passivation layer disposed on a side of the core structure opposing a side of the core structure on which the build-up structure is disposed, and a second passivation layer disposed on a side of the build-up structure opposing a side of the build-up structure on which the core structure is disposed, wherein the first and second passivation layers include different types of materials.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Jung Byun, Yong Duk Lee, Chang Hwa Park, Ki Ho Na, Je Sang Park, Jin Won Lee
  • Patent number: 11062982
    Abstract: A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vikas Gupta, Daniel Yong Lin
  • Patent number: 11063525
    Abstract: The present disclosure provides a power supply module and a manufacture method thereof, belonging to the technical field of power electronics. According to the present disclosure, a unibody conductive member is employed to connect a conductive part in a passive element to a conductive layer in a substrate. This is advantageous in simplifying the structure of the passive element, and enabling a structurally compact power supply module at a reduced cost. Additionally, stacking the passive element with the substrate may allow for a further compact structure for the power supply module, improving the space utilization rate for the power supply module, while enhancing the external appearance of the power supply module with tidiness, simplicity and aesthetics.
    Type: Grant
    Filed: December 29, 2019
    Date of Patent: July 13, 2021
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Pengkai Ji, Shouyu Hong, Xiaoni Xin, Le Liang, Zhenqing Zhao
  • Patent number: 11056438
    Abstract: Semiconductor packages and method of forming the same are disclosed. One of the semiconductor packages includes a first die, a second die, a through via and a dielectric encapsulation. The second die is bonded to the first die. The through via is disposed aside the second die and electrically connected to the first die. The through via includes a step-shaped sidewall. The dielectric encapsulation encapsulates the second die and the through via.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11037913
    Abstract: A semiconductor package includes a bottom package having a lower substrate and a lower semiconductor chip mounted on the lower substrate, an interposer substrate on the bottom package, a first top package and a second top package that are mounted on the interposer substrate, and a heat spreader that is interposed between the first top package and the second top package and separates the first and second top packages from each other. The heat spreader is adhered to the interposer substrate through a plurality of first connection terminals.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 15, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunhyeok Im, Kyoung-Min Lee, Kyungsoo Lee, Horang Jang
  • Patent number: 11024595
    Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Benjamin L. McClain, Brandon P. Wirz, Zhaohui Ma
  • Patent number: 11013120
    Abstract: A tape wiring board includes an insulating film on which a semiconductor chip is mounted and metal layers formed on both principal surfaces, respectively, of the insulating film. That one of the metal layers which is formed on a first surface that is one principal surface of the insulating film and on which the semiconductor chip is mounted has a first electrode that is placed near substantially the center of a region on the first surface where the semiconductor chip is mounted.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 18, 2021
    Assignee: SHENZHEN TOREY MICROELECTRONIC TECHNOLOGY CO. LTD.
    Inventor: Nobuaki Asayama
  • Patent number: 11011389
    Abstract: A semiconductor device assembly and method of providing a semiconductor device assembly. The method includes providing a flexible interposer, providing a first redistribution layer on the flexible interposer, and providing a second redistribution layer on a portion of the first redistribution layer. The second redistribution layer is provided by additive manufacturing. The first redistribution layer may be deposited in a clean room environment. The first redistribution layer may be deposited via chemical deposition or physical deposition. A semiconductor device is attached to the first redistribution layer. The flexible interposer may be attached to a board with the semiconductor device being electrically connected to the board via the first redistribution layer, the flexible interposer, and the second redistribution layer. The flexible interposer may be attached to a flexible hybrid electronic (FHE) board.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 18, 2021
    Assignee: THE BOEING COMPANY
    Inventors: John E. Rogers, John Dalton Williams
  • Patent number: 10985121
    Abstract: Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chang-Pin Huang, Tung-Liang Shao, Hsien-Ming Tu, Ching-Jung Yang, Yu-Chia Lai
  • Patent number: 10985115
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10971454
    Abstract: A semiconductor package includes: a core structure having first and second surfaces and having first and second through-holes; a first semiconductor chip embedded in the core structure and having first and second contacts disposed on two opposing surfaces thereof, respectively; a first wiring layer on the surface of the core structure and connected to the first contact; a second wiring layer on the second surface of the core structure and connected to the second contact; a chip antenna disposed in the first through-hole; a second semiconductor chip in the second through-hole and having a connection pad; a first redistribution layer on the first surface of the core structure and connected to the connection terminal, the connection pad, and the first wiring layer; an encapsulant encapsulating the chip antenna and the second semiconductor chip; and a second redistribution layer on the encapsulant connecting to the second wiring layer.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Rok Kim, Young Sik Hur, Young Kwan Lee, Jung Hyun Cho, Seung Eun Lee
  • Patent number: 10964643
    Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Lim Suk, Seokhyun Lee
  • Patent number: 10937772
    Abstract: A semiconductor package structure includes an interconnection structure having a first surface and a second surface opposite to the first surface, a die surrounded by a molding compound over the first surface of the interconnection structure, and a passive device surrounded by a dielectric structure over the second surface of the interconnection structure. The passive device is electrically coupled to the die by the interconnection structure.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Patent number: 10910314
    Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Li-Sheng Weng, Chung-Hao Joseph Chen, Emile Davies-Venn, Kemal Aygun, Mitul B. Modi
  • Patent number: 10903168
    Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 26, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind S. Bhagavat, Lei Fu, Farshad Ghahghahi
  • Patent number: 10861799
    Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Li-Chung Kuo, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Kung-Chen Yeh
  • Patent number: 10847468
    Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-youn Kim, Seok-hyun Lee
  • Patent number: 10849235
    Abstract: A method of manufacture of a structure includes obtaining or producing a functional electronics assembly including at least a first substrate, at least one electronics component on the first substrate, and at least one connection portion, providing the functional electronics assembly on a first substrate film, wherein the functional electronics assembly is connected to the first substrate film via the at least one connection portion, and providing first material to at least partly embed the at least one electronics component into the first material. The first substrate film is adapted to include a recess defining a volume, and the at least one electronics component is arranged at least partly in the volume.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 24, 2020
    Assignee: TACTOTEK OY
    Inventors: Tomi Simula, Mika Paani, Miikka Kärnä, Outi Rusanen, Johanna Juvani, Tapio Rautio, Marko Suo-Anttila, Mikko Heikkinen
  • Patent number: 10833000
    Abstract: A display device includes a display panel comprising a first substrate, a second substrate provided on the first substrate, and side electrodes provided on a side surface of the first substrate and a side surface of the second substrate aligned to the side surface of the first substrate; a driver unit comprising a circuit board, driving electrodes provided on the circuit board to face the side electrodes, and driving signal lines provided on the circuit board, the driving signal lines are connected to the driving electrodes, respectively; and an adhesive member provided between the side electrodes and the circuit board, the adhesive member comprising: a first adhesive portion configured to adhere and electrically connect a first driving electrode of the driving electrodes to a first side electrode of the side electrodes; and a second adhesive portion configured to adhere the circuit board to the first side electrode.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: November 10, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myong-soo Oh, Hyunchul Jin
  • Patent number: 10827625
    Abstract: An anisotropic conductive film includes an electrically conductive particle dispersion layer, which includes electrically conductive particles dispersed, in a predetermined dispersion state, in an electrically insulating adhesive. The anisotropic conductive film includes a defective portion indication means configured to provide information about a location of a defective portion regarding the dispersion state of the electrically conductive particles. A bonding method for bonding the anisotropic conductive film to an electronic component is performed such that, in accordance with the information about the location of the defective portion, obtained from the defective portion indication means, a defect-free portion of the anisotropic conductive film is bonded to a region where terminals or terminal arrays are present in the electronic component to be anisotropically conductively connected.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: November 3, 2020
    Assignee: DEXERIALS CORPORATION
    Inventor: Seiichiro Shinohara
  • Patent number: 10818642
    Abstract: A flexible multilayer construction (1000) for mounting a plurality of light emitting semiconductor devices (LESDs 100, 110, 120) includes a flexible dielectric substrate (200) comprising top (210) and bottom (220) major surfaces, and pluralities of corresponding electrically conductive top (300, 310, 320, 330) and bottom (500, 510, 520, 530) pads disposed on the top and bottom major surfaces, respectively. An electrically conductive via (400, 410, 420, 430) connects each pair of corresponding top and bottom pads, a side of each top pad partially overlapping a side of the corresponding bottom pad and a side of the substrate, such that in a plan view, each top pad fully overlaps the corresponding bottom pad.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 27, 2020
    Assignee: 3M Innovative Properties Company
    Inventors: Alejandro Aldrin Il A. Narag, Ravi Palaniswamy
  • Patent number: 10811358
    Abstract: A semiconductor package includes an organic frame having first and second surfaces opposing each other, having a cavity, and having a wiring structure connecting the first and second surfaces, a connection structure disposed on the first surface of the organic frame and having a first redistribution layer connected to the wiring structure, at least one inorganic interposer having first and second surfaces, and having an interconnection wiring connecting the first and second surfaces of the at least one inorganic interposer to each other, an encapsulant encapsulating at least a portion of the at least one inorganic interposer, an insulating layer disposed on the second surface of the organic frame and the second surface of the at least one inorganic interposer, a second redistribution layer having portions provided as a plurality of pads, and at least one semiconductor chip having connection electrodes respectively connected to the plurality of pads.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO. LTD.
    Inventors: Job Ha, Sung Hyun Kim, Ji Na Jeung
  • Patent number: 10811931
    Abstract: The present disclosure relates to an electrical connector assembly for a motor and a method for producing the electrical assembly. The electrical connector assembly includes a first electrical terminal device, disposed at one end and having electrical terminals, and a second electrical terminal device, disposed at the other end having electrical terminals. A wire rail with the terminals connects the two terminal devices. The wire rail and at least parts of the terminal devices are jointly encompassed and insulated relative to one another by an insulating material.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 20, 2020
    Assignee: ebm-papst Mulfingen GmbH & Co. KG
    Inventors: Martin Münz, Florian Friedlein
  • Patent number: 10811328
    Abstract: A semiconductor package may include a frame including an insulation layer having a cavity formed in a lower surface of the insulation layer, a first post and a second post spaced apart from the cavity, and a metal plate disposed on an upper side of the cavity; a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposing the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers. The first post is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second post is spaced apart from the first post.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung Sam Kang, Moon Il Kim, Young Gwan Ko
  • Patent number: 10804173
    Abstract: The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 13, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Han Chen, Hsun-Wei Chan, Mei-Yi Wu
  • Patent number: 10797008
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10797213
    Abstract: A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 6, 2020
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chin-Tang Hsieh, Cheng-Hung Shih
  • Patent number: 10770383
    Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hohyeuk Im
  • Patent number: 10756030
    Abstract: A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Eun Park, Mi Jin Park
  • Patent number: 10748825
    Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 10743404
    Abstract: A semiconductor device includes a metal base, a transistor die mounted on the metal base, a lid over the transistor die, and a multilayer printed circuit board electrically connected to the transistor die. The multilayer printed circuit board comprises a first portion positioned between the lid and the metal base, a second portion positioned outside of the lid, a plurality of embedded conductive layers, an embedded dielectric layer disposed between at least two of the plurality of embedded conductive layers, and at least one embedded reactive component formed from at least one of the embedded conductive layers.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 11, 2020
    Assignee: CREE, INC.
    Inventors: Qianli Mu, Cristian Gozzi, Asmita Dani
  • Patent number: 10734315
    Abstract: A display device includes a substrate; a pixel connected to a gate line and a data line on the substrate; a connection unit connected to one of the gate line and the data line of the substrate; and a driving integrated circuit mounted on the connection unit. The connection unit includes: a lead line connected to the driving integrated circuit; and at least one first dummy line adjacent to a first side of the connection unit intersecting a side of the substrate, the first dummy line not connected to any line of the connection unit including the driving integrated circuit and the lead line.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: August 4, 2020
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Myongsoo Oh
  • Patent number: 10734328
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10714417
    Abstract: A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack
  • Patent number: 10706346
    Abstract: The invention relates to a method for producing a chip card module. According to this method, the following are produced: a module with a substrate having contacts and an electronic chip connected to at least some contacts; an antenna on a carrier, this antenna including two ends, each equipped with a connection land; a cavity in at least one layer of the card at least partially covering the carrier, in order to house the module and to expose the connection lands of the antenna; a first end of a wire is connected directly to a connection pad of the chip, and another portion is connected directly to a connection land of the antenna, after having inserted the module into the cavity.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 7, 2020
    Assignee: Linxens Holding
    Inventor: Eric Eymard
  • Patent number: 10684322
    Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: June 16, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rubin Ajit Parekhji, Mahesh M. Mehendale, Vinod Menezes, Vipul K. Singhal
  • Patent number: 10679973
    Abstract: Emitter packages and LEDs displays utilizing the packages are disclosed, with the packages providing advantages such as reducing the cost and interconnect complexity for the packages and displays. One emitter package comprises a casing with a plurality of cavities, each cavity having at least one LED. A lead frame structure is included integral to the casing, with the at least one LED from each of the cavities mounted to the lead frame structure. The package is capable of receiving electrical signals for independently controlling the emission from a first and second of the cavities. One LED display utilizes the LED packages mounted in relation to one another to generate a message or image. The LED packages comprise multiple pixels each having at least one LED, with each package capable of receiving electrical signals for independently controlling the emission of at least a first and second of the pixels.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 9, 2020
    Assignee: Cree Huizhou Solid State Lighting Company Limited
    Inventors: Chak Hau Charles Pang, Chi Keung Alex Chan, David Emerson, Yue Kwong Victor Lau, Zhenyu Zhong
  • Patent number: 10672688
    Abstract: A semiconductor power device including a base plate, a ring frame disposed over the base plate, a semiconductor power die disposed on the base plate and surrounded by the ring frame, an input lead by way the semiconductor power die receives an input signal, wherein the input lead is disposed over a first portion of the ring frame, and an output lead by way an output signal generated by the semiconductor power die is sent to another device, wherein the output lead is disposed over a second portion of the ring frame. The ring frame may be comprised of a relatively high thermal conductivity material, such as beryllium-oxide (Be), silicon-carbide (SiC), diamond, aluminum nitride (AlN), or others. The ring frame produces at least one more heat path between the active region of the semiconductor power die and the base plate so as to reduce the effective thermal impedance.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 2, 2020
    Assignee: Integra Technologies, Inc.
    Inventor: William Veitschegger
  • Patent number: 10672712
    Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 2, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind S. Bhagavat, Lei Fu, Farshad Ghahghahi