On Insulating Carrier Other Than A Printed Circuit Board Patents (Class 257/668)
  • Patent number: 10818642
    Abstract: A flexible multilayer construction (1000) for mounting a plurality of light emitting semiconductor devices (LESDs 100, 110, 120) includes a flexible dielectric substrate (200) comprising top (210) and bottom (220) major surfaces, and pluralities of corresponding electrically conductive top (300, 310, 320, 330) and bottom (500, 510, 520, 530) pads disposed on the top and bottom major surfaces, respectively. An electrically conductive via (400, 410, 420, 430) connects each pair of corresponding top and bottom pads, a side of each top pad partially overlapping a side of the corresponding bottom pad and a side of the substrate, such that in a plan view, each top pad fully overlaps the corresponding bottom pad.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 27, 2020
    Assignee: 3M Innovative Properties Company
    Inventors: Alejandro Aldrin Il A. Narag, Ravi Palaniswamy
  • Patent number: 10811931
    Abstract: The present disclosure relates to an electrical connector assembly for a motor and a method for producing the electrical assembly. The electrical connector assembly includes a first electrical terminal device, disposed at one end and having electrical terminals, and a second electrical terminal device, disposed at the other end having electrical terminals. A wire rail with the terminals connects the two terminal devices. The wire rail and at least parts of the terminal devices are jointly encompassed and insulated relative to one another by an insulating material.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 20, 2020
    Assignee: ebm-papst Mulfingen GmbH & Co. KG
    Inventors: Martin Münz, Florian Friedlein
  • Patent number: 10811328
    Abstract: A semiconductor package may include a frame including an insulation layer having a cavity formed in a lower surface of the insulation layer, a first post and a second post spaced apart from the cavity, and a metal plate disposed on an upper side of the cavity; a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposing the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers. The first post is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second post is spaced apart from the first post.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung Sam Kang, Moon Il Kim, Young Gwan Ko
  • Patent number: 10811358
    Abstract: A semiconductor package includes an organic frame having first and second surfaces opposing each other, having a cavity, and having a wiring structure connecting the first and second surfaces, a connection structure disposed on the first surface of the organic frame and having a first redistribution layer connected to the wiring structure, at least one inorganic interposer having first and second surfaces, and having an interconnection wiring connecting the first and second surfaces of the at least one inorganic interposer to each other, an encapsulant encapsulating at least a portion of the at least one inorganic interposer, an insulating layer disposed on the second surface of the organic frame and the second surface of the at least one inorganic interposer, a second redistribution layer having portions provided as a plurality of pads, and at least one semiconductor chip having connection electrodes respectively connected to the plurality of pads.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO. LTD.
    Inventors: Job Ha, Sung Hyun Kim, Ji Na Jeung
  • Patent number: 10804173
    Abstract: The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 13, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Han Chen, Hsun-Wei Chan, Mei-Yi Wu
  • Patent number: 10797008
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10797213
    Abstract: A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 6, 2020
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chin-Tang Hsieh, Cheng-Hung Shih
  • Patent number: 10770383
    Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hohyeuk Im
  • Patent number: 10756030
    Abstract: A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Eun Park, Mi Jin Park
  • Patent number: 10748825
    Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 10743404
    Abstract: A semiconductor device includes a metal base, a transistor die mounted on the metal base, a lid over the transistor die, and a multilayer printed circuit board electrically connected to the transistor die. The multilayer printed circuit board comprises a first portion positioned between the lid and the metal base, a second portion positioned outside of the lid, a plurality of embedded conductive layers, an embedded dielectric layer disposed between at least two of the plurality of embedded conductive layers, and at least one embedded reactive component formed from at least one of the embedded conductive layers.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 11, 2020
    Assignee: CREE, INC.
    Inventors: Qianli Mu, Cristian Gozzi, Asmita Dani
  • Patent number: 10734328
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10734315
    Abstract: A display device includes a substrate; a pixel connected to a gate line and a data line on the substrate; a connection unit connected to one of the gate line and the data line of the substrate; and a driving integrated circuit mounted on the connection unit. The connection unit includes: a lead line connected to the driving integrated circuit; and at least one first dummy line adjacent to a first side of the connection unit intersecting a side of the substrate, the first dummy line not connected to any line of the connection unit including the driving integrated circuit and the lead line.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: August 4, 2020
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Myongsoo Oh
  • Patent number: 10714417
    Abstract: A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack
  • Patent number: 10706346
    Abstract: The invention relates to a method for producing a chip card module. According to this method, the following are produced: a module with a substrate having contacts and an electronic chip connected to at least some contacts; an antenna on a carrier, this antenna including two ends, each equipped with a connection land; a cavity in at least one layer of the card at least partially covering the carrier, in order to house the module and to expose the connection lands of the antenna; a first end of a wire is connected directly to a connection pad of the chip, and another portion is connected directly to a connection land of the antenna, after having inserted the module into the cavity.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 7, 2020
    Assignee: Linxens Holding
    Inventor: Eric Eymard
  • Patent number: 10684322
    Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: June 16, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rubin Ajit Parekhji, Mahesh M. Mehendale, Vinod Menezes, Vipul K. Singhal
  • Patent number: 10679973
    Abstract: Emitter packages and LEDs displays utilizing the packages are disclosed, with the packages providing advantages such as reducing the cost and interconnect complexity for the packages and displays. One emitter package comprises a casing with a plurality of cavities, each cavity having at least one LED. A lead frame structure is included integral to the casing, with the at least one LED from each of the cavities mounted to the lead frame structure. The package is capable of receiving electrical signals for independently controlling the emission from a first and second of the cavities. One LED display utilizes the LED packages mounted in relation to one another to generate a message or image. The LED packages comprise multiple pixels each having at least one LED, with each package capable of receiving electrical signals for independently controlling the emission of at least a first and second of the pixels.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 9, 2020
    Assignee: Cree Huizhou Solid State Lighting Company Limited
    Inventors: Chak Hau Charles Pang, Chi Keung Alex Chan, David Emerson, Yue Kwong Victor Lau, Zhenyu Zhong
  • Patent number: 10672688
    Abstract: A semiconductor power device including a base plate, a ring frame disposed over the base plate, a semiconductor power die disposed on the base plate and surrounded by the ring frame, an input lead by way the semiconductor power die receives an input signal, wherein the input lead is disposed over a first portion of the ring frame, and an output lead by way an output signal generated by the semiconductor power die is sent to another device, wherein the output lead is disposed over a second portion of the ring frame. The ring frame may be comprised of a relatively high thermal conductivity material, such as beryllium-oxide (Be), silicon-carbide (SiC), diamond, aluminum nitride (AlN), or others. The ring frame produces at least one more heat path between the active region of the semiconductor power die and the base plate so as to reduce the effective thermal impedance.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 2, 2020
    Assignee: Integra Technologies, Inc.
    Inventor: William Veitschegger
  • Patent number: 10672712
    Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 2, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind S. Bhagavat, Lei Fu, Farshad Ghahghahi
  • Patent number: 10658330
    Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: May 19, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu
  • Patent number: 10643956
    Abstract: A semiconductor package includes: a frame having first and second through-holes spaced apart from each other; passive components disposed in the first through-hole; a semiconductor chip disposed in the second through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; a first encapsulant covering at least portions of the passive components and filling at least portions of the first through-hole; a second encapsulant covering at least portions of the semiconductor chip and filling at least portions of the second through-hole; and a connection structure disposed on the frame, the passive components, and the active surface of the semiconductor chip and including wiring layers electrically connected to the passive components and the connection pads of the semiconductor chip. The second encapsulant has a higher electromagnetic wave absorption rate than that of the first encapsulant.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung Joon Kim, Sang Jong Lee, Yoon Seok Seo
  • Patent number: 10645813
    Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Brandon M. Rawlings, Henning Braunisch
  • Patent number: 10629510
    Abstract: An integrated circuit package and a method of fabrication of the same are provided. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
  • Patent number: 10630257
    Abstract: A filter includes a parallel arm resonator and an interdigital capacitor. The parallel arm resonator has an IDT electrode defined by first electrode fingers. The interdigital capacitor is defined by second electrode fingers and is connected to the parallel arm resonator. The electrode finger pitch of the second electrode fingers is smaller than the electrode finger pitch of the first electrode fingers. The film thickness of the second electrode fingers is smaller than the film thickness of the first electrode fingers. A self-resonant frequency of the interdigital capacitor is higher than a pass band of the filter.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 21, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Koji Nosaka
  • Patent number: 10622310
    Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple meta
    Type: Grant
    Filed: September 11, 2016
    Date of Patent: April 14, 2020
    Inventor: Ping-Jung Yang
  • Patent number: 10615056
    Abstract: The present disclosure discloses a method of packaging a chip and a chip package structure. The method of packaging the chip includes: mounting at least one chip to be packaged on a carrier, a back surface of the chip to be packaged facing upwards and an active surface facing towards the carrier; forming a sealing layer, the sealing layer being at least wrapped around the at least one chip to be packaged; forming a first encapsulation layer, wherein the first encapsulation layer covers the entire carrier for encapsulating the at least one chip to be packaged and the sealing layer; detaching the carrier to expose the active surface of the at least one chip to be packaged; and completing the packaging by a rewiring process on the active surface of the at least one chip to be packaged.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 7, 2020
    Assignee: PEP INNOVATION PTE LTD.
    Inventor: Hwee Seng Jimmy Chew
  • Patent number: 10607931
    Abstract: A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack
  • Patent number: 10575394
    Abstract: A Doherty amplifier includes a metal baseplate having a die attach region and a peripheral region; a main amplifier and one or more peaking amplifiers, each amplifier comprising a transistor die that includes at least one RF terminal; and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate. The circuit board includes two embedded electrically conductive layers separated from the two sides by respective composite fiber layers, and an embedded dielectric layer disposed between the embedded electrically conductive layers and having a higher dielectric constant than either of the composite fiber layers. The Doherty amplifier also includes an RF impedance matching network that is electrically connected to an RF terminal of at least one amplifier transistor die, and that comprises one or more reactive components formed from at least one of the embedded electrically conductive layers.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 25, 2020
    Assignee: CREE, INC.
    Inventors: Qianli Mu, Cristian Gozzi, Asmita Dani
  • Patent number: 10559510
    Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Soon Wei Wang, Jin Yoong Liong, Chee Hiong Chew, Francis J. Carney
  • Patent number: 10553529
    Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hohyeuk Im
  • Patent number: 10553544
    Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 10553538
    Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Klaus Jürgen Reingruber, Sven Albers, Christian Georg Geissler, Georg Seidemann, Bernd Waidhas, Thomas Wagner, Marc Dittes
  • Patent number: 10548213
    Abstract: An electronic controlling apparatus includes a circuit board in which conductor layers and insulating layers are disposed alternately. In some embodiments, thicknesses of an upper portion outer conductor layer that is disposed on a first surface of the circuit board and a lower portion outer conductor layer that is disposed on a second surface of the circuit board are identical and have greatest thickness among the conductor layers, or thicknesses of a first outermost position inner conductor layer and a second outermost position inner conductor layer that are positioned at two end portions inside the circuit board are identical and have greatest thickness among the conductor layers, and the conductor layers are disposed symmetrically so as to have a central plane in a thickness direction of the circuit board as a plane of symmetry. In some embodiments, thicknesses and arrangements of conductor layers are not symmetrical in the thickness direction of the circuit board.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 28, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomohiko Nagashima, Yoshihito Asao
  • Patent number: 10541185
    Abstract: A semiconductor device includes a substrate and a bump pattern of a plurality of bumps on the substrate. The bump pattern includes a plurality of rows and a plurality of columns. Bumps of the plurality of bumps include one or more radio frequency (RF) signal bumps for transmission of RF signals during operation or probing of the semiconductor device. Each RF signal bump of the one or more RF signal bumps is surrounded by at least three neighboring bumps immediately adjacent the RF signal bump. Each neighboring bump is selected from the group consisting of (i) a ground bump configured to receive a ground voltage during the operation or probing of the semiconductor device, and (ii) another RF signal bump which defines, together with said RF signal bump, a pair of differential signal bumps for transmission of differential RF signals during the operation or probing of the semiconductor device.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yung-Hsin Kuo
  • Patent number: 10528104
    Abstract: One embodiment is directed towards a molded insulator substrate. The molded insulator substrate includes a first insulator having a first surface and a second surface. A recess in said first surface of the first insulator is configured to facilitate venting of a second insulator over exposed regions of the first surface. A first conductive terminal is exposed through the first surface. A second conductive terminal is exposed through the second surface and electrically coupled to the first terminal.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: January 7, 2020
    Assignee: Intersil Americas LLC
    Inventor: Randolph Cruz
  • Patent number: 10490468
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed over the substrate. The semiconductor device structure also includes a protection layer formed over the conductive pad, and the protection layer has a trench. The semiconductor device structure further includes a conductive structure accessibly arranged through the trench of the protection layer and electrically connected to the conductive pad. The conductive structure has a curved top surface that defines an apex, and an apex of the curved top surface is higher than a top surface of the protection layer.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Chun Tsai, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 10485112
    Abstract: A ceramic circuit substrate according to the present invention includes a ceramic substrate, a copper circuit made of a copper-based material bonded, via a bonding layer, to a surface of the ceramic, and a copper heat sink made of the copper-based material bonded, via a bonding layer, to the other surface of the ceramic. The bonding layers each include a brazing material component including two or more kinds of metals, such as Ag, and an active metal having a predetermined concentration. The bonding layers each include a brazing material layer including the brazing material component, and an active metal compound layer containing the active metal. A ratio of a bonding area of the active metal compound layer in a bonding area of each of the bonding layers is 88% or more.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: November 19, 2019
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventor: Takaomi Kishimoto
  • Patent number: 10475774
    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
  • Patent number: 10459489
    Abstract: A display panel includes a first portion including a display area; a second portion adjacent to the first portion in a first direction; and a bendable portion connecting the first and second portions and at which the display panel is bent about a bending axis extending in a second direction perpendicular to the first direction. The bendable portion includes: a stress concentration portion to which a stress is applied; and first and second stress generation portions at opposing sides of the stress concentration portion in the first direction, and to which stress is applied less than that applied to the stress concentration portion. Each of the first and second stress generation portions defines a second width in the second direction, the stress concentration portion defines a third width in the second direction less than the second width, and the second width is less than the first width.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: October 29, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Bugyoon Yoo, Kyuhan Bae
  • Patent number: 10438879
    Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hohyeuk Im
  • Patent number: 10439112
    Abstract: Light emitter packages, systems, and methods having improved performance are disclosed. In one aspect, a light emitter package can include a submount that can include an anode and a cathode. A light emitter chip can be disposed over the submount such that the light emitter chip is mounted over at least a portion of the cathode and wirebonded to at least a portion of the anode.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: October 8, 2019
    Assignee: Cree, Inc.
    Inventors: Joseph G. Clark, Jeffrey Carl Britt, Amber C. Abare, Raymond Rosado, Harsh Sundani, David T. Emerson, Jeremy Scott Nevins
  • Patent number: 10438873
    Abstract: Disclosed herein is a semiconductor chip package having a heat dissipating structure. The semiconductor chip package including: a semiconductor chip configured such that a plurality of terminals protrudes from the upper surface thereof; lead frames connected to the terminals located on the upper surface of the semiconductor chip; and a package body configured to protect the semiconductor chip and the lead frames and to form the outside shape of the semiconductor chip package, and formed by molding. The lower surfaces of the lead frames are exposed to the outside. The lower surface of the package body is partially cut out such that the bottom surface of the semiconductor chip is exposed to the outside.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 8, 2019
    Assignee: JMJ KOREA CO., LTD.
    Inventors: Yunhwa Choi, Jeonghun Cho
  • Patent number: 10433413
    Abstract: A manufacturing method of circuit structure embedded with heat-dissipation block including the following steps is provided. A core board including a first dielectric layer and two first conductive layers located on two opposite sides of the first dielectric layer is provided. A through hole penetrated the core board is formed. A heat-dissipation block is disposed into the through hole. Two inner-layer circuits are formed on two opposite sides of the core board. At least one build-up structure is bonded on the core board, wherein the build-up structure includes a second dielectric layer and a second conductive layer, and the second dielectric layer is located between the second conductive layer and the core board. A cavity is formed on a predetermined region of the build-up structure, and the cavity is communicated with the corresponding inner-layer circuit. Another manufacturing method of circuit structure embedded with heat-dissipation block is also provided.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: October 1, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Cheng-Po Yu, Ming-Chia Li
  • Patent number: 10424555
    Abstract: A mounting component includes a main body and a metal layer. The main body has a first main surface and a second main surface. The metal layer is arranged on the first main surface of the main body. The metal layer includes at least one concave recognition mark having an inclined surface that is inclined with respect to a main surface of the metal layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 24, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Masatoshi Nakagaki
  • Patent number: 10424536
    Abstract: Electronic component having a first lead frame consisting of an electrically conductive material. The first lead frame carries a first semiconductor component. In the plane of the lead frame a shunt element is arranged, wherein the shunt element comprises a resistor body arranged between a first terminal contact and a second terminal contact. An electrically conducting connection extends from a terminal of the first semiconductor component through the first lead frame to the first terminal contact of the shunt element. A current measurement with good accuracy is facilitated.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 24, 2019
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Christian Rössle
  • Patent number: 10410961
    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Ho Lee, Myung Sam Kang, Young Gwan Ko, Jin Su Kim, Shang Hoon Seo, Jeong Il Lee
  • Patent number: 10381293
    Abstract: An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 13, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng@Eugene Lee, Chong Han Lim, You Chye How
  • Patent number: 10373987
    Abstract: An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 6, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dae Geun Lee
  • Patent number: 10347565
    Abstract: A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 9, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Si Hyeon Go, Jae Sik Choi, Myung Ho Park, Dong Seong Oh, Beom Su Kim
  • Patent number: 10340232
    Abstract: A wiring substrate includes a coil wiring and a magnetic layer that is in contact with a lower surface of the coil wiring and includes an opening extending through in a thickness-wise direction. The wiring substrate further includes a first insulation layer covering the coil wiring, an upper surface of the magnetic layer, and a wall surface of the opening and a signal wiring structure formed so that a signal of a semiconductor element, when mounted on the wiring substrate, travels through the opening of the magnetic layer. The signal wiring structure includes a first wiring portion located on an upper surface of the first insulation layer and a first via wiring located inward from the opening of the magnetic layer and connected to the first wiring portion. The magnetic layer is not in contact with the signal wiring structure.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 2, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Toshiaki Aoki, Shinji Nakazawa