On Insulating Carrier Other Than A Printed Circuit Board Patents (Class 257/668)
  • Patent number: 10410961
    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Ho Lee, Myung Sam Kang, Young Gwan Ko, Jin Su Kim, Shang Hoon Seo, Jeong Il Lee
  • Patent number: 10381293
    Abstract: An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 13, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng@Eugene Lee, Chong Han Lim, You Chye How
  • Patent number: 10373987
    Abstract: An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 6, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dae Geun Lee
  • Patent number: 10347565
    Abstract: A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 9, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Si Hyeon Go, Jae Sik Choi, Myung Ho Park, Dong Seong Oh, Beom Su Kim
  • Patent number: 10340232
    Abstract: A wiring substrate includes a coil wiring and a magnetic layer that is in contact with a lower surface of the coil wiring and includes an opening extending through in a thickness-wise direction. The wiring substrate further includes a first insulation layer covering the coil wiring, an upper surface of the magnetic layer, and a wall surface of the opening and a signal wiring structure formed so that a signal of a semiconductor element, when mounted on the wiring substrate, travels through the opening of the magnetic layer. The signal wiring structure includes a first wiring portion located on an upper surface of the first insulation layer and a first via wiring located inward from the opening of the magnetic layer and connected to the first wiring portion. The magnetic layer is not in contact with the signal wiring structure.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 2, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Toshiaki Aoki, Shinji Nakazawa
  • Patent number: 10304805
    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Mark E. Tuttle
  • Patent number: 10304784
    Abstract: A fan-out semiconductor package includes a wiring portion, semiconductor chips, a dummy chip, and an encapsulant. The wiring portion includes an insulating layer, conductive patterns formed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns. The semiconductor chips are disposed on one region of the wiring portion, and the dummy chip is disposed on another region thereof and has a thickness smaller than those of the semiconductor chips. The encapsulant encapsulates at least portions of the semiconductor chips and the dummy chip. An upper surface of the wiring portion is disposed below a center line of the fan-out semiconductor package, and the thickness t of the dummy chip is such that T/2?t?3T/2 in which T is a distance from the upper surface of the wiring portion to the center line of the fan-out semiconductor package.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Man Kim, Han Kim, Kyung Ho Lee
  • Patent number: 10295563
    Abstract: Provided are a test socket for a semiconductor device and a test device including the test socket. The test device includes a test socket including terminals arranged in a two-dimensional array and corresponding to terminals of the semiconductor device and a ground line extending along at least one row of two-dimensional array; and a substrate electrically connected to the test socket so as to transmit and receive a test signal. The test socket includes a ground line extending along at least one row of the two-dimensional array.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi-so Kim, Jong-won Han
  • Patent number: 10276486
    Abstract: A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 30, 2019
    Assignee: General Electric Company
    Inventors: Thomas Bert Gorczyca, Richard Joseph Saia, Paul Alan McConnelee
  • Patent number: 10276543
    Abstract: A semiconductor device package includes a lower redistribution structure, an upper encapsulated semiconductor device and an upper redistribution structure. The lower redistribution structure includes a first dielectric layer, a RDL, a second dielectric layer, and a second RDL. The first RDL is disposed on the first dielectric layer and includes a circuit portion and an alignment mark portion insulated from the circuit portion. The second dielectric layer is disposed on the first RDL, wherein the second dielectric layer covers the alignment mark portion. The second RDL is disposed on the second dielectric layer and electrically connected to the first RDL. The upper encapsulated semiconductor device is disposed on the lower redistribution structure. The upper redistribution structure is disposed on the upper encapsulated semiconductor device.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sih-Hao Liao, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10269682
    Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Chi-Hsi Wu, Shin-Puu Jeng, Tsung-Yu Chen, Wensen Hung
  • Patent number: 10231335
    Abstract: The present invention generally provides a novel method for manufacturing an electronic module with crossed conducting lines and a novel electronic module with crossed conducting lines. In particular, an aspect of the present invention is to provide a thin, single layer electronic module. It is also an object of the present invention to provide an electronic module with an embedded jumper element having reliable high quality connections and contacts. To achieve at least some of the aspects of the present invention, an embedded pre-fabricated jumper module is placed inside a printed circuit board which allows the crossing of conducting lines within the module without manufacturing additional layers over the whole PCB board. The resultant PCB will have improved contacts and will not have surface deformation.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 12, 2019
    Assignee: GE Embedded Electronics Oy
    Inventors: Petteri Palm, Tuomas Waris, Antti Iihola
  • Patent number: 10225922
    Abstract: A semiconductor package includes a metal baseplate having a die attach region and a peripheral region, a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate. The multilayer circuit board includes two embedded electrically conductive layers that are separated from the first and second sides by layers of composite fiber, and an embedded dielectric layer disposed between the two embedded electrically conductive layers. The embedded dielectric layer has a higher dielectric constant than the layers of composite fiber.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: March 5, 2019
    Assignee: Cree, Inc.
    Inventors: Qianli Mu, Cristian Gozzi, Asmita Dani
  • Patent number: 10211142
    Abstract: A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible substrate. A circuit layer of the flexible substrate includes a plurality of first upper leads, second upper leads, first conductive vias and lower leads. The second upper leads are disposed in the chip mounting area and divided into groups, and each second upper lead has a second inner end and an upper pad opposite to each other. The upper pads of each group are arranged layer by layer into at least two rows. There are two upper pads symmetrically arranged on both sides of a reference line of each group on at least one row furthest from the second inner ends. The first conductive vias connect the upper pads and the lower leads. The chip is mounted in the chip mounting area.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: February 19, 2019
    Assignee: ChipMOS Technologies Inc.
    Inventors: Pi-Chang Chen, Yong-Fang Chiang
  • Patent number: 10199313
    Abstract: The present disclosure relates to a ring-frame power package that includes a thermal carrier, a spacer ring residing on the thermal carrier, and a ring structure residing on the spacer ring. The ring structure includes a ring body and a number of interconnect tabs that protrude from an outer periphery of the ring body. Herein, a portion of the carrier surface of the thermal carrier is exposed through an interior opening of the spacer ring and an interior opening of the ring body. The spacer ring is not electronically conductive and prevents the interconnect tabs from electrically coupling to the thermal carrier. Each interconnect tab includes a top plated area and a bottom plated area, which is electrically coupled to the top plated area.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: February 5, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Robert Charles Dry
  • Patent number: 10186447
    Abstract: A method for bonding thin chips to a target substrate is described herein. According to an example method, an adhesive tape is provided with thinned chips attached thereto. The chips are transferred to a carrier substrate by one or more tape-to-tape transfer steps. The carrier is then diced into separate carrier-and-chip assemblies, which can be handled by existing tools designed for handling chips of regular thickness. The fact that the thinning step is separate from the carrier attachment may lead to reduced thickness variation of the chips. The use of tape-to-tape transfer steps allows for attaching either the front or the back side of the chips to the carrier. The use of an individual carrier per chip allows for treating the thinned chip as if it were a standard chip.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 22, 2019
    Assignees: IMEC VZW, Universiteit Gent
    Inventors: Philip Ekkels, Tom Sterken
  • Patent number: 10186468
    Abstract: According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 22, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Stephan Pindl, Daniel Lugauer, Dominic Maier, Alfons Dehe
  • Patent number: 10170405
    Abstract: A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: January 1, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Toyoaki Sakai
  • Patent number: 10163803
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first die, at least one through integrated fan-out via and a molding layer. The at least one through integrated fan-out via is aside the first die and includes a seed layer and a metal layer. The molding layer encapsulates the at least one through integrated fan-out via and the first die. Besides, the seed layer surrounds a sidewall of the metal layer and is between the metal layer and the molding layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming-Shih Yeh
  • Patent number: 10153255
    Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
  • Patent number: 10149381
    Abstract: The present disclosure relates to a method of integrating a interposer device with a textile layer, wherein the interposer device is a stretchable interposer device comprising a stretchable electrically conductive structure with at least one contact pad for establishing at least one electrically conductive path towards the textile layer. The interposer device is arranged to be mechanically attached to a textile layer comprising a plurality of yarns, at least one of which is an electrically conductive yarn. An electrical connection is established between the at least one conductive yarn of the textile layer and the at least one contact pad, which electrical connection is established after the interposer device has been mechanically attached to the textile layer.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: December 4, 2018
    Assignees: IMEC vzw, Universiteit Gent
    Inventors: Bjorn Van Keymeulen, Frederick Bossuyt, Thomas Vervust
  • Patent number: 10144634
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 4, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Ung Lee, Byong Jin Kim, Young Seok Kim, Wook Choi, Seung Jae Yoo, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang
  • Patent number: 10141292
    Abstract: A display device includes: a display panel driven to display an image, the display panel including a substrate including a display area at which the image is displayed; a terminal pad on the substrate and through which a driving signal is applied to the display area; a driving chip through which the driving signal is applied to the terminal pad; and a non-conductive film which fixes the driving chip to the substrate. The driving chip includes: a non-conductive elastic support body projected from a surface of the driving chip; a bump wiring on the non-conductive elastic support body, the bump wiring directly contacting the terminal pad to apply the driving signal to the terminal pad; and a dispersed particle on the non-conductive elastic support body.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoungyong Kim, Jonghyuk Lee, Jeongho Hwang
  • Patent number: 10103115
    Abstract: A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings. Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: October 16, 2018
    Assignee: VIA Technologies, Inc.
    Inventor: Chen-Yueh Kung
  • Patent number: 10070523
    Abstract: A printed wiring board includes a resin insulating layer, a wiring conductor layer embedded in the insulating layer such that the wiring layer has first surface exposed from the insulating layer, and a conductor post formed in the insulating layer and on second surface of the wiring layer on the opposite side with respect to the first surface of the wiring layer such that the conductor post has side surface covered by the insulating layer and end surface exposed from the insulating layer on the opposite side with respect to the wiring layer. The conductor post is formed such that the side surface of the conductor post is a roughened side surface having surface roughness of first roughness R1, the end surface of the conductor post is a roughened end surface having surface roughness of second roughness R2, and the first and second roughnesses R1, R2 satisfy R1>R2.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: September 4, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Shunsuke Sakai, Toshiki Furutani, Kosuke Ikeda, Takema Adachi, Takayuki Katsuno
  • Patent number: 10062630
    Abstract: A semiconductor die includes an III-V semiconductor body having a periphery devoid of active devices, the periphery terminating at an edge face of the semiconductor die. The semiconductor die further includes a seal ring structure above the periphery of the III-V semiconductor body and a barrier. The barrier is disposed over the periphery of the III-V semiconductor body at least between the seal ring structure and the edge face of the semiconductor die. The barrier has a density which prevents water, water ions, sodium ions and potassium ions from diffusing through the barrier.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 28, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 10049964
    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: August 14, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Yu Gu
  • Patent number: 10043774
    Abstract: An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body. The second conductive line is embedded in the main body. The protrusion pad is disposed on the first conductive line. The protrusion pad protrudes from the main body and is configured to be in electrical contact with a solder portion of a semiconductor chip. A first spacing between the protrusion pad and the second conductive line is determined in accordance with a process deviation of the protrusion pad by the width of the protrusion pad and the width of the first conductive line. Moreover, a semiconductor package having the IC packaging substrate and a manufacturing method of the semiconductor package are also provided.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wei Lin, Chen-Shien Chen, Guan-Yu Chen, Tin-Hao Kuo, Yen-Liang Lin
  • Patent number: 10037059
    Abstract: A memory slot filler for a computer is provided. The slot filler can be used in place of a memory module in a computer system. The slot filler includes at least some exterior dimensions that are smaller than the corresponding exterior dimensions of a memory module.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: William J. Anderl, Cody J. Erie
  • Patent number: 10020245
    Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: July 10, 2018
    Assignee: Infineon Technologies AG
    Inventors: Henrik Ewe, Joachim Mahler, Anton Prueckl, Stefan Landau
  • Patent number: 10014263
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventor: Takashi Shuto
  • Patent number: 10014242
    Abstract: The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: July 3, 2018
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Shih-Ping Hsu
  • Patent number: 10014286
    Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: July 3, 2018
    Assignee: General Electric Company
    Inventors: James Sabatini, Christopher James Kapusta, Glenn Forman
  • Patent number: 10008439
    Abstract: Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 26, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sam Ziqun Zhao, Sam Komarapalayam Karikalan, Edward Law, Rezaur Rahman Khan, Pieter Vorenkamp
  • Patent number: 10002830
    Abstract: One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: June 19, 2018
    Assignee: Infineon Technologies AG
    Inventor: Matthias Stecher
  • Patent number: 10004145
    Abstract: A combined wiring board includes a metal frame having multiple opening portions, and multiple wiring boards accommodated in the opening portions in the metal frame, respectively. The opening portions in the metal frame have side walls having holding portions such that the holding portions hold the wiring boards in the opening portions in the metal frame, and the metal frame has slit portions adjacent to the holding portions and connecting portions connecting the slit portions to the opening portions.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: June 19, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Michimasa Takahashi
  • Patent number: 9991213
    Abstract: A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30) encapsulating the semiconductor chip (1), and lead terminals (21) electrically connected to the semiconductor chip (1) and including inner lead portion (21b) covered with the resin-encapsulating layer (30). The lead terminals (21) are made of copper or a copper alloy. The die pad (10) is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals (21).
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: June 5, 2018
    Assignee: Rohm Co., Ltd.
    Inventors: Yasumasa Kasuya, Motoharu Haga, Shoji Yasunaga
  • Patent number: 9952277
    Abstract: A test device uses a single probe to test plurality of pads of at least one chip, and includes a test circuit, a plurality of short-circuit elements and a plurality of probes. The plurality of short-circuit elements is formed in scribe lines around the at least one chip, where each of the plurality of short-circuit elements connects the plurality of pads, and the plurality of pads includes one testing pad and at least one non-testing pad. The plurality of probes receives a plurality of test signals generated by the at least one chip from the testing pad via the plurality of short-circuit elements, so the test circuit generates a test result according to the plurality of test signals.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 24, 2018
    Assignee: SYNC-TECH SYSTEM CORP.
    Inventors: Hung-Wei Lai, Tsung-Jun Lee
  • Patent number: 9927349
    Abstract: In a method of producing a device in which an element structure is provided on a substrate including a through wiring, a through hole is formed so as to extend from a first surface of the substrate to a second surface of the substrate disposed on an opposite side of the substrate to the first surface, the through wiring is formed by filling the through hole with an electrically conductive material, and the element structure is formed on a first surface side. In the step of forming the through hole, a degree of surface irregularities of an inner wall of the through hole is larger on the first surface side than on a second surface side.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 27, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shinan Wang, Yutaka Setomoto
  • Patent number: 9917047
    Abstract: A wiring board of the present disclosure includes a core substrate, insulating layers, signal wiring conductors, ground wiring conductors, power-supply wiring conductors, a first mounting portion on which a first semiconductor device is to be mounted, a second mounting portion on which a second semiconductor device is to be mounted, many first-semiconductor-device connection pads connectable to signal electrodes of the first semiconductor device, many second-semiconductor-device connection pads connectable to signal electrodes of the second semiconductor device, and many signal connection conductors that connect the first-semiconductor-device connection pads to the second-semiconductor-device connection pads.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: March 13, 2018
    Assignee: KYOCERA Corporation
    Inventor: Takayuki Taguchi
  • Patent number: 9911875
    Abstract: An interdigitated back contact solar cell is provided. The solar cell comprises a solar cell substrate having a light receiving frontside and a backside comprising base and emitter regions. A first level metal (M1) layer is positioned on the substrate backside contacting the base and emitter regions. A second level metal (M2) layer is connected to the first level metal (M1) layer and comprises a base busbar and an emitter busbar. The first level metal comprises substantially orthogonal interdigitated metallization and substantially parallel interdigitated metallization positioned under and corresponding to the base and emitter busbars on the second level metal (M2). The substantially parallel interdigitated metallization of M1 collects carriers of opposite polarity of the corresponding busbar.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: March 6, 2018
    Assignee: Beamreach-Solexel Assets LLC
    Inventors: Swaroop Kommera, Pawan Kapur, Yen-Sheng Su, Vivek Saraswat, Anand Deshpande, Mehrdad M. Moslehi
  • Patent number: 9905526
    Abstract: An electronic component package includes a redistribution layer, an electronic component disposed on the redistribution layer, and an encapsulant encapsulating the electronic component. The electronic component has a trench formed in one side thereof.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: February 27, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyoung Moo Harr, Ji Hoon Kim, Kyung Seob Oh, Sun Ho Kim
  • Patent number: 9898943
    Abstract: The present disclosure provides a liquid crystal display module, which includes a liquid crystal display panel and a driver integrated circuit, wherein the liquid crystal display panel includes a testing pad, a first pad and a second pad, the first pad includes a first sub pad and a second sub pad which are separately disposed, the second sub pad is electrically connected to the testing pad, the driver integrated circuit includes at least two third pads, the third pads are respectively bonded to the first pad and the second pad; the first sub pad and the second sub pad are commonly bonded to one of the third pads, so as to achieve a short circuit between the first sub pad and the second sub pad. In the liquid crystal display module of the present disclosure, the space occupied by the bonding area is small.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 20, 2018
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Xingling Guo, Jiehui Qin, Xiaoping Tan
  • Patent number: 9899250
    Abstract: A method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid electronic packages, tested at their operating temperature and frequency comprises: a step of fabricating reconstituted wafers, each reconstituted wafer being fabricated according to the following sub-steps in the following order: A1)) the electronic packages are placed on a first sticky skin, balls side, B1) molding of the electronic packages in the resin and polymerization of the resin, to obtain the intermediate wafer, C1) thinning of the intermediate wafer on the face of the intermediate wafer opposite to the balls, D1) removal of the first sticky skin and placing of the intermediate wafer on a second sticky skin, side opposite to the balls, E1) thinning of the intermediate wafer on the balls side face, F1) formation of a balls side redistribution layer, G1) removal of the second sticky skin to obtain a reconstituted wafer of smaller thickness than the
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: February 20, 2018
    Assignee: 3D PLUS
    Inventor: Christian Val
  • Patent number: 9899237
    Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: February 20, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
  • Patent number: 9893021
    Abstract: Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wensen Hung
  • Patent number: 9881863
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: January 30, 2018
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
  • Patent number: 9881890
    Abstract: A semiconductor module includes an image pickup device on which a bump is disposed, and a flexible wiring board having a flexible resin as a base and including a wire having a bonding electrode at a distal end portion solder-bonded to the bump, in which the bonding electrode is pressed against the bump by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: January 30, 2018
    Assignee: OLYMPUS CORPORATION
    Inventor: Kazuaki Kojima
  • Patent number: 9865579
    Abstract: In a display device connected with an IC driver, particularly the reliability of connection between an IC terminal located on the outermost side and the IC driver is improved. IC terminals and flexible wiring board terminals are formed on a terminal region of a TFT substrate. A plurality of the IC terminals are formed at a predetermined pitch. The reliability of an outermost IC terminal is degraded as compared with the reliability of the other IC terminals caused by the loading effect in etching a protection insulating film. In order to prevent this degradation, a dummy terminal is formed on the outer side of the outermost IC terminal, and the loading effect on the outermost IC terminal is made equal to the loading effect on the other IC terminals. Accordingly, degradation in the reliability of the outermost IC terminal is prevented.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: January 9, 2018
    Assignee: JAPAN DISPLAY INC.
    Inventor: Takahiro Nagami
  • Patent number: 9857063
    Abstract: The present disclosure provides a lighting module. The lighting module includes a heat sink, a board disposed over the heat sink, and a bonding component that bonds the heat sink and the board together. The bonding component contains a combination of a first metal and a second metal. The lighting module also includes a photonic lighting device disposed over the board.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: January 2, 2018
    Assignee: Epistar Corporation
    Inventor: Wei-Yu Yeh