On Insulating Carrier Other Than A Printed Circuit Board Patents (Class 257/668)
  • Patent number: 11521941
    Abstract: A semiconductor device including a semiconductor chip disposed on a substrate having a conductive pattern, an insulating plate and a metal plate that are sequentially formed and respectively have the thicknesses of T2, T1 and T3. The metal plate has a plurality of depressions formed on a rear surface thereof. In a side view, a first edge face, which is an edge face of the conductive pattern, is at a first distance away from a second edge face that is an edge face of the metal plate, and a third edge face, which is an edge face of the semiconductor chip, is at a second distance away from the second edge face. Each depression is located within a depression formation distance from the first edge face, where: 0<depression formation distance?(0.9×T12/first distance), and/or (1.1×T12/first distance)?depression formation distance<second distance.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: December 6, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshinori Oda, Yoshinori Uezato
  • Patent number: 11512200
    Abstract: A resin composition contains a (A) thermoplastic component, a (B) thermosetting component, and a (C) inorganic filler, 5%-weight-reduction temperature of a hardened substance of the resin composition being 440 degrees C. or more.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 29, 2022
    Assignee: LINTEC CORPORATION
    Inventor: Yasunori Karasawa
  • Patent number: 11515267
    Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Wu, Li-Chung Kuo, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Kung-Chen Yeh
  • Patent number: 11508671
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 11482484
    Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11462445
    Abstract: A semiconductor module including a semiconductor element which is bonded to a wiring pattern part and connects or disconnects two main electrode terminals to or from each other according to a drive signal applied to a gate electrode terminal, includes a deterioration detecting circuit configured to use one main electrode terminal of the two main electrode terminals of the semiconductor element with an applied DC voltage, as a reference potential, and detect deterioration of a joining part of the semiconductor element on the basis of a gate voltage which is the voltage between the one main electrode terminal and the gate electrode terminal and an inter-main-electrode voltage which is the voltage between the one main electrode terminal and the other main electrode terminal, and outputs an alarm signal.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 4, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Eiji Kurosawa
  • Patent number: 11454888
    Abstract: A method of manufacturing a semiconductor device includes forming a polymer mixture over a substrate, curing the polymer mixture to form a polymer material, and patterning the polymer material. The polymer mixture includes a polymer precursor, a photosensitizer, a cross-linker, and a solvent. The polymer precursor may be a polyamic acid ester. The cross-linker may be tetraethylene glycol dimethacrylate. The photosensitizer includes 4-phenyl-2-(piperazin-1-yl)thiazole. The mixture may further include an additive.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 11421316
    Abstract: Methods and apparatus for producing fine pitch patterning on a substrate. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2/2 ?m l/s fine pitch patterning.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 23, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prayudi Lianto, Mohamed Rafi, Muhammad Azim Bin Syed Sulaiman, Guan Huei See, Ang Yu Xin Kristy, Karthik Elumalai, Sriskantharajah Thirunavukarasu, Arvind Sundarrajan
  • Patent number: 11417595
    Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunghun Chae, Youngkwan Seo, Jaeean Lee, Soyeon Moon, Hyeyeong Jo, Iljong Seo
  • Patent number: 11409335
    Abstract: A display device including a display panel having a plurality of signal wirings disposed on a side surface, each of the signal wirings including a first surface and a second surface different from the first surface; and a printed circuit board attached to the side surface of the display panel and including a base film and a plurality of lead wirings disposed on one surface of the base film. Each of the lead wirings includes a first lead portion and a second lead portion having a thickness less than that of the first lead portion. The first lead portion is bonded to the second surface, and the second lead portion is bonded to the first surface.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 9, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventor: Young Cheol Jeong
  • Patent number: 11404375
    Abstract: There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: August 2, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Hideaki Yanagida, Yoshihisa Takada
  • Patent number: 11387213
    Abstract: A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Shun Sing Liao
  • Patent number: 11362062
    Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: June 14, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jihwan Hwang, Unbyoung Kang, Sangsick Park, Jihwan Suh, Soyoun Lee, Teakhoon Lee
  • Patent number: 11355440
    Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-youn Kim, Seok-hyun Lee
  • Patent number: 11342304
    Abstract: A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: May 24, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Shun Sing Liao
  • Patent number: 11342321
    Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.
    Type: Grant
    Filed: January 12, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-Shuan Chung
  • Patent number: 11342287
    Abstract: A semiconductor device includes a substrate, a semiconductor chip, and a sealing member. The semiconductor chip is disposed on the substrate. The semiconductor chip includes a first principal surface on a side of the substrate and a second principal surface on a side opposite to the first principal surface. The sealing member seals the semiconductor chip. The sealing member includes a first sealing member and a second sealing member. The second sealing member faces at least a part of the second principal surface. A permittivity of the second sealing member is lower than a permittivity of the first sealing member.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: May 24, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Daisuke Kimura
  • Patent number: 11342489
    Abstract: A method of connecting a plurality of electronic components to a flexible circuit board comprises: providing a carrier substrate carrying the electronic components, each of the electronic components having at least one electrical contact coated with electrically conductive adhesive; and applying the carrier substrate to the flexible circuit board such that the electronic components are adhered to the flexible circuit board in electrical contact therewith via the conductive adhesive. The electronic components may comprise LEDs and there may be provided one or more optical layers over the flexible circuit board.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: May 24, 2022
    Assignee: DST Innovations Limited
    Inventors: Anthony Miles, Benjamin Masheder
  • Patent number: 11336060
    Abstract: An electrical connector electrically connects a first printed circuit board and a second printed circuit board, where the electrical connector includes: (a) an insulative housing; (b) a plurality of signal conductors, with at least a portion of each of the plurality of signal conductors disposed within the insulative housing; (c) each of the plurality of signal conductors having a first contact end, a second contact end and an intermediate portion therebetween; and (d) a passive circuit element electrically connected to the intermediate portion of each of the plurality of signal conductors, where the passive circuit element is housed in an insulative package and includes at least a capacitor or an inductor.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 17, 2022
    Assignee: AMPHENOL CORPORATION
    Inventors: Leon Khilchenko, Mark W. Gailus
  • Patent number: 11328997
    Abstract: A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Matthew Monroe
  • Patent number: 11315881
    Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: April 26, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Chee-Key Chung
  • Patent number: 11315857
    Abstract: A package structure is provided. The package structure includes a leadframe including a first portion and a second portion. The first portion includes a first base part and a plurality of first extended parts connected to the first base part. The second portion includes a second base part and a plurality of second extended parts connected to the second base part. The first extended parts and the second extended parts are arranged in such a way that they alternate with each other. In the package structure, a chip is disposed on a part of the first extended parts of the first portion and the second extended parts of the second portion of the leadframe. The package structure further includes a plurality of protrusions, opposite to the chip, disposed on the first extended parts and the second extended parts.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 26, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Peng-Hsin Lee
  • Patent number: 11304293
    Abstract: A display apparatus includes a display panel which have first display pads arranged in a first direction, a main circuit board, a first flexible circuit board which includes first substrate pads connected to the main circuit board and the first display pads and a first driving chip connected to the first substrate pads, and is bent in a direction toward a back surface of the display panel, and a protective member disposed on the first flexible circuit board. The protective member covers the first driving chip.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoo jeong Lee, Hyunseop Song, Minsoo Kang, Yeong Won Kim
  • Patent number: 11296033
    Abstract: The invention discloses a fan-out multi-device hybrid integrated flexible micro-system and an associated fabrication method in the field of microelectronics. The flexible microsystem uses microelectromechanical system (MEMS) chips and/or integrated circuit (IC) chips as the device units, flexible isolation trenches filled with flexible polymer as a flexible connection between the device units, and metal wiring layers to provide electrical interconnections between the device units. The disclosed multi-device hybrid integrated flexible micro-system completed by a fan-out method not only retains excellent electrical performance of silicon-based devices, but also realizes flexibility of the overall micro-system, and has stable structure and reliable performance.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 5, 2022
    Assignee: Peking University
    Inventors: Wei Wang, Xiao Dong
  • Patent number: 11289449
    Abstract: Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Monsen Liu, Chen-Hua Yu
  • Patent number: 11289409
    Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 29, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 11282795
    Abstract: A packaged integrated circuit device includes a frame having a cavity therein and an inner semiconductor chip within the cavity. A lower re-distribution layer is provided, which extends adjacent lower surfaces of the frame and the inner semiconductor chip. The lower re-distribution layer has an opening therein which at least partially exposes the lower surface of the inner semiconductor chip. A lower semiconductor chip is provided, which extends adjacent the lower surface of the inner semiconductor chip, and within the opening in the lower re-distribution layer. This lower re-distribution layer includes: (i) an insulating layer covering the lower surface of the frame, (ii) a re-distribution pattern disposed on the insulating layer, and (iii) a barrier layer, which is disposed on the insulating layer and surrounds at least a portion of the lower semiconductor chip.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: March 22, 2022
    Inventor: Sanguk Kim
  • Patent number: 11276623
    Abstract: A circuit carrier for holding at least one electrical power component is disclosed. The circuit carrier including a heat sink for holding and for cooling the power component. The heat sink having a surface. The circuit carrier includes a copper layer for mechanically connecting the heat sink to at least one copper plate, where the copper layer includes copper or a copper alloy and is cold-gas-sprayed or sintered on the surface of the heat sink. The circuit carrier also includes at least one copper plate for mechanically and electrically connecting the power component to the copper layer. The copper plate includes copper or a copper alloy and is arranged directly on a surface of the copper layer facing away from the heat sink and is areally, mechanically and electrically conductively connected to the copper layer.
    Type: Grant
    Filed: February 18, 2018
    Date of Patent: March 15, 2022
    Assignee: VITESCO TECHNOLOGIES GMBH
    Inventors: Erich Mattmann, Sabine Bergmann, Roland Brey, Soeren Rittstieg
  • Patent number: 11272610
    Abstract: A printed wiring board includes a first insulator, a second insulator, a first conductor, and a second conductor. The first conductor is between the first insulator and the second insulator. The first conductor contains a first conductive material. The second conductor includes a first portion. The first portion is between the first insulator and the first conductor. The first portion is in contact with the first conductor and extends along the first conductor. The second conductor contains a second conductive material. The second conductive material is lower in electrical resistivity than the first conductive material. The second insulator is closer to an outside of the printed wiring board than the first insulator is in a thickness direction of the printed wiring board.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: March 8, 2022
    Assignee: Kioxia Corporation
    Inventor: Daigo Suzuki
  • Patent number: 11264316
    Abstract: A package structure includes a first RDL structure, a die, an encapsulant, a film, a TIV and a second RDL structure. The die is located over the first RDL structure. The encapsulant laterally encapsulates sidewalls of the die. The film is disposed between the die and the first RDL structure, and between the encapsulant and the first RDL structure. The TIV penetrates through the encapsulant and the film to connect to the first RDL structure. The second RDL structure is disposed on the die, the TIV and the encapsulant and electrically connected to die and the TIV.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 11264367
    Abstract: The present disclosure relates to an optical module, including: a carrier, a emitter, a detector and an encapsulant. The carrier has a first surface. The emitter is disposed above the first surface. The detector is disposed above the first surface. The encapsulant is disposed on the first surface and exposes at least a portion of the emitter.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: March 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jung-Hsuan Chang, Ying-Chung Chen, Chao-Lin Shih
  • Patent number: 11257778
    Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventor: Xinhua Wang
  • Patent number: 11257772
    Abstract: The present disclosure provides a fan-out antenna packaging structure and a preparation method thereof. The fan-out antenna packaging structure comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip, a via being formed in the plastic packaging material layer; a conductive pole located in the via and running through the plastic packaging material layer from top to bottom; an antenna structure located on a first surface of the plastic packaging material layer and electrically connected with the conductive pole; a redistribution layer located on a second surface of the plastic packaging material layer and electrically connected with the semiconductor chip and the conductive pole; and a solder bump located on a surface of the redistribution layer, electrically connected with the redistribution layer and insulated from the plastic packaging material layer.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 22, 2022
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengchung Lin, Jangshen Lin, Chengtar Wu, Chihon Ho
  • Patent number: 11239168
    Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: February 1, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Hsin-Han Lin, Yu-Min Lin, Tao-Chih Chang
  • Patent number: 11222839
    Abstract: A semiconductor structure includes a substrate, a chip, a first edge pad, a first central pad, a second edge pad, and a second central pad. The substrate has a first surface and a conductive trace extending above the substrate. The chip is above the first surface of the substrate, and has a sidewall, a central area, and an edge area. The first edge pad is on the edge area. The first central pad is on the central area and electrically connected to the first edge pad. The second edge pad is on the edge area of the chip. A distance between the first edge pad and the sidewall of the chip is substantially smaller than a distance between the second edge pad and the sidewall of the chip. The second central pad is on the central area of the chip and electrically connected to the second edge pad.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 11, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11217546
    Abstract: A method includes attaching a voltage regulator to a first redistribution structure of a first package. A second redistribution structure is formed over the voltage regulator, the voltage regulator being embedded in the second redistribution structure. The first substrate is attached to the second redistribution structure to form a second package including the first package. A first voltage may be provided to the second redistribution structure and through the second redistribution structure to the voltage regulator. The voltage regulator regulates the first voltage into a second voltage and provides the second voltage through the first redistribution structure to a first device die, where an output of the voltage regulator is attached directly to the first redistribution structure.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chien-Hsun Chen
  • Patent number: 11189547
    Abstract: A semiconductor module includes a laminated substrate that includes a heat radiating plate, and an insulation layer having a conductive pattern thereof and being disposed on a top surface of the heat radiating plate, a semiconductor element disposed on a top surface of the conductive pattern, an integrated circuit that controls driving of the semiconductor element, a control-side lead frame having a primary surface on which the integrated circuit is disposed, and a mold resin that seals the laminated substrate, the semiconductor element, the integrated circuit, and the control-side lead frame. The control-side lead frame has a rod-shaped first pin having a first end, a first end side of the first pin extending toward the top surface of the heat radiating plate, and the heat radiating plate has at least one insertion hole into one of which the first end of the first pin is press-fitted.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Nobuhiro Higashi
  • Patent number: 11191162
    Abstract: Provided is a circuit board supporting structure capable of easily detaching a circuit board on a base. The circuit board supporting structure is configured to support a circuit board on a base, in which the base has a concave portion formed in a placement surface of the circuit board, and a rotational operation member configured to be rotatably accommodated in the concave portion and extend and retract in a direction perpendicular to the placement surface by a rotational operation, in which the circuit board has a through hole formed at a position corresponding to the concave portion, in which the rotational operation member has a reference surface formed approximately in parallel with the placement surface, and an operation portion formed on a rotational axis of the rotational operation member so as to be exposed from the through hole.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 30, 2021
    Assignee: HOYA CORPORATION
    Inventor: Hiroaki Watanabe
  • Patent number: 11183445
    Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: November 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Frank Daeche, Daniel Schleisser, Thomas Stoek
  • Patent number: 11171122
    Abstract: The semiconductor device includes a substrate having a main surface, a plurality of conductive patterns provided on the main surface, a plurality of switching elements disposed on one of the conductive patterns, each switching element having a first electrode and a second electrode and being connected to the one of the conductive patterns through its first or second electrode, and at least one first wiring member each directly connecting the first electrodes of two switching elements that are respectively disposed on different conductive patterns and are electrically connected in parallel.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shunta Horie, Susumu Iwamoto
  • Patent number: 11165143
    Abstract: An antenna module includes an antenna substrate, a fan-out package and first electrical connection structures. The antenna substrate includes a pattern layer including antenna and ground patterns, and a feeding layer under the pattern layer including a feeding network that supplies power to the antenna patterns. The fan-out package is under the antenna substrate and includes a semiconductor chip driving the antenna substrate, an encapsulant encapsulating some of the semiconductor chip, a first redistribution layer on the semiconductor chip electrically connecting the semiconductor chip with the antenna substrate, and a second redistribution layer under the semiconductor chip electrically connecting the semiconductor chip with external devices. The first electrical connection structures are between and electrically connect the antenna substrate and the fan-out package.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghwa Kim, Heeseok Lee
  • Patent number: 11158582
    Abstract: In one example, a semiconductor device comprises a main substrate having a top side and a bottom side, a first electronic component on the top side of the main substrate, a second electronic component on the bottom side of the main substrate, a substrate structure on the bottom side of the main substrate adjacent to the second electronic component, and an encapsulant structure comprising an encapsulant top portion on the top side of the main substrate and contacting a side of the first electronic component, and an encapsulant bottom portion on the bottom side of the main substrate and contacting a side of the second electronic component and a side of the substrate structure. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 26, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jin Seong Kim, Yeong Beom Ko, Kwang Seok Oh, Jo Hyun Bae, Sung Woo Lim, Yun Ah Kim, Yong Jae Ko, Ji Chang Lee
  • Patent number: 11158576
    Abstract: A package structure includes a redistribution layer (RDL) structure, a die, and an encapsulant. The die is attached to the RDL structure through an adhesive layer. The encapsulant is disposed on the RDL structure and laterally encapsulates the die and the adhesive layer. The encapsulant includes a protruding part extending into the RDL structure and having a bottom surface in contact with the RDL structure.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Hao-Yi Tsai, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Patent number: 11145639
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Wei Cheng, Chien-Hsun Lee, Chi-Yang Yu, Hao-Cheng Hou, Hsin-Yu Pan, Tsung-Ding Wang
  • Patent number: 11145637
    Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yanggyoo Jung, Chulwoo Kim, Hyo-Chang Ryu, Yun Seok Choi
  • Patent number: 11121119
    Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a flexible substrate, a driving circuit, and a memory. The substrate has a first surface and a second surface opposite to each other, and the first surface has a display region and a bonding region. The display unit is disposed on the display region of the first surface. The flexible substrate is disposed below the second surface and has a connection portion extended to the bonding region of the first surface. The driving circuit is disposed on the flexible substrate and electrically connects with the display unit. The memory is disposed on the flexible substrate and electrically connects with the driving circuit.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 14, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Liang Chen, Hann-Jye Hsu
  • Patent number: 11121090
    Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changbo Lee, Joonseok Oh, Byunglyul Park
  • Patent number: 11121064
    Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Park, Da Hye Kim, Jin-Woo Park, Jae Gwon Jang
  • Patent number: 11116087
    Abstract: Disclosed are a display module and a display device. The display module includes a display panel having a light emitting surface and a back surface opposite to the light emitting surface; a drive circuit board disposed adjacent to an edge at a side of the display panel, and a wiring gap is formed between the drive circuit board and the display panel; a chip-on-film, a first connecting end of which is disposed on the light emitting surface and connected to the display panel, and a second connecting end of which passes through the wiring gap and extends to the back surface of the display panel; and an adapter structure disposed on a side of the second connecting end of the chip-on-film facing away from the display panel, connected between the chip-on-film and the drive circuit board.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: September 7, 2021
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiaoxia Huang, Shuang Zhang, Bing Ji, Chang Zhang
  • Patent number: RE49031
    Abstract: LED assemblies and related LED light bulbs. An LED assembly has a flexible, transparent substrate, an LED chip on the first surface and electrically connected to two adjacent conductive sections, a first wavelength conversion layer, formed on the first surface to substantially cover the LED chip, and a second wavelength conversion layer formed on the second surface. The flexible, transparent substrate has first and second surfaces opposite to each other, and several conductive sections, which are separately formed on the first surface.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 12, 2022
    Assignees: EPISTAR CORPORATION, KAISTAR LIGHTING (XIAMEN) CO., LTD.
    Inventors: Hong-Zhi Liu, Tzu-Chi Cheng