Abstract: An electronic controlling apparatus includes a circuit board in which conductor layers and insulating layers are disposed alternately. In some embodiments, thicknesses of an upper portion outer conductor layer that is disposed on a first surface of the circuit board and a lower portion outer conductor layer that is disposed on a second surface of the circuit board are identical and have greatest thickness among the conductor layers, or thicknesses of a first outermost position inner conductor layer and a second outermost position inner conductor layer that are positioned at two end portions inside the circuit board are identical and have greatest thickness among the conductor layers, and the conductor layers are disposed symmetrically so as to have a central plane in a thickness direction of the circuit board as a plane of symmetry. In some embodiments, thicknesses and arrangements of conductor layers are not symmetrical in the thickness direction of the circuit board.

Abstract: A semiconductor device includes a substrate and a bump pattern of a plurality of bumps on the substrate. The bump pattern includes a plurality of rows and a plurality of columns. Bumps of the plurality of bumps include one or more radio frequency (RF) signal bumps for transmission of RF signals during operation or probing of the semiconductor device. Each RF signal bump of the one or more RF signal bumps is surrounded by at least three neighboring bumps immediately adjacent the RF signal bump. Each neighboring bump is selected from the group consisting of (i) a ground bump configured to receive a ground voltage during the operation or probing of the semiconductor device, and (ii) another RF signal bump which defines, together with said RF signal bump, a pair of differential signal bumps for transmission of differential RF signals during the operation or probing of the semiconductor device.

Abstract: One embodiment is directed towards a molded insulator substrate. The molded insulator substrate includes a first insulator having a first surface and a second surface. A recess in said first surface of the first insulator is configured to facilitate venting of a second insulator over exposed regions of the first surface. A first conductive terminal is exposed through the first surface. A second conductive terminal is exposed through the second surface and electrically coupled to the first terminal.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed over the substrate. The semiconductor device structure also includes a protection layer formed over the conductive pad, and the protection layer has a trench. The semiconductor device structure further includes a conductive structure accessibly arranged through the trench of the protection layer and electrically connected to the conductive pad. The conductive structure has a curved top surface that defines an apex, and an apex of the curved top surface is higher than a top surface of the protection layer.

Abstract: A ceramic circuit substrate according to the present invention includes a ceramic substrate, a copper circuit made of a copper-based material bonded, via a bonding layer, to a surface of the ceramic, and a copper heat sink made of the copper-based material bonded, via a bonding layer, to the other surface of the ceramic. The bonding layers each include a brazing material component including two or more kinds of metals, such as Ag, and an active metal having a predetermined concentration. The bonding layers each include a brazing material layer including the brazing material component, and an active metal compound layer containing the active metal. A ratio of a bonding area of the active metal compound layer in a bonding area of each of the bonding layers is 88% or more.

Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.

Abstract: A display panel includes a first portion including a display area; a second portion adjacent to the first portion in a first direction; and a bendable portion connecting the first and second portions and at which the display panel is bent about a bending axis extending in a second direction perpendicular to the first direction. The bendable portion includes: a stress concentration portion to which a stress is applied; and first and second stress generation portions at opposing sides of the stress concentration portion in the first direction, and to which stress is applied less than that applied to the stress concentration portion. Each of the first and second stress generation portions defines a second width in the second direction, the stress concentration portion defines a third width in the second direction less than the second width, and the second width is less than the first width.

Abstract: Light emitter packages, systems, and methods having improved performance are disclosed. In one aspect, a light emitter package can include a submount that can include an anode and a cathode. A light emitter chip can be disposed over the submount such that the light emitter chip is mounted over at least a portion of the cathode and wirebonded to at least a portion of the anode.

Abstract: Disclosed herein is a semiconductor chip package having a heat dissipating structure. The semiconductor chip package including: a semiconductor chip configured such that a plurality of terminals protrudes from the upper surface thereof; lead frames connected to the terminals located on the upper surface of the semiconductor chip; and a package body configured to protect the semiconductor chip and the lead frames and to form the outside shape of the semiconductor chip package, and formed by molding. The lower surfaces of the lead frames are exposed to the outside. The lower surface of the package body is partially cut out such that the bottom surface of the semiconductor chip is exposed to the outside.

Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.

Abstract: A manufacturing method of circuit structure embedded with heat-dissipation block including the following steps is provided. A core board including a first dielectric layer and two first conductive layers located on two opposite sides of the first dielectric layer is provided. A through hole penetrated the core board is formed. A heat-dissipation block is disposed into the through hole. Two inner-layer circuits are formed on two opposite sides of the core board. At least one build-up structure is bonded on the core board, wherein the build-up structure includes a second dielectric layer and a second conductive layer, and the second dielectric layer is located between the second conductive layer and the core board. A cavity is formed on a predetermined region of the build-up structure, and the cavity is communicated with the corresponding inner-layer circuit. Another manufacturing method of circuit structure embedded with heat-dissipation block is also provided.

Abstract: Electronic component having a first lead frame consisting of an electrically conductive material. The first lead frame carries a first semiconductor component. In the plane of the lead frame a shunt element is arranged, wherein the shunt element comprises a resistor body arranged between a first terminal contact and a second terminal contact. An electrically conducting connection extends from a terminal of the first semiconductor component through the first lead frame to the first terminal contact of the shunt element. A current measurement with good accuracy is facilitated.

Abstract: A mounting component includes a main body and a metal layer. The main body has a first main surface and a second main surface. The metal layer is arranged on the first main surface of the main body. The metal layer includes at least one concave recognition mark having an inclined surface that is inclined with respect to a main surface of the metal layer.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.

Abstract: An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.

Abstract: An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.

Abstract: A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.

Abstract: A wiring substrate includes a coil wiring and a magnetic layer that is in contact with a lower surface of the coil wiring and includes an opening extending through in a thickness-wise direction. The wiring substrate further includes a first insulation layer covering the coil wiring, an upper surface of the magnetic layer, and a wall surface of the opening and a signal wiring structure formed so that a signal of a semiconductor element, when mounted on the wiring substrate, travels through the opening of the magnetic layer. The signal wiring structure includes a first wiring portion located on an upper surface of the first insulation layer and a first via wiring located inward from the opening of the magnetic layer and connected to the first wiring portion. The magnetic layer is not in contact with the signal wiring structure.

Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

Abstract: A fan-out semiconductor package includes a wiring portion, semiconductor chips, a dummy chip, and an encapsulant. The wiring portion includes an insulating layer, conductive patterns formed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns. The semiconductor chips are disposed on one region of the wiring portion, and the dummy chip is disposed on another region thereof and has a thickness smaller than those of the semiconductor chips. The encapsulant encapsulates at least portions of the semiconductor chips and the dummy chip. An upper surface of the wiring portion is disposed below a center line of the fan-out semiconductor package, and the thickness t of the dummy chip is such that T/2?t?3T/2 in which T is a distance from the upper surface of the wiring portion to the center line of the fan-out semiconductor package.

Abstract: Provided are a test socket for a semiconductor device and a test device including the test socket. The test device includes a test socket including terminals arranged in a two-dimensional array and corresponding to terminals of the semiconductor device and a ground line extending along at least one row of two-dimensional array; and a substrate electrically connected to the test socket so as to transmit and receive a test signal. The test socket includes a ground line extending along at least one row of the two-dimensional array.

Abstract: A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.

Abstract: A semiconductor device package includes a lower redistribution structure, an upper encapsulated semiconductor device and an upper redistribution structure. The lower redistribution structure includes a first dielectric layer, a RDL, a second dielectric layer, and a second RDL. The first RDL is disposed on the first dielectric layer and includes a circuit portion and an alignment mark portion insulated from the circuit portion. The second dielectric layer is disposed on the first RDL, wherein the second dielectric layer covers the alignment mark portion. The second RDL is disposed on the second dielectric layer and electrically connected to the first RDL. The upper encapsulated semiconductor device is disposed on the lower redistribution structure. The upper redistribution structure is disposed on the upper encapsulated semiconductor device.

Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.

Abstract: The present invention generally provides a novel method for manufacturing an electronic module with crossed conducting lines and a novel electronic module with crossed conducting lines. In particular, an aspect of the present invention is to provide a thin, single layer electronic module. It is also an object of the present invention to provide an electronic module with an embedded jumper element having reliable high quality connections and contacts. To achieve at least some of the aspects of the present invention, an embedded pre-fabricated jumper module is placed inside a printed circuit board which allows the crossing of conducting lines within the module without manufacturing additional layers over the whole PCB board. The resultant PCB will have improved contacts and will not have surface deformation.

Abstract: A semiconductor package includes a metal baseplate having a die attach region and a peripheral region, a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate. The multilayer circuit board includes two embedded electrically conductive layers that are separated from the first and second sides by layers of composite fiber, and an embedded dielectric layer disposed between the two embedded electrically conductive layers. The embedded dielectric layer has a higher dielectric constant than the layers of composite fiber.

Abstract: A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible substrate. A circuit layer of the flexible substrate includes a plurality of first upper leads, second upper leads, first conductive vias and lower leads. The second upper leads are disposed in the chip mounting area and divided into groups, and each second upper lead has a second inner end and an upper pad opposite to each other. The upper pads of each group are arranged layer by layer into at least two rows. There are two upper pads symmetrically arranged on both sides of a reference line of each group on at least one row furthest from the second inner ends. The first conductive vias connect the upper pads and the lower leads. The chip is mounted in the chip mounting area.

Abstract: The present disclosure relates to a ring-frame power package that includes a thermal carrier, a spacer ring residing on the thermal carrier, and a ring structure residing on the spacer ring. The ring structure includes a ring body and a number of interconnect tabs that protrude from an outer periphery of the ring body. Herein, a portion of the carrier surface of the thermal carrier is exposed through an interior opening of the spacer ring and an interior opening of the ring body. The spacer ring is not electronically conductive and prevents the interconnect tabs from electrically coupling to the thermal carrier. Each interconnect tab includes a top plated area and a bottom plated area, which is electrically coupled to the top plated area.

Abstract: According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.

Abstract: A method for bonding thin chips to a target substrate is described herein. According to an example method, an adhesive tape is provided with thinned chips attached thereto. The chips are transferred to a carrier substrate by one or more tape-to-tape transfer steps. The carrier is then diced into separate carrier-and-chip assemblies, which can be handled by existing tools designed for handling chips of regular thickness. The fact that the thinning step is separate from the carrier attachment may lead to reduced thickness variation of the chips. The use of tape-to-tape transfer steps allows for attaching either the front or the back side of the chips to the carrier. The use of an individual carrier per chip allows for treating the thinned chip as if it were a standard chip.

Abstract: A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first die, at least one through integrated fan-out via and a molding layer. The at least one through integrated fan-out via is aside the first die and includes a seed layer and a metal layer. The molding layer encapsulates the at least one through integrated fan-out via and the first die. Besides, the seed layer surrounds a sidewall of the metal layer and is between the metal layer and the molding layer.

Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

Abstract: The present disclosure relates to a method of integrating a interposer device with a textile layer, wherein the interposer device is a stretchable interposer device comprising a stretchable electrically conductive structure with at least one contact pad for establishing at least one electrically conductive path towards the textile layer. The interposer device is arranged to be mechanically attached to a textile layer comprising a plurality of yarns, at least one of which is an electrically conductive yarn. An electrical connection is established between the at least one conductive yarn of the textile layer and the at least one contact pad, which electrical connection is established after the interposer device has been mechanically attached to the textile layer.

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

Abstract: A display device includes: a display panel driven to display an image, the display panel including a substrate including a display area at which the image is displayed; a terminal pad on the substrate and through which a driving signal is applied to the display area; a driving chip through which the driving signal is applied to the terminal pad; and a non-conductive film which fixes the driving chip to the substrate. The driving chip includes: a non-conductive elastic support body projected from a surface of the driving chip; a bump wiring on the non-conductive elastic support body, the bump wiring directly contacting the terminal pad to apply the driving signal to the terminal pad; and a dispersed particle on the non-conductive elastic support body.

Abstract: A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings. Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided.

Abstract: A printed wiring board includes a resin insulating layer, a wiring conductor layer embedded in the insulating layer such that the wiring layer has first surface exposed from the insulating layer, and a conductor post formed in the insulating layer and on second surface of the wiring layer on the opposite side with respect to the first surface of the wiring layer such that the conductor post has side surface covered by the insulating layer and end surface exposed from the insulating layer on the opposite side with respect to the wiring layer. The conductor post is formed such that the side surface of the conductor post is a roughened side surface having surface roughness of first roughness R1, the end surface of the conductor post is a roughened end surface having surface roughness of second roughness R2, and the first and second roughnesses R1, R2 satisfy R1>R2.

Abstract: A semiconductor die includes an III-V semiconductor body having a periphery devoid of active devices, the periphery terminating at an edge face of the semiconductor die. The semiconductor die further includes a seal ring structure above the periphery of the III-V semiconductor body and a barrier. The barrier is disposed over the periphery of the III-V semiconductor body at least between the seal ring structure and the edge face of the semiconductor die. The barrier has a density which prevents water, water ions, sodium ions and potassium ions from diffusing through the barrier.

Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package.

Abstract: An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body. The second conductive line is embedded in the main body. The protrusion pad is disposed on the first conductive line. The protrusion pad protrudes from the main body and is configured to be in electrical contact with a solder portion of a semiconductor chip. A first spacing between the protrusion pad and the second conductive line is determined in accordance with a process deviation of the protrusion pad by the width of the protrusion pad and the width of the first conductive line. Moreover, a semiconductor package having the IC packaging substrate and a manufacturing method of the semiconductor package are also provided.

Abstract: A memory slot filler for a computer is provided. The slot filler can be used in place of a memory module in a computer system. The slot filler includes at least some exterior dimensions that are smaller than the corresponding exterior dimensions of a memory module.

Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.

Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.

Abstract: The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.

Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.

Abstract: Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer.

Abstract: A combined wiring board includes a metal frame having multiple opening portions, and multiple wiring boards accommodated in the opening portions in the metal frame, respectively. The opening portions in the metal frame have side walls having holding portions such that the holding portions hold the wiring boards in the opening portions in the metal frame, and the metal frame has slit portions adjacent to the holding portions and connecting portions connecting the slit portions to the opening portions.

Abstract: One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer.

Abstract: A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30) encapsulating the semiconductor chip (1), and lead terminals (21) electrically connected to the semiconductor chip (1) and including inner lead portion (21b) covered with the resin-encapsulating layer (30). The lead terminals (21) are made of copper or a copper alloy. The die pad (10) is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals (21).