Abstract: Methods and apparatus for producing fine pitch patterning on a substrate. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2/2 ?m l/s fine pitch patterning.

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.

Abstract: A display device including a display panel having a plurality of signal wirings disposed on a side surface, each of the signal wirings including a first surface and a second surface different from the first surface; and a printed circuit board attached to the side surface of the display panel and including a base film and a plurality of lead wirings disposed on one surface of the base film. Each of the lead wirings includes a first lead portion and a second lead portion having a thickness less than that of the first lead portion. The first lead portion is bonded to the second surface, and the second lead portion is bonded to the first surface.

Abstract: There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.

Abstract: A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

Abstract: A method of connecting a plurality of electronic components to a flexible circuit board comprises: providing a carrier substrate carrying the electronic components, each of the electronic components having at least one electrical contact coated with electrically conductive adhesive; and applying the carrier substrate to the flexible circuit board such that the electronic components are adhered to the flexible circuit board in electrical contact therewith via the conductive adhesive. The electronic components may comprise LEDs and there may be provided one or more optical layers over the flexible circuit board.

Abstract: A semiconductor device includes a substrate, a semiconductor chip, and a sealing member. The semiconductor chip is disposed on the substrate. The semiconductor chip includes a first principal surface on a side of the substrate and a second principal surface on a side opposite to the first principal surface. The sealing member seals the semiconductor chip. The sealing member includes a first sealing member and a second sealing member. The second sealing member faces at least a part of the second principal surface. A permittivity of the second sealing member is lower than a permittivity of the first sealing member.

Abstract: A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.

Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.

Abstract: An electrical connector electrically connects a first printed circuit board and a second printed circuit board, where the electrical connector includes: (a) an insulative housing; (b) a plurality of signal conductors, with at least a portion of each of the plurality of signal conductors disposed within the insulative housing; (c) each of the plurality of signal conductors having a first contact end, a second contact end and an intermediate portion therebetween; and (d) a passive circuit element electrically connected to the intermediate portion of each of the plurality of signal conductors, where the passive circuit element is housed in an insulative package and includes at least a capacitor or an inductor.

Abstract: A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.

Abstract: A package structure is provided. The package structure includes a leadframe including a first portion and a second portion. The first portion includes a first base part and a plurality of first extended parts connected to the first base part. The second portion includes a second base part and a plurality of second extended parts connected to the second base part. The first extended parts and the second extended parts are arranged in such a way that they alternate with each other. In the package structure, a chip is disposed on a part of the first extended parts of the first portion and the second extended parts of the second portion of the leadframe. The package structure further includes a plurality of protrusions, opposite to the chip, disposed on the first extended parts and the second extended parts.

Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.

Abstract: A display apparatus includes a display panel which have first display pads arranged in a first direction, a main circuit board, a first flexible circuit board which includes first substrate pads connected to the main circuit board and the first display pads and a first driving chip connected to the first substrate pads, and is bent in a direction toward a back surface of the display panel, and a protective member disposed on the first flexible circuit board. The protective member covers the first driving chip.

Abstract: The invention discloses a fan-out multi-device hybrid integrated flexible micro-system and an associated fabrication method in the field of microelectronics. The flexible microsystem uses microelectromechanical system (MEMS) chips and/or integrated circuit (IC) chips as the device units, flexible isolation trenches filled with flexible polymer as a flexible connection between the device units, and metal wiring layers to provide electrical interconnections between the device units. The disclosed multi-device hybrid integrated flexible micro-system completed by a fan-out method not only retains excellent electrical performance of silicon-based devices, but also realizes flexibility of the overall micro-system, and has stable structure and reliable performance.

Abstract: Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.

Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

Abstract: A packaged integrated circuit device includes a frame having a cavity therein and an inner semiconductor chip within the cavity. A lower re-distribution layer is provided, which extends adjacent lower surfaces of the frame and the inner semiconductor chip. The lower re-distribution layer has an opening therein which at least partially exposes the lower surface of the inner semiconductor chip. A lower semiconductor chip is provided, which extends adjacent the lower surface of the inner semiconductor chip, and within the opening in the lower re-distribution layer. This lower re-distribution layer includes: (i) an insulating layer covering the lower surface of the frame, (ii) a re-distribution pattern disposed on the insulating layer, and (iii) a barrier layer, which is disposed on the insulating layer and surrounds at least a portion of the lower semiconductor chip.

Abstract: A circuit carrier for holding at least one electrical power component is disclosed. The circuit carrier including a heat sink for holding and for cooling the power component. The heat sink having a surface. The circuit carrier includes a copper layer for mechanically connecting the heat sink to at least one copper plate, where the copper layer includes copper or a copper alloy and is cold-gas-sprayed or sintered on the surface of the heat sink. The circuit carrier also includes at least one copper plate for mechanically and electrically connecting the power component to the copper layer. The copper plate includes copper or a copper alloy and is arranged directly on a surface of the copper layer facing away from the heat sink and is areally, mechanically and electrically conductively connected to the copper layer.

Abstract: A printed wiring board includes a first insulator, a second insulator, a first conductor, and a second conductor. The first conductor is between the first insulator and the second insulator. The first conductor contains a first conductive material. The second conductor includes a first portion. The first portion is between the first insulator and the first conductor. The first portion is in contact with the first conductor and extends along the first conductor. The second conductor contains a second conductive material. The second conductive material is lower in electrical resistivity than the first conductive material. The second insulator is closer to an outside of the printed wiring board than the first insulator is in a thickness direction of the printed wiring board.

Abstract: The present disclosure relates to an optical module, including: a carrier, a emitter, a detector and an encapsulant. The carrier has a first surface. The emitter is disposed above the first surface. The detector is disposed above the first surface. The encapsulant is disposed on the first surface and exposes at least a portion of the emitter.

Abstract: A package structure includes a first RDL structure, a die, an encapsulant, a film, a TIV and a second RDL structure. The die is located over the first RDL structure. The encapsulant laterally encapsulates sidewalls of the die. The film is disposed between the die and the first RDL structure, and between the encapsulant and the first RDL structure. The TIV penetrates through the encapsulant and the film to connect to the first RDL structure. The second RDL structure is disposed on the die, the TIV and the encapsulant and electrically connected to die and the TIV.

Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

Abstract: The present disclosure provides a fan-out antenna packaging structure and a preparation method thereof. The fan-out antenna packaging structure comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip, a via being formed in the plastic packaging material layer; a conductive pole located in the via and running through the plastic packaging material layer from top to bottom; an antenna structure located on a first surface of the plastic packaging material layer and electrically connected with the conductive pole; a redistribution layer located on a second surface of the plastic packaging material layer and electrically connected with the semiconductor chip and the conductive pole; and a solder bump located on a surface of the redistribution layer, electrically connected with the redistribution layer and insulated from the plastic packaging material layer.

Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

Abstract: A semiconductor structure includes a substrate, a chip, a first edge pad, a first central pad, a second edge pad, and a second central pad. The substrate has a first surface and a conductive trace extending above the substrate. The chip is above the first surface of the substrate, and has a sidewall, a central area, and an edge area. The first edge pad is on the edge area. The first central pad is on the central area and electrically connected to the first edge pad. The second edge pad is on the edge area of the chip. A distance between the first edge pad and the sidewall of the chip is substantially smaller than a distance between the second edge pad and the sidewall of the chip. The second central pad is on the central area of the chip and electrically connected to the second edge pad.

Abstract: A method includes attaching a voltage regulator to a first redistribution structure of a first package. A second redistribution structure is formed over the voltage regulator, the voltage regulator being embedded in the second redistribution structure. The first substrate is attached to the second redistribution structure to form a second package including the first package. A first voltage may be provided to the second redistribution structure and through the second redistribution structure to the voltage regulator. The voltage regulator regulates the first voltage into a second voltage and provides the second voltage through the first redistribution structure to a first device die, where an output of the voltage regulator is attached directly to the first redistribution structure.

Abstract: A semiconductor module includes a laminated substrate that includes a heat radiating plate, and an insulation layer having a conductive pattern thereof and being disposed on a top surface of the heat radiating plate, a semiconductor element disposed on a top surface of the conductive pattern, an integrated circuit that controls driving of the semiconductor element, a control-side lead frame having a primary surface on which the integrated circuit is disposed, and a mold resin that seals the laminated substrate, the semiconductor element, the integrated circuit, and the control-side lead frame. The control-side lead frame has a rod-shaped first pin having a first end, a first end side of the first pin extending toward the top surface of the heat radiating plate, and the heat radiating plate has at least one insertion hole into one of which the first end of the first pin is press-fitted.

Abstract: Provided is a circuit board supporting structure capable of easily detaching a circuit board on a base. The circuit board supporting structure is configured to support a circuit board on a base, in which the base has a concave portion formed in a placement surface of the circuit board, and a rotational operation member configured to be rotatably accommodated in the concave portion and extend and retract in a direction perpendicular to the placement surface by a rotational operation, in which the circuit board has a through hole formed at a position corresponding to the concave portion, in which the rotational operation member has a reference surface formed approximately in parallel with the placement surface, and an operation portion formed on a rotational axis of the rotational operation member so as to be exposed from the through hole.

Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.

Abstract: The semiconductor device includes a substrate having a main surface, a plurality of conductive patterns provided on the main surface, a plurality of switching elements disposed on one of the conductive patterns, each switching element having a first electrode and a second electrode and being connected to the one of the conductive patterns through its first or second electrode, and at least one first wiring member each directly connecting the first electrodes of two switching elements that are respectively disposed on different conductive patterns and are electrically connected in parallel.

Abstract: An antenna module includes an antenna substrate, a fan-out package and first electrical connection structures. The antenna substrate includes a pattern layer including antenna and ground patterns, and a feeding layer under the pattern layer including a feeding network that supplies power to the antenna patterns. The fan-out package is under the antenna substrate and includes a semiconductor chip driving the antenna substrate, an encapsulant encapsulating some of the semiconductor chip, a first redistribution layer on the semiconductor chip electrically connecting the semiconductor chip with the antenna substrate, and a second redistribution layer under the semiconductor chip electrically connecting the semiconductor chip with external devices. The first electrical connection structures are between and electrically connect the antenna substrate and the fan-out package.

Abstract: In one example, a semiconductor device comprises a main substrate having a top side and a bottom side, a first electronic component on the top side of the main substrate, a second electronic component on the bottom side of the main substrate, a substrate structure on the bottom side of the main substrate adjacent to the second electronic component, and an encapsulant structure comprising an encapsulant top portion on the top side of the main substrate and contacting a side of the first electronic component, and an encapsulant bottom portion on the bottom side of the main substrate and contacting a side of the second electronic component and a side of the substrate structure. Other examples and related methods are also disclosed herein.

Abstract: A package structure includes a redistribution layer (RDL) structure, a die, and an encapsulant. The die is attached to the RDL structure through an adhesive layer. The encapsulant is disposed on the RDL structure and laterally encapsulates the die and the adhesive layer. The encapsulant includes a protruding part extending into the RDL structure and having a bottom surface in contact with the RDL structure.

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.

Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a flexible substrate, a driving circuit, and a memory. The substrate has a first surface and a second surface opposite to each other, and the first surface has a display region and a bonding region. The display unit is disposed on the display region of the first surface. The flexible substrate is disposed below the second surface and has a connection portion extended to the bonding region of the first surface. The driving circuit is disposed on the flexible substrate and electrically connects with the display unit. The memory is disposed on the flexible substrate and electrically connects with the driving circuit.

Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.

Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

Abstract: Disclosed are a display module and a display device. The display module includes a display panel having a light emitting surface and a back surface opposite to the light emitting surface; a drive circuit board disposed adjacent to an edge at a side of the display panel, and a wiring gap is formed between the drive circuit board and the display panel; a chip-on-film, a first connecting end of which is disposed on the light emitting surface and connected to the display panel, and a second connecting end of which passes through the wiring gap and extends to the back surface of the display panel; and an adapter structure disposed on a side of the second connecting end of the chip-on-film facing away from the display panel, connected between the chip-on-film and the drive circuit board.

Abstract: A chip on film package includes; a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: A manufacturing method for an organic electronic device according to a mode includes a device substrate manufacturing step S01 of manufacturing a device substrate 12 in which a first electrode layer 18, a device function portion 20 including an organic layer, and a second electrode layer 22 are sequentially laminated in each of a plurality of device formation regions DA virtually set in a flexible support substrate 16 and having at least one corner, a bonding step S02 of bonding a sealing member 14 including a sealing base 24 and an adhesive layer 26 laminated on the sealing base to a side of the second electrode layer of the device substrate via the adhesive layer such that the sealing member is not disposed at corners c1 to c4 of the device formation region, and a dicing step S03 of dicing the device substrate, to which the sealing member is bonded, for each of the device formation regions to obtain an organic electronic device 10.

Abstract: A method includes encapsulating a plurality of package components in an encapsulant, and forming a first plurality of redistribution layers over and electrically coupling to the plurality of package components. The first plurality of redistribution layers have a plurality of power/ground pad stacks, with each of the plurality of power/ground pad stacks having a pad in each of the first plurality of redistribution layers. The plurality of power/ground pad stacks include a plurality of power pad stacks, and a plurality of ground pad stacks. At least one second redistribution layer is formed over the first plurality of redistribution layers. The second redistribution layer(s) include power lines and electrical grounding lines electrically connecting to the plurality of power/ground pad stacks.

Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.

Abstract: A semiconductor device includes a semiconductor module having a heat conductive portion formed of metal and also having a molded resin having a surface at which the heat conductive portion is exposed, a cooling body secured to the semiconductor module by means of bonding material, and heat conductive material formed between and thermally coupling the heat conductive portion and the cooling body.

Abstract: A substrate having an electronic component embedded therein includes a core structure including a first insulating body and first wiring layers and having a cavity, an electronic component embedded in the cavity, a build-up structure including a second insulating body, covering at least a portion of each of the core structure and the electronic component and filling a portion of the cavity, and second wiring layers, a first passivation layer disposed on a side of the core structure opposing a side of the core structure on which the build-up structure is disposed, and a second passivation layer disposed on a side of the build-up structure opposing a side of the build-up structure on which the core structure is disposed, wherein the first and second passivation layers include different types of materials.

Abstract: A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

Abstract: LED assemblies and related LED light bulbs. An LED assembly has a flexible, transparent substrate, an LED chip on the first surface and electrically connected to two adjacent conductive sections, a first wavelength conversion layer, formed on the first surface to substantially cover the LED chip, and a second wavelength conversion layer formed on the second surface. The flexible, transparent substrate has first and second surfaces opposite to each other, and several conductive sections, which are separately formed on the first surface.