On Insulating Carrier Other Than A Printed Circuit Board Patents (Class 257/668)
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Publication number: 20140117519Abstract: The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.Type: ApplicationFiled: January 7, 2014Publication date: May 1, 2014Applicant: ROHM CO., LTD.Inventor: Kunihiro KOMIYA
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Patent number: 8710669Abstract: A semiconductor device includes a core substrate, and at least one insulating layer and at least one wiring layer that are disposed on a first surface and a second, opposite surface of the substrate. The semiconductor device includes a via disposed in the insulating layer and in the core substrate, and which connects the wiring layers to one another. The semiconductor device includes a semiconductor element mounted on the first surface, forming an electrode terminal that faces up. The semiconductor device includes a connecting portion that penetrates the insulating layer and directly connects the electrode terminal of the semiconductor element and the wiring layer on the first surface. A minimum wiring pitch of this wiring that of any wiring layer on the second surface.Type: GrantFiled: May 18, 2010Date of Patent: April 29, 2014Assignee: NEC CorporationInventors: Kentaro Mori, Yoshiki Nakashima, Daisuke Ohshima, Katsumi Kikuchi, Shintaro Yamamichi
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Patent number: 8710681Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: GrantFiled: May 31, 2012Date of Patent: April 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Publication number: 20140103503Abstract: A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.Type: ApplicationFiled: December 23, 2013Publication date: April 17, 2014Applicant: STATS ChipPAC, Ltd.Inventors: JaeHyun Lee, KiYoun Jang, KyungHoon Lee, TaeWoo Lee
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Publication number: 20140103504Abstract: A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.Type: ApplicationFiled: December 27, 2013Publication date: April 17, 2014Applicant: Panasonic CorporationInventors: HIROKI YAMASHITA, TAKASHI YUI, TAKESHI KAWABATA, KIYOMI HAGIHARA, KENJI YOKOYAMA
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Patent number: 8698303Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.Type: GrantFiled: September 30, 2011Date of Patent: April 15, 2014Assignee: Ibiden Co., Ltd.Inventors: Toshiki Furutani, Daiki Komatsu, Masatoshi Kunieda, Naomi Fujita, Nobuya Takahashi
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Patent number: 8698311Abstract: A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.Type: GrantFiled: August 30, 2012Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Gyu Kang, Ho-Tae Jin, Tae-ho Moon, Il-soo Choi, Jong-Eun Lee
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Patent number: 8698288Abstract: A semiconductor device includes first and second flexible substrates each with first and second peripheral edges. First and second dies are attached on respective surfaces of the flexible substrates and are each respectively electrically connected to first and second metal traces. A first crimping structure electrically connects the first metal traces to the second metal traces and crimps together the first peripheral edges of the first and second substrates. A second crimping structure electrically connects the first metal traces to the second metal traces and crimps together the second peripheral edges of the first and second substrates.Type: GrantFiled: May 23, 2013Date of Patent: April 15, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Boon Yew Low, Navas Khan Oratti Kalandar, Sharon Huey Lin Tay
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Publication number: 20140097525Abstract: Provided is a circuit board, which may include a base layer, an adhesive film, a conductive circuit, and a through via. The adhesive film and the conductive circuit may be provided in plurality to be alternately stacked on the base layer. The through via may be formed through soldering. Since the base layer is not damaged during the soldering, the through via may include various conductive materials. The through via makes it possible to easily connect the conductive circuits having different functions to one another. Accordingly, the circuit board may have multi functions. Thicknesses of the conductive circuits may be adjusted to protect the conductive circuits from folding or bending of the base layer. The circuit board having a multi-layered structure can function not only as a fabric or clothes but also as an electronic circuit.Type: ApplicationFiled: March 7, 2013Publication date: April 10, 2014Applicant: Electronics and Telecommunications Research InstituteInventor: Electronics and Telecommunications Research Institute
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Patent number: 8686566Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.Type: GrantFiled: June 30, 2011Date of Patent: April 1, 2014Assignee: Intel CorporationInventors: Mihir K. Roy, Matthew J. Manusharow
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Publication number: 20140084430Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.Type: ApplicationFiled: October 24, 2013Publication date: March 27, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Sang Cho, Chang-Sig Kang, Dae-Woo Son, Yun-Seok Choi, Kyong-Soon Cho, Sang-Heui Lee
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Patent number: 8664752Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: March 26, 2012Date of Patent: March 4, 2014Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Patent number: 8659145Abstract: A semiconductor device in which a flip chip is mounted which can change a potential of a specific terminal without changing a design of a package external. The semiconductor device includes an IC chip having a bump for an external terminal, and a package in which the IC chip is mounted. The package includes an inner lead portion that supplies a first signal or a second signal to the external terminal. The inner lead portion has a pattern of an inner lead that can change a signal to be supplied to the external terminal to the first signal or the second signal according to a position at which the IC chip is mounted.Type: GrantFiled: July 27, 2012Date of Patent: February 25, 2014Assignee: Renesas Electronics CorporationInventor: Azuma Araya
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Patent number: 8653669Abstract: A semiconductor package including a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads.Type: GrantFiled: April 10, 2013Date of Patent: February 18, 2014Assignee: Lapis Semiconductor Co., Ltd.Inventor: Tae Yamane
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Publication number: 20140042601Abstract: One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region and the power traces are located in a wafer level fan out (WLFO) region located lateral the IC device region. This embodiment further comprises a first IC device located on a first side of the substrate within the IC device region and that contacts the signal traces in the IC device region. A second IC device is located on a second side of the substrate opposite the first side and overlaps the IC device region and the WLFO region. The second IC device contacts a first portion of the signal traces in the IC device region and contacts a first portion of the power traces in the WLFO region.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Applicant: LSI CorporationInventor: Donald E. Hawk
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Publication number: 20140042602Abstract: A wiring board includes a substrate having a cavity, and an electronic component accommodated in the cavity of the substrate. The substrate has a thickness which is greater than a thickness of the electronic component such that a ratio of the thickness of the substrate to the thickness of the electronic component is set in a range of 0.3 or greater and 0.7 or less.Type: ApplicationFiled: August 9, 2013Publication date: February 13, 2014Applicant: IBIDEN CO., LTD.Inventors: Toyotaka SHIMABE, Keisuke SHIMIZU, Toshiki FURUTANI
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Patent number: 8643154Abstract: A semiconductor mounting device including a first substrate having first insulation layers, first conductor layers formed on the first insulation layers and via conductors connecting the first conductor layers, a second substrate having a core substrate, second conductor layers, through-hole conductors and buildup layers having second insulation layers and third conductor layers, first bumps connecting the first and second substrates and formed on the outermost first conductor layer on the outermost first insulation layer, and second bumps positioned to connect a semiconductor element and formed on the outermost third conductor layer on the outermost second insulation layer.Type: GrantFiled: November 22, 2011Date of Patent: February 4, 2014Assignee: Ibiden Co., Ltd.Inventors: Hiroyuki Watanabe, Masahiro Kaneko
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Patent number: 8642408Abstract: A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer.Type: GrantFiled: October 7, 2010Date of Patent: February 4, 2014Assignee: Infineon Technologies AGInventors: Ralf Otremba, Joachim Mahler, Bernd Rakow, Reimund Engl, Rupert Fischer
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Patent number: 8643155Abstract: A chip on film (COF) is disclosed in the present disclosure, which comprises an adhesive base layer, a driving integrated circuit (IC), an adhesive layer and a copper layer. The driving IC is embedded on a surface of the adhesive base layer; the adhesive layer is located under the adhesive base layer; the copper layer is located under the adhesive layer. The adhesive base layer is formed with a heat and pressure spreading structure. A heat and pressure spreading structure is disposed on the adhesive base layer of the COF so that deformation or unevenness of the glass substrate in the bonded area can be avoided when the COF is thermally pressed to the glass substrate of the LCD. These guarantees the consistency between the bonded area and the unbounded area, the bonded area and the unbounded area of the glass substrate will have the same transmissivity and luminance.Type: GrantFiled: August 31, 2011Date of Patent: February 4, 2014Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventors: Liang-Chan Liao, Po-Shen Lin, Yu Wu
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Publication number: 20140027889Abstract: A reconstituted wafer level package for a versatile high-voltage capable component is disclosed. The reconstituted wafer package includes a dice substantially encapsulated by a mold material except for a first face. A dielectric layer is disposed on the first face of the dice. The package further includes an array of ball bumps formed on an exterior facing portion of the dielectric layer. Further, a field plate is disposed within the dielectric material and interposed between the first face of the dice and the ball bump array. The field plate may be spaced from the dice by a predetermined distance to prevent dielectric breakdown of the material of the dielectric layer.Type: ApplicationFiled: July 24, 2012Publication date: January 30, 2014Inventors: Mark R. Boone, Mohsen Askarinya, Larry E. Tyler
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Patent number: 8637964Abstract: A power module includes a substrate including an insulating member and a patterned metallization on the insulating member. The patterned metallization is segmented into a plurality of spaced apart metallization regions. Adjacent ones of the metallization regions are separated by a groove which extends through the patterned metallization to the insulating member. A first power transistor circuit includes a first power switch attached to a first one of the metallization regions and a second power switch attached to a second one of the metallization regions adjacent a first side of the first metallization region. A second power transistor circuit includes a third power switch attached to the first metallization region and a fourth power switch attached to a third one of the metallization regions adjacent a second side of the first metallization region which opposes the first side. The second power transistor circuit mirrors the first power transistor circuit.Type: GrantFiled: October 26, 2011Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Patrick Jones, Andre Christmann, Daniel Domes
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Patent number: 8629537Abstract: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.Type: GrantFiled: January 23, 2006Date of Patent: January 14, 2014Assignee: Stats Chippac Ltd.Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
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Patent number: 8629538Abstract: Disclosed herein is a power module package including: a first substrate having one surface and the other surface; a second substrate contacting one side of one surface of the first substrate; and a first lead frame contacting the other side of one surface of the first substrate. The power module package further includes: a first metal layer formed on one side of one surface of the first substrate; a first bonding layer formed on the first metal layer and contacting a lower surface of the second substrate; a second metal layer formed on the other side of one surface of the first substrate; and a second bonding layer formed on the second metal layer and contacting a lower surface of the first lead frame.Type: GrantFiled: December 9, 2011Date of Patent: January 14, 2014Assignee: Samsung Electro-Mechanics Co., LtdInventors: Young Ki Lee, Young Ho Sohn, Kwang Soo Kim, Chang Hyun Lim
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Patent number: 8624365Abstract: Some of the embodiments of the present disclosure provide a semiconductor package structure comprising a leadframe; an interposer disposed on the leadframe, the interposer comprising a plurality of dielectric layers including at least (i) a first dielectric layer and (ii) a second dielectric layer; a semiconductor device disposed on the interposer; and a capacitor that is embedded within the interposer, wherein the capacitor is formed using at least (i) a first conductive area disposed on the first dielectric layer and (ii) a second conductive area disposed on the second dielectric layer. Other embodiments are also described and claimed.Type: GrantFiled: July 14, 2011Date of Patent: January 7, 2014Assignee: Marvell International Ltd.Inventor: William B. Weiser
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Publication number: 20140001612Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsun Lee, Kai-Chiang Wu
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Publication number: 20130341775Abstract: A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns.Type: ApplicationFiled: August 23, 2013Publication date: December 26, 2013Applicant: Mitsubishi Electric CorporationInventors: Tatsuo Ota, Toshiaki Shinohara
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Patent number: 8614502Abstract: A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.Type: GrantFiled: April 26, 2012Date of Patent: December 24, 2013Assignee: Bridge Semiconductor CorporationInventors: Charles W.C. Lin, Chia-Chung Wang
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Patent number: 8610237Abstract: A semiconductor apparatus includes a semiconductor chip, a lead frame that has a first surface having the semiconductor chip mounted thereover and a second surface opposite to the first surface, a bonding wire that couples the semiconductor chip and the lead frame, and a high dielectric constant layer that is disposed over a surface of the lead frame opposite to a surface having the semiconductor chip mounted thereover and that has a relative permittivity of 5 or more. The lead frame includes a source electrode lead coupled to the source of a semiconductor device formed over the semiconductor chip and a source-wire junction at which the source electrode lead and the bonding wire are coupled together. The high dielectric layer is disposed in a region including at least a position corresponding to the source-wire junction over the second surface of the lead frame.Type: GrantFiled: July 19, 2012Date of Patent: December 17, 2013Assignee: Renesas Electronics CorporationInventor: Naoki Sakura
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Patent number: 8604595Abstract: An electronic component includes lead fingers and a die paddle. A tape pad is mounted below the lead fingers and the die paddle. A first semiconductor chip is bonded onto the tape pad by a layer of first adhesive and a second semiconductor chip is bonded onto the die paddle by a layer of second adhesive. Electrical contacts are disposed between the contact areas of the semiconductors chips and the lead fingers. An encapsulating compound covers part of the lead fingers, the tape pad, the semiconductor chips and the electrical contacts.Type: GrantFiled: August 14, 2008Date of Patent: December 10, 2013Assignee: Infineon Technologies AGInventors: Chee Chian Lim, May Ting Hng
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Patent number: 8598694Abstract: Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity.Type: GrantFiled: November 22, 2011Date of Patent: December 3, 2013Assignee: Infineon Technologies AGInventors: Khalil Hosseini, Joachim Mahler, Anton Prueckl
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Patent number: 8598692Abstract: A semiconductor device includes (i) a tape base material, (ii) a wiring pattern, (iii) a semiconductor element which is electrically connected with the wiring pattern, (iv) a top-side insulating protective film which covers a top surface of the tape base material and has an top-side opening section provided in a region where the top-side insulating protective film faces the semiconductor element, and (v) a reverse-side insulating protective film which covers a reverse surface of the tape base material and has a reverse-side opening section provided on a reverse side below the top-side opening section. The top-side insulating protective film has a protruding opening section extending outwardly from the region. An opening of the reverse-side opening section is 1.00 time to 8.50 times larger in an area than the region.Type: GrantFiled: February 17, 2012Date of Patent: December 3, 2013Assignee: Sharp Kabushiki KaishaInventor: Tomohiko Iwane
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Publication number: 20130313695Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.Type: ApplicationFiled: May 23, 2013Publication date: November 28, 2013Applicant: NICHIA CORPORATIONInventors: Takuya NOICHI, Yuichi OKADA
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Patent number: 8591756Abstract: A method of manufacturing a metallized ceramic substrate includes forming a metal layer on a ceramic substrate, and forming on the metal layer a resist having a first patterned resist opening and a second patterned resist opening for the metal layer to be exposed therefrom. A first width of the first patterned resist opening is greater than the thickness of the metal layer, and a second width of the second patterned resist opening is less than the thickness of the metal layer. A wet-etching process is conducted, to form in the first patterned resist opening a patterned metal layer opening and form in the second patterned resist opening a patterned metal layer dent. Therefore, an internal stress between the metal layer and the ceramic substrate is reduced, and the yield rate and reliability of the metallized ceramic substrate is increased.Type: GrantFiled: December 2, 2011Date of Patent: November 26, 2013Assignee: Viking Tech CorporationInventors: Shih-Long Wei, Shen-Li Hsiao, Chien-Hung Ho
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Patent number: 8580647Abstract: A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate.Type: GrantFiled: December 19, 2011Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Yu-Ling Lin
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Patent number: 8581372Abstract: According to one embodiment, a semiconductor storage device includes a plate and an external connection terminal. The plate is molded in a resin mold section. A semiconductor memory chip is placed on the plate. The external connection terminal is exposed to the outer circumferential surface of the semiconductor storage device. The plate includes a plurality of exposed portions exposed to the outer circumferential surface of the resin mold section. The plurality of exposed portions is electrically insulated from each other inside the resin mold section.Type: GrantFiled: March 18, 2011Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Asada, Taku Nishiyama, Atsuko Seki
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Patent number: 8581373Abstract: A tape package providing a plurality of input and output portions each having a minimum pitch. The tape package includes a tape wiring substrate including first and second wirings, and a semiconductor chip mounted on the tape wiring substrate, and including a first edge, a first pad disposed adjacent to the first edge, and a second pad disposed to be farther spaced apart from the first edge than the first pad, where the first wiring is connected to a portion of the first pad that is spaced from the first edge by a first distance, and where the second wiring is connected to a portion of the second pad that is spaced from the first edge by a second distance that is greater than the first distance.Type: GrantFiled: September 1, 2011Date of Patent: November 12, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Dong-han Kim, So-young Lim
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Patent number: 8581113Abstract: A low-cost high-frequency electronic device package and associated fabrication method are described wherein waveguide structures are formed from the high frequency device to the package lead transition. The package lead transition is optimized to take advantage of waveguide interconnect structure.Type: GrantFiled: December 19, 2007Date of Patent: November 12, 2013Assignee: Bridgewave Communications, Inc.Inventors: Eric A. Sanjuan, Sean S. Cahill
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Patent number: 8575734Abstract: A lead frame enabling simultaneous burn-in testing of plural LEDs while the LEDs are mounted thereon is disclosed. The lead frame according to embodiments of this disclosure may enable burn-in testing of LEDs before packaging.Type: GrantFiled: July 14, 2011Date of Patent: November 5, 2013Assignee: LG Innotek Co., Ltd.Inventor: KyungHo Shin
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Patent number: 8575746Abstract: A Chip on Flexible Printed Circuit (COF) type semiconductor package may include a flexible film, a semiconductor IC chip on the flexible film, and a heating pad on the flexible film.Type: GrantFiled: July 20, 2007Date of Patent: November 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Si-Hoon Lee, Sa-Yoon Kang, Kyoung-Sei Choi
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Patent number: 8570748Abstract: With respect to an electronic component, in particular a power module, and in a corresponding method for producing or contact-connecting said component, the component (1) is fastened to an electrically insulating carrier film (3) having at least one first inorganic material and at least one opening (5) in which at least one electrical contact-connection (7) of the component (1) to outside the component (1) is provided. This makes it possible to provide electronic components (1), in particular power modules, for a temperature range of >175 DEG C.Type: GrantFiled: June 16, 2009Date of Patent: October 29, 2013Assignee: Siemens AktiengesellschaftInventors: Friedrich Lupp, Karl Weidner
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Patent number: 8558359Abstract: Disclosed herein is a semiconductor package, including: a substrate having a first surface and a second surface; at least one semiconductor device formed on the first surface of the substrate; first lead frames respectively formed at both sides of the first surface of the substrate; and second lead frames respectively formed at both sides of the second surface of the substrate, wherein the first lead frame and the second lead frame are spaced apart from each other by an isolation distance base.Type: GrantFiled: January 17, 2012Date of Patent: October 15, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Chang Hyun Lim, Chang Jae Heo, Young Ki Lee, Sung Keun Park
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Patent number: 8558363Abstract: A lead frame substrate, includes: a metal plate having first and second surfaces; a semiconductor element mounting section, semiconductor element electrode connection terminals, and a first outer frame section formed on the first surface; external connection terminals formed on the second surface and electrically connected with the semiconductor element electrode connection terminals; a second outer frame section formed on the second surface; and a resin layer formed on a gap between the first outer frame and the second outer frame. Each external connection terminal buried in the resin layer has at least one projection formed on a side surface thereof throughout a side lower portion of the first surface.Type: GrantFiled: March 10, 2011Date of Patent: October 15, 2013Assignee: Toppan Printing Co., Ltd.Inventors: Takehito Tsukamoto, Susumu Maniwa, Junko Toda, Yasuhiro Sakai
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Patent number: 8546922Abstract: A wiring board including a core substrate made of an insulative material and having a penetrating portion, a first interlayer insulation layer formed on the surface of the core substrate, a first conductive circuit formed on the surface of the first interlayer insulation layer, a first via conductor formed in the first interlayer insulation layer, and an electronic component accommodated in the penetrating portion of the core substrate and including a semiconductor element, a bump body mounted on the semiconductor element, a conductive circuit connected to the bump body, an interlayer resin insulation layer formed on the conductive circuit, and a via conductor formed in the interlayer resin insulation layer. The first via conductor has a tapering direction which is opposite of a tapering direction of the via conductor in the electronic component.Type: GrantFiled: September 28, 2011Date of Patent: October 1, 2013Assignee: Ibiden Co., Ltd.Inventors: Toshiki Furutani, Daiki Komatsu, Nobuya Takahashi, Masatoshi Kunieda, Naomi Fujita, Koichi Tsunoda, Minetaka Oyama, Toshimasa Yano
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Patent number: 8546943Abstract: Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.Type: GrantFiled: August 30, 2010Date of Patent: October 1, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jung Hyun Park, Nam Keun Oh, Sang Duck Kim, Jong Gyu Choi, Young Ji Kim, Ji Eun Kim, Myung Sam Kang
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Patent number: 8546942Abstract: Disclosed is a flip-chip semiconductor device having isotropic electrical interconnection, primarily comprising a chip and a substrate. The chip has at least a first bump and a plurality of second bumps. The substrate has a plurality of bump pads disposed on the top surface and an isotropic connecting mechanism disposed inside the substrate consisting of a plurality of terminals electrically isolated from each other and a flexible vertical pad protruded from the top surface, wherein the disposition locations of the terminals circle around the flexible vertical pad as a disposition center. When the second bumps of the chip are bonded onto the corresponding bump pads, the first bump presses and bends the flexible vertical pad in a specific horizontal direction so that the flexible vertical pad selectively and electrically connect to a selected one of the terminals.Type: GrantFiled: April 18, 2012Date of Patent: October 1, 2013Assignee: Powertech Technology Inc.Inventor: Hian-Hang Mah
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Patent number: 8541886Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stacking carrier having a cavity; placing a base integrated circuit in the cavity, the base integrated circuit having a base interconnect facing the cavity; mounting a stack integrated circuit to the base integrated circuit; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier.Type: GrantFiled: March 9, 2010Date of Patent: September 24, 2013Assignee: STATS ChipPAC Ltd.Inventor: Chee Keong Chin
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Patent number: 8531014Abstract: A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier.Type: GrantFiled: September 27, 2010Date of Patent: September 10, 2013Assignee: Infineon Technologies AGInventors: Manfred Mengel, Oliver Eichinger, Khalil Hosseini, Joachim Mahler
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Publication number: 20130228905Abstract: A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallisation region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallisation region.Type: ApplicationFiled: April 18, 2013Publication date: September 5, 2013Applicant: Infineon Technologies Austria AGInventors: Carsten von Koblinski, Gerald Lackner, Karin Schrettlinger, Markus Ottowitz
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Patent number: 8525312Abstract: A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.Type: GrantFiled: August 12, 2011Date of Patent: September 3, 2013Assignee: Tessera, Inc.Inventors: Qwai H. Low, Chok J. Chia, Kishor Desai, Charles G. Woychik, Huailiang Wei
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Patent number: 8525341Abstract: Provided are a printed circuit board (PCB) and a semiconductor package including the same. The PCB includes a core layer having a stacked structure including at least a first layer made of a first material that has a first coefficient of thermal expansion (CTE) and a second layer made of a second material that has a second CTE different from the first CTE, an upper wiring layer disposed on a first surface of the core layer, and a lower wiring layer disposed on a second surface of the core layer opposite the first surface.Type: GrantFiled: September 22, 2011Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Ki Kim, Dae-Young Choi, Mi-Yeon Kim