With Stress Relief Patents (Class 257/669)
  • Patent number: 10290564
    Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: May 14, 2019
    Assignee: Intersil Americas LLC
    Inventor: Randolph Cruz
  • Patent number: 10276478
    Abstract: A lead frame includes an outer frame. The outer frame includes: an upper surface; a lower surface that is opposite to the upper surface; a side surface between the upper surface and the lower surface; a first recess that is formed to extend from the upper surface to the side surface; a second recess that is formed to extend from the lower surface to the side surface; and a curved surface that is positioned between the side surface and a side wall of the first recess or between the side surface and a side wall of the second recess.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 30, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kentaro Kaneko, Yoshio Furuhata, Mitsuharu Sato, Toshio Masuda
  • Patent number: 10267700
    Abstract: A high-precision pressure sensor, having a first base body that has two electrically conductive layers and an insulation layer arranged between the two layers and electrically insulating the two layers from one another, an electrically conductive measurement membrane arranged on the first base body with inclusion of a pressure chamber, which measurement membrane can be charged with a pressure to be measured, and an electrode provided in the membrane-facing layer and spaced apart from the measurement membrane, which electrode together with the measurement membrane forms a capacitor having a capacitance that varies according to the pressure acting upon the measurement membrane.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 23, 2019
    Assignee: ENDRESS+HAUSER SE+CO.KG
    Inventors: Rafael Teipen, Benjamin Lemke, Timo Kober, Lars Karweck, Stefan Rummele-Werner, Thomas Zieringer
  • Patent number: 10236268
    Abstract: Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising one or more metal pads, wherein the processing may comprise: forming a second metal contact on the one or more metal pads; forming a pillar on the second metal contact, and forming a solder bump on the second metal contact and the pillar, wherein the pillar extends into the solder bump. The second metal contact may comprise a stepped mushroom shaped bump, a sloped mushroom shaped bump, a cylindrical post, and/or a redistribution layer. The semiconductor wafer may comprise silicon. A solder brace layer may be formed around the second metal contact. The second metal contact may be tapered down to a smaller area at the one or more metal pads on the semiconductor wafer. A seed layer may be formed between the second metal contact and the one or more metal pads on the semiconductor wafer. The pillar may comprise copper.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: March 19, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Karthikeyan Dhandapani, Ahmer Syed, Sundeep Nand Nangalia
  • Patent number: 10211172
    Abstract: A surface mount device includes at least one semiconductor device including an exposed top metal, an encapsulation layer partially encapsulating the at least one semiconductor device, and at least one end-termination cap on the surface mount device resulting in an electrical connection from a first side of the surface mount device to a second side of the surface mount device. In implementations, one process for fabricating the surface mount device includes dicing a finished device wafer in a scribe-line region, applying tape to a first side of the finished device wafer, backgrinding a second side of the finished device wafer, encapsulating the second side of the finished device wafer with an encapsulation layer, singulating the finished device wafer, and forming at least one wrap-around connection from a first side of the surface mount device to a second side of the surface mount device.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 19, 2019
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Anuranjan Srivastava, Khanh Tran
  • Patent number: 10134654
    Abstract: One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The semiconductor chip is disposed in the module housing. A dielectric first encapsulation is disposed in the module housing, in physical contact with both the semiconductor chip and the substrate and has a first modulus of elasticity. A dielectric second encapsulation is disposed in the module housing and has a second modulus of elasticity. The first encapsulation is a polymer and disposed between the substrate and the second encapsulation. The semiconductor chip is disposed between the first encapsulation and the substrate. Further, the first modulus of elasticity is greater than the second modulus of elasticity.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans Hartung, Reinhold Bayerer
  • Patent number: 10121942
    Abstract: A package includes an element placement region, a pair of leads and a resin molded body. The resin molded body holds the pair of leads. The resin molded body includes a black resin part, and a light reflective foam part arranged at least on a part of a surface of the black resin part in a light irradiation region configured to be irradiated by light from a light emitting element placed in the element placement region.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: November 6, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Motokiyo Shirahama
  • Patent number: 10008444
    Abstract: A display device includes a display panel and a chip-on-film (COF) bonded to the display panel. The chip-on-film includes a film on which a driving chip is mounted, a plurality of film lines on the film, and at least one dummy pattern on the film between an adjacent pair of films in the plurality of film lines.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 26, 2018
    Assignee: LG Display Co., Ltd.
    Inventor: Hyungseok Seo
  • Patent number: 9997589
    Abstract: A display device according to the invention includes: a first substrate that includes a flexible substrate, is segmented into a display area and a non-display area outside the display area, and includes a thin film transistor and an electroluminescent light-emitting element formed on the display area of the flexible substrate; and an IC chip that is bonded on the non-display area of the first substrate via an anisotropic conductive film, wherein the first substrate includes, between the flexible substrate and the anisotropic conductive film, at least one or more support layers whose plan view shape is larger than that of the IC chip and whose hardness is higher than that of the flexible substrate, and the IC chip is located inside the at least one or more support layers in a plan view.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 12, 2018
    Assignee: Japan Display Inc.
    Inventor: Kazuto Tsuruoka
  • Patent number: 9984971
    Abstract: Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chuan Tseng, Chia-Wei Liu, Fang-Ting Kuo, Ren-Wei Xiao
  • Patent number: 9905515
    Abstract: The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: February 27, 2018
    Assignee: MediaTek Inc.
    Inventors: Chin-Chiang Chang, Tao Cheng
  • Patent number: 9831143
    Abstract: A leadframe and air cavity packages formed using the leadframe are described. Using the leadframe, several air cavity packages can be quickly formed at one time. Further, electrical components can be placed within and interconnected with the air cavity packages easily by repositioning several devices at a time using the leadframe. After assembly, the air cavity packages can be separated from the leadframe. The air cavity packages can include a slug, a plastic frame that surrounds the slug and forms an air cavity, and a cover that encloses the air cavity. The air cavity package further includes one or more conductive leads of the leadframe that extend through the plastic frame and are exposed within the air cavity. The conductive leads can be relied upon to bond out components secured within the air cavity. Finally, the cover can be secured to enclose the air cavity.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: November 28, 2017
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventor: Quinn Don Martin
  • Patent number: 9763334
    Abstract: Heat-assisted wiring traces and a conductive support substrate are respectively formed on first and second surfaces of an insulating layer. Further, connection terminals electrically insulated from the support substrate and electrically respectively connected to the heat-assisted wiring traces are formed on the second surface of the insulating layer. Each connection terminal has an element connection portion, a pattern connection portion and a spread blocking portion. When a circuit element is connected to the element connection portion of the connection terminal by solder, spreading of a molten solder applied to the element connection portion to the pattern connection portion is blocked by the spread blocking portion.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: September 12, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Terukazu Ihara, Naohiro Terada
  • Patent number: 9706643
    Abstract: An electronic device according to the present disclosure includes a component, an electrode placed on the component, a conductor which includes a first conductor section, including an electrode contact surface in contact with the electrode, and two second conductor sections, electrically connected to two respective facing edges of the first conductor section to extend in respective directions away from the electrode and including respective inclined surfaces inclined in directions toward a central axis passing through a center of the electrode and perpendicular to the surface of the electrode, an insulator which is in contact with the two second conductor sections from sides opposite to the central axis and encloses the conductor and the electrode, and a case housing the component, the electrode, the conductor, and the insulator. A space without the insulator is defined between the two second conductor sections.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: July 11, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tomoko Iwama
  • Patent number: 9660007
    Abstract: A display device according to the invention includes: a first substrate that includes a flexible substrate, is segmented into a display area and a non-display area outside the display area, and includes a thin film transistor and an electroluminescent light-emitting element formed on the display area of the flexible substrate; and an IC chip that is bonded on the non-display area of the first substrate via an anisotropic conductive film, wherein the first substrate includes, between the flexible substrate and the anisotropic conductive film, at least one or more support layers whose plan view shape is larger than that of the IC chip and whose hardness is higher than that of the flexible substrate, and the IC chip is located inside the at least one or more support layers in a plan view.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: May 23, 2017
    Assignee: Japan Display Inc.
    Inventor: Kazuto Tsuruoka
  • Patent number: 9640744
    Abstract: A LED module includes a substrate, a LED chip supported on the substrate, a metal wiring installed on the substrate, the metal wiring including a mounting portion on which the LED chip is mounted, an encapsulating resin configured to cover the LED chip and the metal wiring, and a clad member configured to cover the metal wiring to expose the mounting portion, the encapsulating resin arranged to cover the clad member.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 2, 2017
    Assignee: Rohm Co., Ltd.
    Inventor: Masahiko Kobayakawa
  • Patent number: 9629267
    Abstract: A housing for an electronic device and a method for manufacturing the housing are provided that combine metal and plastic in an aesthetically pleasing manner while meeting physical and technical requirements and specifications for the electronic device. Metal islands may be engaged with a plastic member so that projections of the plastic member are interlocked with corresponding recesses of formed between each of the metal islands. An exterior of the housing includes a surface of each of the metal islands and at least a portion of a surface of the plastic member. The interior of the housing includes another surface of the plastic member.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: April 18, 2017
    Assignee: Google Technology Holdings LLC
    Inventors: Vijay L Asrani, Paul L Fordham, Mark D Janninck
  • Patent number: 9613855
    Abstract: A method that includes, among other things, forming first and second contact openings in a layer of insulating material that respectively expose a portion of first and second source/drain (S/D) regions of first and second transistors that are of the opposite type, forming first, second and third layers of material within each of the first and second contact openings, and forming an implant masking layer that masks the first contact opening while leaving the second contact opening exposed for further processing. The method also includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, removing the implant masking layer and forming a conductive material in both the first and second contact openings so as to define first and second MIS contact structures positioned in the first and second contact openings.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Suraj K. Patil, Zhiguo Sun, Keith Tabakman
  • Patent number: 9601402
    Abstract: A package apparatus comprises a first wiring layer, a metal layer, a conductive pillar layer, a passive component, a first molding compound layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to each other. The metal layer is disposed on the first surface of the first wiring layer. The conductive pillar layer is disposed on the second surface of the first wiring layer. The passive component is disposed on the second surface of the first wiring layer. The first molding compound layer is disposed within a part of the zone of the first wiring layer and the conductive pillar layer. The second wiring layer is disposed on the first molding compound layer and one end of the conductive pillar layer. The protection layer is disposed on the first molding compound layer and the second wiring layer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: March 21, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: E-Tung Chou, Chu-Chin Hu, Shih-Ping Hsu
  • Patent number: 9543239
    Abstract: A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 ?m.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: January 10, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Shoji Yasunaga
  • Patent number: 9536802
    Abstract: A semiconductor device includes a semiconductor chip, a resin mold portion sealing a component in which the semiconductor chip is included, and a bonding layer disposed between the resin mold portion and the component. The bonding layer is made of an organic resin that is disposed at an obverse side of the component, and includes a first layer bonded to the component and a second layer bonded to the resin mold portion. A loss coefficient tan ? of the first layer is smaller than a loss coefficient tan ? of the second layer within a temperature range of 200° C. to 250° C.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: January 3, 2017
    Assignee: DENSO CORPORATION
    Inventor: Tomohito Iwashige
  • Patent number: 9502272
    Abstract: Devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first semiconductor device and a second semiconductor device coupled to the first semiconductor device. An underfill material is disposed between the first semiconductor device and the second semiconductor device. The underfill material is also disposed on sidewalls of the first semiconductor device and the second semiconductor device. The underfill material has a first thickness on sidewalls of the first semiconductor device and a second thickness on sidewalls of the second semiconductor device. The second thickness is different than the first thickness.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 9466544
    Abstract: A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 11, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Trent S. Uehling
  • Patent number: 9466556
    Abstract: A lead frame includes an outer lead and a plating layer that covers a lower surface and side surfaces of the outer lead. The plating layer does not cover the upper surface of the outer lead. A frame base material is exposed from the plating layer at the upper surface of the outer lead.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: October 11, 2016
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Harunobu Sato, Takashi Yoshie, Susumu Kurashima
  • Patent number: 9437519
    Abstract: A lid including a lid body, and a wing portion, the wing portion being disposed on a die side of the lid body such that an edge of the wing portion is flexible independent from a portion of the lid body adjacent to the edge of the wing portion.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Gerard McVicker, Sri M. Sri-Jayantha
  • Patent number: 9431364
    Abstract: A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non-conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: August 30, 2016
    Assignee: Cypess Semiconductor Corporation
    Inventors: Kiah Ling Tan, Sally Yin Lye Foong, Lee Changhak, Chin Nguk Lai
  • Patent number: 9379034
    Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 28, 2016
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Kim-Yong Goh, Yiyi Ma, Xueren Zhang
  • Patent number: 9379193
    Abstract: A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: June 28, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stephen St. Germain, Roger M. Arbuthnot, Peter Moens
  • Patent number: 9252028
    Abstract: A power semiconductor module has a first frame portion, a power semiconductor element, a second frame portion, a control integrated circuit, a wire, and an insulator portion. The power semiconductor element is mounted on a first surface of the first frame portion. The control integrated circuit is mounted on a third surface of the second frame portion for controlling the power semiconductor element. A wire has one end connected to the power semiconductor element and the other end connected to the control integrated circuit. The first surface of the first frame portion and the third surface of the second frame portion are located at the same height in a direction vertical to the first surface of the first frame portion.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: February 2, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masataka Shiramizu, Ming Shang
  • Patent number: 9196578
    Abstract: A semiconductor package has multiple dies and an interior power bar that extends within an interior space formed within the die flag between the dies. The bond pads located on the interior side of each die are wire-bonded to the interior power bar. Some embodiments may have more than two dies and/or more than one interior power bar between each pair of adjacent dies.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: November 24, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sheau Mei Lim, Meng Kong Lye, Pei Fan Tong
  • Patent number: 9165868
    Abstract: A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: October 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Masato Hatano
  • Patent number: 9153527
    Abstract: The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: October 6, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yusuke Ota, Fukumi Shimizu
  • Patent number: 9147648
    Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: September 29, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Hamza Yilmaz
  • Patent number: 9142472
    Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: September 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernardo Gallegos, Abram Castro
  • Patent number: 9111920
    Abstract: A semiconductor device includes: a die pad comprised of a metal, and having at least one cutout portion in its peripheral edge portion, and a protruding portion formed by the cutout portion so as to protrude laterally from the peripheral edge portion; an inner lead having at its end a bonding pad that is placed in the cutout portion with an interval between the bonding pad and the die pad; a semiconductor chip held on the die pad so that a center position of the semiconductor chip is located on the protruding portion side with respect to a center position of the die pad; and a wire configured to electrically connect the semiconductor chip to the bonding pad.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: August 18, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY CO., LTD.
    Inventors: Masaaki Nishijima, Tsuyoshi Tanaka
  • Patent number: 9048365
    Abstract: A light-emitting diode device includes a base substrate including a plurality of quantum well layers, a first electrode on one side of the plurality of quantum well layers, and a second electrode on an opposite side of the plurality of quantum well layers. The device includes a tensile-stressing layer formed on the base substrate and having a thickness and chemical composition configured to generate a first tensile stress in the base substrate, the first compressive stress selected to cause the base substrate to have a predetermined band-gap.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Patent number: 9040387
    Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Zhiwei Gong, Michael B Vincent, Scott M Hayes, Jason R Wright
  • Patent number: 9029992
    Abstract: In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 12, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Sung Gyu Kim, Byong Jin Kim, Gi Jeong Kim
  • Publication number: 20150108624
    Abstract: A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Inventor: Masato HATANO
  • Patent number: 9000589
    Abstract: A surface mount semiconductor device is assembled by positioning an array of semiconductor dies with an array of metallic ground plane members between and beside the semiconductor dies. The arrays of dies and ground plane members are encapsulated in a molding compound. A redistribution layer is formed on the arrays of dies and ground plane members. The redistribution layer has an array of sets of redistribution conductors within a layer of insulating material. The redistribution conductors interconnect electrical contacts of the dies with external electrical contact elements of the device. As multiple devices are formed at the same time, adjacent devices are separated (singulated) by cutting along saw streets between the dies. The molding compound is interposed between tie bars of the ground plane members and the insulating material of the redistribution layer in the saw streets, and at the side surfaces of the singulated devices.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: April 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dominic Poh Meng Koey, Zhiwei Gong
  • Publication number: 20150084168
    Abstract: A microelectronic device package including a package substrate, microelectronic component disposed on a first surface of a first portion of the substrate, and encapsulant material surrounding the microelectronic electronic component. An exposed surface of the first portion of the substrate is exposed through an opening in a first major surface of the encapsulant material. The exposed surface of the first portion has an edge. Encapsulant material is adjacent to the edge at the first major surface. The exposed surface is opposite the first surface. A stress relief feature located in one of the first major surface or a second major surface of the encapsulant material. The second major surface is opposite the first major surface. The stress relief feature reduces an amount of the encapsulant material and is 1 mm or less of a plane of the edge of the exposed surface. The plane is generally perpendicular to the exposed surface.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Inventors: MIN DING, Tim V. Pham
  • Patent number: 8987874
    Abstract: Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of the support member. Some of the conductive traces include bond sites carried by the projection and having an outer surface at a first distance from the first side of the support member. The assembly further includes a protective coating deposited over the first side of the support member and at least a portion of the conductive traces. The protective coating is generally co-planar with the outer surface of the bond sites carried by the projection.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Kevin W. Hutto
  • Patent number: 8981536
    Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: March 17, 2015
    Assignee: Chipbond Technology Corporation
    Inventors: Chin-Tang Hsieh, You-Ming Hsu, Ming-Sheng Liu, Chih-Ping Wang
  • Patent number: 8969138
    Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshihiko Shimanuki
  • Patent number: 8946875
    Abstract: A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 3, 2015
    Assignee: Intersil Americas LLC
    Inventors: Nikhil Vishwanath Kelkar, Lynn Wiese, Viraj Ajit Patwardhan
  • Patent number: 8937375
    Abstract: A substrate structure has a first surface and a second surface. A plurality of carrying members are formed on the first surface and a plurality of conductive traces are formed on the second surface. In addition, the substrate structure has a first, a second and a third thermal stress relief structures. The first thermal stress relief structure is that lengths of the substrate structure in different axial directions are substantially equal to each other. The second thermal stress relief structure is that a plurality of separated alignment marks are formed on the substrate structure. The third thermal stress relief structure is that the substrate structure has at least one clearance area extending along one of the axial directions of the substrate structure and the clearance area has no carrying members and no conductive traces formed thereon.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: January 20, 2015
    Assignees: Lite-On Electronics (Guangzhou) Limited, Lite-On Technology Corporation
    Inventor: Chen-Hsiu Lin
  • Patent number: 8933548
    Abstract: A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: January 13, 2015
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Kazunori Oda, Masaki Yazaki
  • Patent number: 8927342
    Abstract: The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: January 6, 2015
    Assignee: Tyco Electronics AMP GmbH
    Inventors: Peter Goesele, Friedrich Seger, Josef Sinder, Joachim Stifter, Oliver Werner
  • Patent number: 8900969
    Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: December 2, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventor: Hong Shen
  • Publication number: 20140312479
    Abstract: Methods of and devices for providing escaping routes for the flux and gases generated to move away from the solder joint in the process of solder joint formation.
    Type: Application
    Filed: March 5, 2014
    Publication date: October 23, 2014
    Applicant: Flextronics AP, LLC
    Inventors: Omar Garcia Lopez, Pedro Alejandro Ahumada Quintero, Enrique Avelar Secada, Murad Kurwa, Juan Carlos Gonzalez