Abstract: Composite interconnect structure forming methods using injection molded solder are disclosed. The methods provide a mold having at least one opening formed therein with each opening including a member of a material dissimilar to a solder to be used to fill the opening, and then fill the remainder of each opening with solder to form the composite interconnect structure. The resulting composite interconnect structure can be leveraged to achieve a much larger variety of composite structures than exhibited by the prior art. For example, the material may be chosen to be more electrically conductive than the solder portion, more electromigration-resistant than the solder portion and/or more fatigue-resistant than the solder portion. In one embodiment, the composite interconnect structure can include an optical structure, or plastic or ceramic material.

Abstract: The present invention relates to a stress-free lead frame (1) for a semiconductor. The stress-free lead frame (1) is provided with a stress-relief means (15) and an interlocking means (16) at the outer periphery. The stress-relief means (15) is capable of accommodating expansion and compression while the interlocking means (16) take care of shock and vibration during handling to thereby eliminate delamination of the lead frame (10).

Abstract: A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer into at least two discrete sections. The stress-relieving pattern may be in the form of an interface between the discrete sections of the first layer, or a wall of material different from the material of the first layer.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: An integrated circuit carrier arrangement includes a printed circuit board (PCB), a receiving plate to which an integrated circuit can be mounted, and a carrier fast with the PCB. The carrier has a plurality of resilient interconnection arms and a plurality of electrical connection islands. A number of the interconnection arms interconnect adjacent electrical connection islands, and a number of the interconnection arms interconnect an electrical connection island and the receiving plate, so that a plurality of electrical connection islands surrounds the receiving plate.

Abstract: A surface of a lead frame of a semiconductor device package, on which a semiconductor chip is mounted, is formed to have a mesh structure, whereby a connecting area between the lead frame and a molding resin can be increased to have strong bonding. Further, only filler particles having a small diameter than the mesh are taken into the vicinity of the lead frame, suppressing the effect of stresses to reduce deformation of the lead frame.

Abstract: A power semiconductor component includes at least one power semiconductor chip and surface-mountable external contacts. The power semiconductor chip includes large-area contact areas on its top side and its rear side, which cover essentially the entire top side and rear side, respectively. The top side also includes, alongside the large-area contact area, a small-area contact area; the areal extent of the small-area contact is at least ten times smaller than the areal extent of the large-area contact areas. The small-area contact area is connected to an individual external contact of the power semiconductor component via a bonding wire connection. The large-area contact area of the top side is connected to external contacts via a bonding tape.

Abstract: An apparatus, method, and system for providing a stress absorption layer for integrated circuits includes a stiffening layer adapted to limit flexing. A compliance layer is physically associated with the stiffening layer, with the compliance layer adapted to absorb stress caused by mismatched thermal properties between two materials. A thru hole passes through both the stiffening layer and the compliance layer, with the thru hole being adapted to receive a solder joint. The stress absorption layer contacts both a semiconductor package and a substrate. The solder joint disposed in the thru hole connects the semiconductor package to the substrate.

Abstract: A crack stopping structure is disclosed. The crack stopping structure includes a semiconductor substrate having a die region, a die seal ring region, and a scribe line region; a metal interconnect structure disposed on the semiconductor substrate of the scribe line region; and a plurality of dielectric layers disposed on the semiconductor substrate of the die region, the die seal ring region, and the scribe line region. The dielectric layers include a first opening exposing the surface of the metal interconnect structure of the scribe line region and a second opening exposing the dielectric layer adjacent to the metal interconnect structure such that the metal interconnect structure and the exposed portion of the dielectric layer form a step.

Abstract: The present invention provides a semiconductor element mounting substrate 101 including: a base substrate 1 having a region 2 for mounting a semiconductor element 11, the region 2 being set on the major surface of the base substrate 1; a plurality of wiring patterns 3 formed on the base substrate 1 and connected to the semiconductor element 11; and a dummy pattern 8 formed like a frame in the region 2 for mounting the semiconductor element 11 and not connected to the wiring patterns 3.

Abstract: The invention relates to a module comprising a carrier element having a lower stiffness or a different structure in a first region than in a second region, and also comprising a component applied to the carrier element. The component and the first region are connected to one another by a wire connection covered by a material.

Abstract: A clamping assembly for clamping a lead frame with pre-attached semiconductor device, comprising of: a first member, to hold the lead frame, said first member having a surface profile in contact with a surface profile of the semiconductor device, a second member for allowing the mounting of the first member thereon, an attachment means to secure the first member onto the second member, wherein the attachment means is adjustable to conform the surface profile of the first member to the surface profile of the lead frame.

Abstract: A clip for a semiconductor device package may include a metal sheet including an array of windows and one or more conductive fingers. Each of the conductive fingers has a first end and a second end. The first end is electrically connected to the metal sheet at one of the windows. Each of the conductive fingers is adapted to provide electrical connection to a top semiconductor region of a semiconductor device or a lead frame at the second end.

Abstract: A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.

Abstract: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus.

Abstract: A monitoring system includes a monitor chip or chips soldered to a printed wiring board. By mirroring a function IC chip interface with the monitor chip, the consumed and remaining thermal/and or vibration-fatigue life of the function IC chip based on the life-environment actually experienced through monitoring of the monitor chip is readily determined. The monitor chip includes monitoring interconnections and/or circuitry which determines the number and/or location of failed-open solder terminations of the monitor chip.

Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film. The second interconnection is connected to the first interconnection via the via. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, with a warped shape such that when the wiring substrate rests on a horizontal plate, at least a central part of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised.

Abstract: Provided is a semiconductor device including a semiconductor chip, a film (first film) which is provided so as to cover an active region with a peripheral portion of the semiconductor chip being uncovered, and is made of a dielectric material having a low dielectric constant, and a package molding resin (sealing resin) provided so as to cover the semiconductor chip and the film. As a result, deterioration in contact property with the sealing resin is suppressed and a high frequency characteristic can be enhanced.

Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

Abstract: The present invention provides a method of making a stackable power semiconductor package system comprising forming a lower lead frame, having an upward bent source lead and an upward bent gate lead, mounting a power semiconductor device on the lower lead frame utilizing interconnect structures and forming an upper lead frame wherein the upper lead frame is on the power semiconductor device.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

Abstract: An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support.

Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.

Abstract: An integrated circuit package system is provided including forming a D-ring comprising half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.

Abstract: In a ball grid array (BGA) package, a first stiffener is attached to a surface of a substrate. A second stiffener is attached to the surface of the substrate to be co-planar with the first stiffener. The second stiffener is separated from the first stiffener by a channel therebetween. An integrated circuit (IC) die is mounted to a surface of the second stiffener.

Abstract: A lead frame and a semiconductor device having a lead frame are disclosed. The lead frame is provided with a mount bed to mount a semiconductor chip, first and second lead terminals and first and second extension portions of band-shapes. The first and the second extension portions extend from sides of the first and second lead terminals and are bent. An electronic component is attached to Tip portions of the first and the second extension portions with connection conductors interposed in between.

Abstract: A magnetic sensor is constituted using magnetic sensor chips mounted on stages supported by interconnecting members and a frame having leads in a lead frame. Herein, the stages are inclined upon plastic deformation of the interconnecting members. When the frame is held in a metal mold and the stages are pressed, the interconnecting members are elastically deformed, so that the magnetic sensor chips are bonded onto the stages placed substantially in the same plane and are then wired with the leads. Thereafter, the stages are released from pressure, so that the interconnecting members are restored from the elastically deformed states thereof. When the magnetic sensor chips are combined together to realize three sensing directions, it is possible to accurately measure three-dimensional bearings of magnetism, and the magnetic sensor can be reduced in dimensions and manufactured with a reduced cost therefore.

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

Abstract: A heat spreader lid includes an outer periphery region having a lip for bonding to an underlying substrate board, a center region, and one or more strain isolation regions. The strain isolation regions are located between the center region and the outer periphery region and may comprise a number of slots cut partially or completely through the lid in a pattern surrounding or partially surrounding the center region. The strain isolation regions provide isolation of strain and relief of stress due to thermal expansion of the lid despite constraint at its periphery by the bonded lip, resulting in less thermally-induced warping of the center region, less thermally-induced stress on the bond between the lip and the substrate board, and/or less thermally-induced deflection of the substrate board.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is a step of forming electrodes (12) on a wafer (10); a step of providing a resin layer (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); a step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract: A semiconductor device according to the present invention includes a conductor member, an IC-chip and leads, all molded together with a resin mold. The conductor member is composed of a base portion on which the IC-chip is mounted, a cover portion for covering a functioning surface of the IC-chip, and a bent portion connecting the cover portion to the base portion. The base portion includes a lead portion that is grounded. The cover portion and the base portion are positioned substantially in parallel to each other, and the IC-chip is disposed in an inner space between the cover portion and the base portion. The lead portion to be grounded and the leads electrically connected to the IC-chip extend out of the resin mold. Since the IC-hip is disposed in the inner space of the conductor member that is grounded, the IC-chip is protected from the electromagnetic noises and from electrostatic charges otherwise accumulated in the resin mold.

Abstract: A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.

Abstract: An electronic component package includes: a main body including a plurality of layer portions that are stacked and that have their respective side surfaces, the main body having a side surface including the side surfaces of the layer portions; and wiring disposed on the side surface of the main body. Each of the layer portions has at least one electronic component chip and a plurality of electrodes disposed on the side surface of the layer portion.

Abstract: An electronic component includes a metal substrate, a semiconductor chip configured to be attached to the metal substrate, and a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate. The buffer layer extends across less than an entire bottom surface of the semiconductor chip.

Abstract: Mechanical stress on solder joints that hold BGA modules to computer motherboards is reduced by adding to the motherboard a topmost layer, and forming V-shaped channels into the layer next to the BGA module so that stress is shielded from the BGA module and its solder joints.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin layer (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); a step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal, thin film fabrication technology is used during the wafer process.

Abstract: The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each of the mounting portions are electrically connected, a corner portion which connects the plurality of mounting portions and which has a hanging lead piece that supports the mounting portions and an electrode connection piece that connects the plurality of electrodes, and a half-blanking portion that has a concave portion formed in a thickness direction of the lead frame and a protrusion formed at a position corresponding to the concave portion, and which is covered with a sealing resin material that seals the semiconductor element. A stress-dispersing portion for dispersing stress that arises, when the half-blanking portion is formed, is provided in the corner portion.

Abstract: A lead frame structure is provided, which includes a die pad having a first mounting portion and a second mounting portion separated from the first mounting portion by a gap. The first and second mounting portions are formed with corresponding blocking surfaces bordering the gap, so as to allow a flow rate of an encapsulating resin flowing through the gap during a molding process to be reduced by the blocking surfaces, such that different portions of the encapsulating resin respectively flowing above, in and below the die pad can have substantially the same flow rate, thereby preventing bonding wires from being deformed to cause short circuit and avoiding formation of voids. A semiconductor package with the lead frame structure is also provided.

Abstract: A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

Abstract: A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface, first bonding pads and second bonding pads, wherein the first bonding pads and the second bonding pads are disposed on the active surface. The chip is fixed below the lead frame, and the lead frame includes inner leads and bus bars. The inner leads and the bus bars are disposed above the active surface of the chip, and the bus bars are located between the inner leads and the corresponding first bonding pads. The first bonding wires respectively connect the first bonding pads and the bus bars. The second bonding wires respectively connect the bus bars and a part of the inner leads. The third bonding wires respectively connect the second bonding pads and the other of the inner leads.

Abstract: The present invention is directed to a new bonding pad structure having a rugged contact interface that makes it more difficult for a crack to grow from the peripheral edge of the bonding pad. The rugged contact interface also helps to accumulate more solder paste on the edge of the bonding pad, increase the thickness of the solder layer near the pad edge and prevent the pad edge from being oxidized and turning into a crack initiation point.

Abstract: A circuit board including a flexible insulating substrate, a plurality of conductive wirings placed in line on the flexible insulating substrate, and bumps provided at end portions of the respective conductive wirings positioned in a region for mounting a semiconductor chip is provided. The circuit board further includes an auxiliary conductive wiring positioned at an outermost corner of the region for mounting the semiconductor chip, being adjacent to and an outside the outermost conductive wiring, and an auxiliary bump formed on the auxiliary conductive wiring in line with the bumps on the conductive wirings.

Abstract: A technique for preventing cracks and residual resin on a semiconductor chip in a molding process in the assembly of semiconductor devices is provided. A distance from a bottom surface of a cavity of a lower mold die to a ceiling surface of a cavity of an upper mold die of a resin molding die is made same as or smaller than a distance from a lower surface of a die pad to an upper surface of a plate terminal, and an U-shape elastic body is arranged on semiconductor elements between the plate terminal and the die pad, thereby mitigating a load due to a clamp pressure of mold dies in the molding process by an elastic deformation of the elastic body. Consequently, a load applied on the semiconductor devices is reduced, thereby preventing formation of cracks on the semiconductor elements.

Abstract: The present invention provides a semiconductor element mounting substrate 101 including: a base substrate 1 having a region 2 for mounting a semiconductor element 11, the region 2 being set on the major surface of the base substrate 1; a plurality of wiring patterns 3 formed on the base substrate 1 and connected to the semiconductor element 11; and a dummy pattern 8 formed like a frame in the region 2 for mounting the semiconductor element 11 and not connected to the wiring patterns 3.

Abstract: Provided is a circuit device having conductive patterns which are equally spaced apart and a manufacturing method thereof. A method for manufacturing a circuit device of the present invention includes the steps of: preparing a conductive foil; forming conductive patterns, which are included in a unit having at least regions for mounting circuit elements, by forming isolation trenches having a uniform width in the conductive foil; electrically connecting the conductive patterns to the circuit elements; sealing with a sealing resin so as to cover the circuit elements and to be filled in the isolation trenches; and removing the conductive foil in its thickness portions where no isolation trenches are provided.