With Stress Relief Patents (Class 257/669)
  • Patent number: 5796162
    Abstract: The present invention is a mechanism for packaging semiconductor chip which provides ease of assembling and high positioning precision with improved mechanical, electrical and thermal performance. The present invention adopts a die pad frame for supporting the semiconductor chip and a separate lead frame for connection to center part of the semiconductor chip. The semiconductor chip is fixed on the die pad using silver paste, the lead frame conductors are then placed on top of the chip, and the lead frame and the die pad frame containing the chip are assembled with the positioning protrusions of the die pad frame locked and secured by the positioning openings of the lead frame. Subsequently the bonding terminals on the chip are connected to the lead conductors with short gold wires. The frames locking method does not require high precision positioning machines, thereby reducing the assembly cost.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: August 18, 1998
    Assignee: Greatek Technology Co., Ltd.
    Inventor: Chien Ping Huang
  • Patent number: 5793100
    Abstract: A lead frame includes first slits in a lead frame edge in a direction parallel to a longitudinal direction of the lead frame edge at spaced intervals and a plurality of slits in the lead frame edge in a direction parallel to the first slits at spaced intervals so that the second slits are separated from the first slits wherein each end of each of the second slits is located near the center of a corresponding first slit.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: August 11, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshiharu Takahashi
  • Patent number: 5789806
    Abstract: A leadframe including bendable support arms for downsetting a die attach pad and method are disclosed herein. The leadframe includes at least one frame member and the die attach pad. At least two distinct, readily bendable support arms are connected with and extend between the die attach pad and the frame member. The support arms are configured to be bent in a predetermined way in the method of the invention such that when they are bent they provide previously unattainable amounts of die attach pad downset within the overall configuration of the leadframe.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: August 4, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Charlie Kho Chua, Ka-Heng The, Peter Howard Spalding
  • Patent number: 5789804
    Abstract: Between an IC and an IC receptacle is interposed a flexible wiring sheet, via which contact pieces of the IC and contacts of the IC receptacle are held in contact with one another. In this case, lateral deviation and flexing of the wiring sheet are prevented satisfactorily, and proper contact between the IC and IC receptacle is ensured. A back-up frame is applied by adhesive to the flexible wiring sheet to form a contact agency. The back-up frame 11 has a central window 11 to form a non-backed-up region in a central portion of the flexible wiring sheet 3 that covers the window. The IC 3 and flexible wiring sheet are held in forced contact with each other in the non-backed-up region. The back-up frame has an outer edge portion forming a back-up region for backing up an edge portion of the wiring sheet. In this back-up region, the IC receptacle and the flexible wiring sheet 1 are held in contact with each other.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: August 4, 1998
    Assignee: Yamaichi Electronics Co., Ltd.
    Inventors: Noriyuki Matsuoka, Kazumi Uratsuji
  • Patent number: 5783868
    Abstract: Extension areas of a metal layer electrically connected to the original die bond pad allow for testing connections to be made. In this way, the connection area used for the final packaging of the die will not be damaged. The extension areas can be removed along with the testing connections. The use of perforations and/or underlayer sections can aid in the removal of the extension area. The extension area can extend over a passivation layer so that the basic die design need not be changed.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: July 21, 1998
    Assignee: Integrated Device Technology, Inc.
    Inventor: Terry R. Galloway
  • Patent number: 5773878
    Abstract: The present invention relates to a lead frame design for IC packaging to reduce chip stress and deformation and to improve mold filling. The die-pad is split into several sections which are jointed together by flexible expansion joints. The split die-pad allows relative motion between the pad and the chip during die attach cure. It also breaks down the total die pad area (and length) that is rigidly attached to the chip into smaller sections. These two factors reduce the magnitude of coefficient-of-thermal expansion (CTE) mismatch and out of plane deformation of the assembly, resulting in lower chip stress and deformation and improved package moldability.
    Type: Grant
    Filed: January 4, 1996
    Date of Patent: June 30, 1998
    Assignee: Institute of Microelectronics National University of Singapore
    Inventors: Thiam Beng Lim, Sarvotham M. Bhandarkar
  • Patent number: 5773877
    Abstract: A method for designing an IC package having a plastic encapsulated portion and a lead frame portion that are bonded together at a bonding interface includes selecting material candidates for each of the plastic encapsulated portion and the lead frame potion to obtain possible material combinations. A peeling stress and a shear stress at the bonding interface for each possible material combination is determined. A design material combination from all of the possible material combinations is then selected based on a singularity parameter and stress intensity factors of the peeling stress and the shear stress. To enhance the IC package, a circular fillet feature having a radius is added to a singularity point at the bonding interface of the IC package to reduce the stress at the singularity point.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: June 30, 1998
    Assignee: Ford Motor Company
    Inventors: Jun Min Hu, Yi-Hsi Pao
  • Patent number: 5767527
    Abstract: A semiconductor device includes a rigid member embedded in a resin package body for supporting thereon outer leads that extend from the resin package body and test pads provided on the outer leads for testing the semiconductor device.
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: June 16, 1998
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Yoneda, Kazuto Tsuji
  • Patent number: 5763941
    Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a dielectric layer and leads extending across a surface of the dielectric layer. Each lead has one end permanently fastened to the dielectric layer and another end releasably bonded to the dielectric layer. The releasable end is held in place by a bond having a relatively low peel strength, desirably less than about 0.35.times.10.sup.6 dynes/cm.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: June 9, 1998
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 5763942
    Abstract: There is provided a lead frame including an outer frame, a die pad on which a semiconductor device is to be mounted, a plurality of outer leads extending from the outer frame to the die pad, a dam bar connected at opposite ends thereof to the outer frame for connecting the outer leads to one another for prevention of resin overflow, and a support lead extending obliquely to the dam bar for connecting the die pad to the outer frame. The outer frame is formed beyond an end of the dam bar with an opening extending in a direction making an angle with a direction in which the dam bar longitudinally extends so that there is formed an elastically deformable portion between the opening and an end of the dam bar, the opening having a length covering at least a width of the dam bar.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: June 9, 1998
    Assignee: NEC Corporation
    Inventor: Yasuhiro Suzuki
  • Patent number: 5760465
    Abstract: An electronic package which includes a flexible substrate, stiffener and chip. The chip is bonded to the substrate, which was secured to the stiffener. Strain relief means are utilized at various locations in the package to prevent problems (e.g., tape "wrinkling") associated with relatively large differences in coefficients of thermal expansion between the package's various elements.
    Type: Grant
    Filed: February 1, 1996
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: David James Alcoe, Steven Wayne Anderson, Yifan Guo, Eric Arthur Johnson
  • Patent number: 5760467
    Abstract: A lead frame includes a die pad having a plurality of die pads including a main die pad and an auxiliary die pad respectively supported by a main die pad supporting lead and an auxiliary die pad supporting lead extending inwardly from opposite sides of a planar annular frame, thereby inhibiting vertical movement of the die pad to which a load member is die-bonded. This support prevents deformation and breaking of wires bonded to the load member and the lead frame.
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: June 2, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Motomi Itihasi
  • Patent number: 5757067
    Abstract: There is provided a semiconductor device sealed therearound with resin, including (a) a lead frame formed with an island region and a plurality of inner leads, tip ends of the inner leads defining a cavity as viewed perpendicularly to a plane of the chip, the island region being located in the cavity, (b) a chip mounted on the island region of the lead frame and having a plurality of electrodes thereon, and (c) wires for connecting the electrodes of the chip to the inner leads. The cavity is defined so that a wire for connecting inner leads to electrodes located at corners on a diagonal line D1 of the chip is shortest in length and a wire for connecting one of electrodes located at a corner on a diagonal line D2 perpendicular to the diagonal line D1 is longest in length.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: May 26, 1998
    Assignee: NEC Corporation
    Inventor: Takehito Inaba
  • Patent number: 5731962
    Abstract: A semiconductor chip mounted on an island is electrically connected to inner leads through tape-automated bonding leads supported by an insulating suspender tape, and a support ring is connected between the insulating suspender tape and suspender pins connected to the island so as to maintain an original relative position between the semiconductor chip and the tape-automated bonding leads during a molding stage.
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: March 24, 1998
    Assignee: NEC Corporation
    Inventor: Tomoo Imura
  • Patent number: 5729049
    Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: March 17, 1998
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Larry D. Kinsman, Jerry M. Brooks
  • Patent number: 5719437
    Abstract: Thin semiconductor die, approximately 0.004 to 0.007 inches thick, are positioned substantially on the neutral plane of a smart card, the neutral plane defined as the plane of substantially no mechanical strain during flexure of the smart card, thereby providing smart cards having improved resistance to mechanical flexure, and/or smart cards having improved RF performance.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: February 17, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Mark Bradford Clifton, Richard Michael Flynn, Fred William Verdi
  • Patent number: 5712507
    Abstract: A plurality of slits are formed in a die pad of a lead-frame for mounting a semiconductor chip, and are arranged in such a manner as to nearly equalize the length of peripheral sub-areas of the die pad uncovered with the semiconductor chip, thereby effectively absorbing a shrinkage and an elongation due to a difference in thermal expansion coefficient among the die pad, the semiconductor chip and a plastic package hermetically sealing the semiconductor chip.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: January 27, 1998
    Assignee: NEC Corporation
    Inventors: Takahiro Eguchi, Yasuhiro Suzuki
  • Patent number: 5708293
    Abstract: In a unit part of a lead frame for mounting a semiconductor chip, connecting leads and supporting leads extending from a lead frame main body toward a semiconductor chip mounting region are formed. Between each supporting lead and the lead frame main body, a movable part and a spring part for elastically supporting the movable part are disposed. The tip portion of the supporting lead connected with the movable part extends to the inside of the semiconductor chip mounting region in the natural state of the movable part, so that the tip portion butts against the side face of a semiconductor chip when the semiconductor chip is mounted. Thus, the semiconductor chip can be supported and fixed by using a bias force applied by the spring part. The base portions of the supporting leads, the movable part and the spring part do not remain in a package, and hence do not cause a stress in the package and do not increase the volume of the package.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: January 13, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Takao Ochi, Hisashi Funakoshi, Ichiro Okumura, Hajime Honma, Keiji Okuma, Keiichi Fujimoto
  • Patent number: 5686757
    Abstract: A film carrier tape for use in TAB, having a lead wiring of a desired shape, and formed on a base film having a sprocket hole for conveyance and positioning, for connecting electrode pads of a semiconductor chip, includes a corner slit formed in at least one portion of four corner portions of a suspender positioned between a device hole and outer lead holes so as to vertically communicate.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: November 11, 1997
    Assignee: NEC Corporation
    Inventor: Michitaka Urushima
  • Patent number: 5684327
    Abstract: A lead frame for use in a resin-sealed type semiconductor device, comprising an outer frame, a plurality of leads supported by the outer frame, arranged side by side and each composed of an inner lead and an outer lead, a die pad arranged inside the outer frame and located so that the tips of the inner leads are close to the die pad and oppose the die pad, and a resin flow-control body. The resin flow-control body has been formed by extending a portion of the outer frame toward the die pad through a space formed in the outer frame. The body is designed to be placed in a cavity of a mold having a gate communicating with the cavity, with the space located between the gate and the cavity, in order to form a resin sealing body.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: November 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakazawa, Yumi Inoue
  • Patent number: 5684328
    Abstract: An LOC type semiconductor package and a fabricating method thereof comprises first and second through holes formed at inner leads and bus bars of the LOC-type lead frame, and third through holes formed at the tape which is bonded with the lower side of the inner leads and the bus bars, by pins at a tape cutter. Thus, air existing at both tape during the bonding process effectively flows out so as to prevent the trapping of air bubbles. Accordingly, during the wire bonding process, wire shorting and damage to the package body can be prevented. Since EMC is deposited into the first and the second through holes and supports the inner leads and the bus bars during the molding of the semiconductor package, the reliability of the semiconductor package can be improved.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: November 4, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Tae Jin, In Pyo Hong, Chang Eui Ko
  • Patent number: 5682061
    Abstract: A semiconductor chip assembly is mounted to contact pads in a compact area array. An interposer is disposed between the chip and the substrate. The contacts on the chip are connected to terminals on the interposer by flexible leads extending through apertures in the interposer. The terminals on the interposer in turn are bonded to the contact pads on the substrate. Flexibility of the leads permits relative movement of the contacts on the chip relative to the terminals and the contact pads of the substrate and hence relieves the stresses caused by differential thermal expansion. The arrangement provides a compact structure similar to that achieved through flip-chip bonding, but with markedly increased resistance to thermal cycling damage.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 28, 1997
    Assignee: Tessera, Inc.
    Inventors: Igor Y. Khandros, Thomas H. DiStefano
  • Patent number: 5677571
    Abstract: The present invention relates to a semiconductor package having lead pins of lead frame for outwardly extending terminals of electrodes of a semiconductor chip embedded in a mold resin. The semiconductor package according to the present invention comprises flat lead fins connected to respective sides of a bed portion of a lead frame, an insulation film for covering at least one side of each of the lead fins, and lead pins formed on a surface of the insulation film, the lead pins being disposed at a predetermined pitch.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: October 14, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koji Shirai
  • Patent number: 5670797
    Abstract: On an insulating substrate through which a plurality of through holes are formed, the following components and members are provided: LED chips, each of which consists of a p-side semiconductor layer and an n-side semiconductor layer that are joined into a p-n junction, and is placed between the adjacent through holes; a first electrode which is formed in one of the adjacent through holes, and connected to the p-side semiconductor layer so as to form electrical connections on the bottom surface of the insulating substrate; and a second electrode which is formed in the other adjacent through hole in a separate manner from the first electrode, and connected to the n-side semiconductor layer so as to form electrical connections on the bottom surface of the insulating substrate. Further, each through hole is sealed by a sealing member such as a conductive bonding agent. Moreover, the LED chips are sealed by a light-transmitting resin.
    Type: Grant
    Filed: December 1, 1995
    Date of Patent: September 23, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Jun Okazaki
  • Patent number: 5668404
    Abstract: A semiconductor device includes a semiconductor chip attached to a lead frame with recesses on the rear surface of the semiconductor chip opposite the lead frame. These recesses increase the heat radiation area of the semiconductor chip. In a method of producing a semiconductor device, the height of a cavity between upper and lower dies is smaller than the height of the semiconductor chip including bump electrodes. During a molding process, the bump electrodes contact the upper die or a dam surrounding the bump electrodes so that no thin burrs are produced on the surfaces of the bump electrodes in the molding process.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: September 16, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shunichi Abe, Seizo Ohmae
  • Patent number: 5654877
    Abstract: A lead-on-chip integrated circuit assembly comprising at least one extremely thin adhesive layer transferred from a carrier onto the face of an integrated circuit chip, and a lead frame laminated to the last adhesive layer, with cured adhesive acting as an insulator, wherein said lead frame is aligned and connected to integrated circuit chip connection pads. This lead-on-chip integrated circuit assembly may be encapsulated. Thermally conductive and electrically insulating filling may be included with the adhesive to improve heat conduction from the integrated circuit ("IC"). Compliant adhesive reduces thermally induced stresses between the lead frame and IC chip. Both the improved thermal performance and reduced moisture absorption of the encapsulated assembly improves the reliability of the integrated circuit package.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: August 5, 1997
    Assignee: Staktek Corporation
    Inventor: Carmen D. Burns
  • Patent number: 5640044
    Abstract: The present invention is premised on a semiconductor device in which one semiconductor chip is mounted on each of both faces of a die pad of a lead frame. The semiconductor chips are disposed such that the projected lines, on the die pad, of the corresponding sides of the semiconductor chips, intersect with each other at an angle of 45.degree.. The tips of inner leads are located in the sides of a virtual octagon formed by outwardly enlarging an octagon formed by connecting, to one another, the apexes of the semiconductor chips. The sides of the virtual octagon are respectively opposite to the sides of the semiconductor chips. The number of the inner leads of which tips are located in each of the sides of the virtual octagon, is the same as the number of bonding pads disposed at each of the sides of the semiconductor chips.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: June 17, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinitsu Takehashi, Kenzo Hatada
  • Patent number: 5637914
    Abstract: A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: June 10, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Naotaka Tanaka, Akihiro Yaguchi, Makoto Kitano, Tatsuya Nagata, Tetsuo Kumazawa, Atsushi Nakamura, Hiromichi Suzuki, Masayoshi Tsugane
  • Patent number: 5623163
    Abstract: A leadframe for semiconductor derides having patterned die-mounting structures arranged along the longitudinal axis of the leadframe. Each of the structures contains a die pad for mounting a semiconductor device chip thereon, die pad supports for supporting the die pad, fingers for forming inner leads and outer leads, and tiebars for preventing leakage of a molding material during a molding process. At least one of the die pad supports has a first communication path through which a molding material flows from one side of the body to the other thereof. The molding material supplied into one side of the leadframe can flow to the other side thereof through not only the gaps between the die pad and the body but also the first communication path during a molding process, resulting in a small flow rate difference of the molding material. Failures such as visible voids and no fillings are not produced in the plastic-molding package.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: April 22, 1997
    Assignee: NEC Corporation
    Inventor: Atsuhiko Izumi
  • Patent number: 5621242
    Abstract: A thin semiconductor package having a support film formed on an upper surface of the inner leads with a thickness approximately equal to the thickness of a portion of the molding compound overlaying the inner leads.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: April 15, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Kon Mok, Seung-Ho Ahn, Gu-Sung Kim
  • Patent number: 5614759
    Abstract: Semiconductor rectifier devices having oppositely extending terminals lying in a common plane are fabricated using upper and lower lead frames each comprising a pair of parallel side rails and spaced apart cross bars extending between the side rails. Cantilevered terminals are mounted along the cross bars. The cross bars of the upper frame lie in a plane downwardly off-set from the plane of the upper frame, and the cross bars of the lower frame lie in a plane upwardly off-set from the plane of the lower frame. Free ends of the terminals of the upper frame lie in a plane upwardly off-set from the plane of the upper frame cross bars, and free ends of the terminals of the lower frame are off-set downwardly from the plane of the lower frame cross bars. Semiconductor chips are mounted on the terminal free ends of the lower frame, and the upper frame is disposed on top of the lower frame with the upper frame terminals contacting the chips.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: March 25, 1997
    Assignee: General Instrument Corp.
    Inventors: William Vandenheuvel, Johannes Vandenbroeke
  • Patent number: 5610436
    Abstract: A surface mount electronic device, attachable to a circuit board, comprises an insulating substrate having a top surface and a bottom surface; a plurality of metallized terminal pads on the bottom surface; and a plurality of leads, each attached to one of the terminal pads by a solder column. Each of the leads comprises a first substantially horizontal lead portion attached to one of the terminal pads by the solder column. A plurality of upturned prongs on the first substantially horizontal lead portion forms a pronged area configured to hold the solder column. A second substantially horizontal lead portion terminates in a free end for attachment to the circuit board. An upwardly curved intermediate lead portion connects the first and second substantially horizontal portions and underlies the bottom surface of the substrate.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 11, 1997
    Assignee: Bourns, Inc.
    Inventors: Roger Sponaugle, Robert R. Rainey
  • Patent number: 5608260
    Abstract: A leadframe has conductive fingers with an insulating film located on a first portion of the fingers. The insulating film has openings into which contact pads formed of a noble metal are provided. Pads on a chip are wire bonded to these contact pads on the leadframe. The first portion is encapsulated in a molded package. The structure inhibits silver migration, provides insulation between wires and leadframe, and provides improved adhesion between plastic package and leadframe. A single insulating film with openings for providing the contact pads provides all these features.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: March 4, 1997
    Assignee: International Business Machines Corporation
    Inventors: James L. Carper, Gary H. Irish, Sheldon C. Rieley, Robert M. Smith, Robert L. Jackson
  • Patent number: 5594274
    Abstract: A distance between each two sides adjacent to a first portion X of the outer peripheral portion of an island portion 3 and the inner end of an inner lead portion 4 is set to d.sub.1 while the distance between each two sides adjacent to a second portion Y, which is diagonal to the first portion X, and the inner end of the inner lead portion 4 is set to d.sub.2 (<d.sub.1). The island portion 3 has a portion 2a for placing the semiconductor chip thereon and an overhang portion 3a attached to that portion. A semiconductor chip 2 is adhered on the island portion 3 of the lead frame 10, which is then attached in position within a mold. From a gate 21 a molten resin is injected into the cavity 23 in a diagonal direction of the square island portion, i.e. a direction from the first portion X toward the second portion Y.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: January 14, 1997
    Assignee: NEC Corporation
    Inventor: Kenji Suetaki
  • Patent number: 5587606
    Abstract: A lead frame includes a die pad on which a semiconductor chip is mounted, a plurality of leads each having an end which faces the die pad, and tie bars connecting the leads, wherein each of the tie bars is formed so as to project from a surface of each of the leads by an amount sufficient to break a boundary between a tie bar and a lead when the tie bar is pushed back so that the tie bar and lead is separated. The method for producing a semiconductor device using the above lead frame includes steps of clamping by molding dies the lead frame having the semiconductor chip mounted on the die pad so that the tie bar is pushed back and cut off and encapsulating the semiconductor chip by resin so that a package made of the resin is formed, and releasing the lead frame from clamping by the molding dies and removing the tie bar pushed back by the clamping from the lead frame.
    Type: Grant
    Filed: February 16, 1995
    Date of Patent: December 24, 1996
    Assignee: Fujitsu Miyagi Electronics Ltd.
    Inventor: Takashi Sekiba
  • Patent number: 5572346
    Abstract: In an LCD driver package using a TAB tape carrier an object of this invention is to prevent damage to the input leads from being caused under the influence of the twisting or wrinkling of TAB tape due to the difference in thermal expansion coefficient between the printed circuit board and the LCD glass board, and so forth. At least one pair of anchor hole 40are formed in the TAB tape carrier 10 of an LCD driver package having input leads 12 connected to a printed circuit board 24, output leads 14 connected to an LCD glass board 26, and a chip 22, the tape carrier 10 being fixed on the printed circuit board 24 with solder or an adhesive using anchor holes 40 after mounting of the LCD driver chip. Fixing through such anchor holes prevents the twisting or wrinkling of the tape from propagating to the input leads.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: November 5, 1996
    Assignee: International Business Machines Corporation
    Inventors: Kazunori Sakamoto, Kazuhiro Umemoto
  • Patent number: 5572067
    Abstract: An integrated circuit chip die (12) is manufactured with sacrificial structures (16) placed at the areas of die that are likely to experience cracks. According to one embodiment of the invention, these sacrificial structures are placed at the corners of the die. The sacrificial structures are constructed with metal lines (22, 24) that resist propagation of cracks into the area of the die containing electronic devices. The metal lines form lattice steps so that the surface of the die will more tightly bond to the molding compound that makes up the die package.
    Type: Grant
    Filed: October 6, 1994
    Date of Patent: November 5, 1996
    Assignee: Altera Corporation
    Inventor: Guru Thalapaneni
  • Patent number: 5554885
    Abstract: A semiconductor device comprises an electrically insulating film having a device hole; a plurality of groups of leads, each group including of a large number of leads arranged in a predetermined pattern, in a plurality of lead formation regions on the surface of the film; an integrated circuit chip positioned within the device hole and with electrodes connected to inner lead portions of the leads; and a resin sealing portion that seals in at least the integrated circuit chip, the film, and the lead groups. The film comprises a first group of aperture portions including of aperture portions provided in regions outside the lead formation regions and a second group of aperture portions consisting of a plurality of aperture portions provided in the lead formation regions.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: September 10, 1996
    Assignee: Seiko Epson Corporation
    Inventors: Yasuo Yamasaki, Norikata Hama, Munenori Kurasawa, Nobuaki Hashimoto
  • Patent number: 5550402
    Abstract: In the electronic module (M) of extra-thin construction disclosed, it is the principal object to substantially reduce the tendency to fracture of the module's semiconductor chip embedded in the plastic casing of the module (M), notwithstanding the extremely small thickness of the casing. The chip is fitted on the chip pad of a system support formed by a thin metal strip, commonly known as a lead frame. The chip may partly overlap the external contacts of the module that lie on one of the flat sides of the module's plastic casing. Slits in the system support, which form the boundaries of the chip pad and are inevitable lines of weakness in the thin metal strip, are situated at an oblique angle relative to the edges of the square or rectangular chip, preferably at about 45.degree.; hence the slits extend also at an oblique angle to possible fracture lines within the monocrystalline structure of the material used in chip manufacture, because said fracture lines are parallel to the chip's edges.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: August 27, 1996
    Assignee: Esec Sempac S.A.
    Inventor: Karl Nicklaus
  • Patent number: 5545921
    Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.
    Type: Grant
    Filed: November 4, 1994
    Date of Patent: August 13, 1996
    Assignees: International Business Machines, Corporation, Siemens Aktiengesellschaft
    Inventors: Harold W. Conru, Francis E. Froebel, Albert J. Gregoritsch, Jr., Sheldon C. Rieley, Stephen G. Starr, Ronald R. Uttecht, Eric J. White, Jens G. Pohl
  • Patent number: 5541451
    Abstract: A semiconductor device has a semiconductor chip and a ceramic envelope consisting of a base portion and a sealing portion sealing the chip, and has good high-speed operability, radiation properties and electric characteristics. Leads made of Cu and electrically connected to the semiconductor chip are held between the base portion and the sealing portion, and have anchor holes formed in the portions thereof held therebetween. A glass-based adhesive is coated in the anchor holes, between the held portions of the leads and the base portion, and between the held portions and the sealing portion.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: July 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Megumi Kusumi
  • Patent number: 5541447
    Abstract: A lead frame for use in producing of a semiconductor integrated circuit comprises a lead frame member, a plurality of leads, a tie bar, a plurality of auxiliary leads, a support-stay portion and a connecting portion. A semiconductor element such as an IC chip is mounted on a semiconductor-element-mounting portion of the lead frame member, while the leads are arranged along and extending from a side portion of the lead frame member. The tie bar is connected among the leads and auxiliary leads at their tip-edge portions. Herein, the auxiliary leads are electrically unconnected from the semiconductor element. Further, the support-stay portion is provided at a corner portion of the lead frame member. The connecting portion is provided between a base-edge portion of the support-stay portion and a base portion of the auxiliary lead. A location of the connecting portion is selected in such a manner than the connecting portion will be unaffected by bending of the leads.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: July 30, 1996
    Assignee: Yamaha Corporation
    Inventors: Yoshihisa Maejima, Seiya Nishimura, Masayoshi Takabayashi, Tokuyoshi Ohta
  • Patent number: 5539251
    Abstract: A "leads over chip" lead frame design is disclosed which can be used with a conventional die having leads located at the periphery. The inventive design uses an elongated tie bar which extends from one side of the lead frame to the other, across the die. The die is attached to the bottom of the tie bar, then the bond pads are wire bonded to the lead fingers. The lead fingers of the inventive lead frame do not extend over the top of the die, but are positioned in close proximity to allow for short bond wires. The die and a portion of the lead fingers are encapsulated, and the tie bars are severed to separate them from the lead frame. The invention allows the advantages of a leads over die configuration with a conventional die having bond pads located at the periphery. Therefor, a single die can be manufactured which can be used either with the inventive lead frame for a plastic package, or with a ceramic package.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: July 23, 1996
    Assignee: Micron Technology, Inc.
    Inventors: Robert E. Iverson, Walter L. Moden
  • Patent number: 5528077
    Abstract: A TAB semiconductor device according to the present invention is as follows. One end of each lead whose direction is fixed by a TAB tape is connected to a corresponding electrode on a semiconductor pellet placed at a predetermined position of the TAB tape. The TAB tape is a tape having the thin leads fixed on a film and a portion where the film is removed, i.e., a window portion in a predetermined area. Only the arrangement of the leads is exposed to the window portion. A user arbitrarily cuts the leads in this area in accordance with mounting. The leads have normal signal leads and wider leads together. As for these wider leads, slits are provided to make the lead widths uniform throughout the window portion.
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: June 18, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Tane, Jiro Nakano, Jun-ichi Ohno
  • Patent number: 5521428
    Abstract: A flagless semiconductor device (10) includes a semiconductor die (22) having a plurality of bond pads (26) which are electrically coupled to a plurality of leads (16) by wire bonds (28). The die is supported by two cantilevered tie bars (18). Use of cantilevered tie bars decreases the total plastic-metal interface area in a plastic encapsulated device, thereby lessening the probability of internal delamination and package cracking. The cantilevered tie bars also permit a variety of die sizes to be used with the same lead frame design. Suitable configurations for cantilevered tie bars include, but are not limited to, U-shape, T-shape, and H-shape configurations.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: May 28, 1996
    Assignee: Motorola, Inc.
    Inventors: Tom R. Hollingsworth, Michael B. McShane
  • Patent number: 5517056
    Abstract: A leadframe (30) having a novel resin injecting area (44) is disclosed to facilitate and control the removal of a molded gate (18) prior to excising a semiconductor device(70) from a carrier ring (14). The carrier ring has a corner which is on a diagonal with a corner of the package body (12) to form the resin injecting area. The resin injecting area of the leadframe has a hole (48) and an extension bar (50) extending from the hole to connect to a tie bar (36), which supports a die pad (32), inside the package body. The hole in the leadframe is designed for retaining a molded gate. The extension bar is designed to make the removal of a portion of a molded gate easier and more controllable. The semiconductor device can be shipped in the carrier ring with a portion of the molded gate already removed.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: May 14, 1996
    Assignee: Motorola, Inc.
    Inventors: Charles G. Bigler, Alan H. Woosley, Michael B. McShane
  • Patent number: 5506446
    Abstract: There is provided a base for an electronic package. The base includes a peripheral portion for a polymer adhesive and a central portion for one or more semiconductor devices. A lead support is adjacent the substrate and located between the peripheral portion and the central portion. When a polymer adhesive bonds a leadframe to the package base, the lead support prevents deflection of the inner lead tips.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: April 9, 1996
    Assignee: Olin Corporation
    Inventors: Paul R. Hoffman, George A. Brathwaite, Doanh D. Bui, Deepak Mahulikar
  • Patent number: 5486722
    Abstract: A lead frame in which a bulgy portion is disposed to each of inner leads or outer leads at a position corresponding to a mold line, whereby a lead gap in the portion is defined as less than 0.15 mm.The lead frame has such a shape as causing less resin leakage upon applying resin molding to a packaging main body upon preparing an IC plastic package. This enables to improve the yield in preparing the IC plastic package and reduce the manufacturing cost.
    Type: Grant
    Filed: May 3, 1994
    Date of Patent: January 23, 1996
    Assignee: Sumitomo Metal Mining Company, Limited
    Inventors: Naohumi Sato, Yasuhiro Yanagisawa
  • Patent number: 5471097
    Abstract: A semiconductor device encapsulated with a synthetic resin portion, includes a semiconductor chip, a plurality of leads each electrically connected at one end thereof to the semiconductor chip and bent to have a gull-wing like shape extending outwardly from the synthetic resin portion, and an insulating support member provided in a flat portion nearer to the resin portion than a bottom soldering face of the leads of the gull-wing like shape. The leads are fixed to each other by means of the insulating support member. The semiconductor device has an improved lead alignment even if the leads are each very thin and aligned with fine pitch. Such a semiconductor device can be assuredly mounted on a printed board or the like with ease together with mounting the semiconductor device on the printed board type components, thereby contributing to acquisition of a highly reliable electronic device.
    Type: Grant
    Filed: September 9, 1994
    Date of Patent: November 28, 1995
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Patent number: 5468993
    Abstract: A semiconductor device includes a rectangular semiconductor chip bonded to a die pad of a lead frame in which a plurality of leads are arranged around the die pad. An area where the semiconductor ship is electrically connected with the leads around the semiconductor chip and the semiconductor chip are sealed with a resin. A distance between the semiconductor chip and a peripheral wall of the die pad is larger at a central portion of each side of the chip than at each corner of the chip. The leads are arranged such that a line connecting all lead ends is substantially parallel with the peripheral wall of the die pad.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: November 21, 1995
    Assignee: Rohm Co., Ltd.
    Inventor: Koji Tani