Abstract: There is disclosed herein an electronic circuit assembly, comprising: (1) a plastic molded substrate 10 having a first surface 12 with a mounting pad 14 disposed thereon; (2) a reinforcing member 20 having a first member portion 22 and a second member portion 24, wherein the first portion 22 is embedded within the substrate 10 beneath the first surface 12 thereof proximate the mounting pad 14 and wherein the second portion 24 is oriented generally parallel with and at a first predetermined distance h.sub.1 above the mounting pad 14; (3) an electronic surface mount component 18 having a termination 16 thereon, the component 18 being oriented such that the termination 16 is disposed at a second predetermined distance h.sub.2 above the second member portion 24; and (4) a solder joint 30 connecting the component termination 16 with the mounting pad 14 and the second member portion 24.

Abstract: A lead frame for LOC is provided which can reduce a variation in coverage of an insulating adhesive, permitting the fixation of a semiconductor chip and wire bonding to be stably performed. In a lead frame for LOC 10 wherein an insulating adhesive for fixing a semiconductor chip is applied to inner leads 11 in their semiconductor chip mounting region, a coverage regulating lead 14 is provided outside the semiconductor chip mounting region and adjacent to inner leads 11a, 11b located at the end of the semiconductor chip mounting region, permitting the insulting adhesive to be homogeneously applied to each of the inner leads 11 without creating any variation in coverage of the adhesive.

Abstract: A lead (10) for a semiconductor device (12) comprising a strip portion (14) comprising a first substantially horizontal portion (18) connected to the semiconductor device (12), a substantially vertical portion (20) connected to the first substantially horizontal portion (18), and a second substantially horizontal portion (22) connected to the substantially vertical portion (20) with at least one hole (16) disposed in the strip portion (14). A method of providing an electrical contact for connecting a semiconductor device (12) to a surface (24) comprising the steps of extending at least one lead (10) from the semiconductor device (12) and slotting the lead (10).

Abstract: A patterned tape attached to a semiconductor chip in a chip scale package enhances process reliability in manufacturing of the chip scale package. A shape of the beam leads concentrates stresses in the part of the beam lead where the beam lead should be disconnected during the bonding of the beam leads to the chip bonding pads, and therefore, the part to be expected to be disconnected disconnects without damaging other parts of the beam lead. In addition, the reliability of a chip scale package is enhanced, because the beam lead attached to the chip bonding pad has little chance of being damaged during bonding.

Abstract: Improved TAB tapes include an electrically insulating tape, an electrically conductive pattern on a first surface of the electrically insulating tape and a protective layer for protecting exposed portions the electrically conductive pattern. The protective layer may comprise a solder resist layer. A bonding agent is also provided for bonding the electrically conductive pattern to the electrically insulating tape. According to a preferred aspect of the present invention, any "peel-off" stress which may arise during formation of the TAB tape and/or during subsequent thermal treatment steps and cause cambering of the electrically insulating tape, may be reduced by forming a camber suppressing film on a second surface of the electrically insulating tape. The camber suppressing film is preferably made of the same material as the protective layer so that any camber stress induced by the protective layer is offset equally by an opposing camber stress induced by the camber suppressing film.

Abstract: A semiconductor package has a controlling IC attached to a die pad using an epoxy molding compound (EMC) pad. The EMC pad is formed so as to be slightly larger than the controlling IC. EMC pads are cut from an EMC pad pattern which is formed from a predetermined number of EMC tablets. The EMC pad pattern is molded by heating and pressing the EMC tablets into a wafer shape having a thickness of approximately 0.3 mm and a diameter of approximately 100 mm. Such a thin EMC pad is capable of providing sufficient dielectric strength, and allows for manufacturing of semiconductor packages at lower cost. In addition, conventional equipment can be used to fabricate the semiconductor packages. The packages are flexible, and even a thin package is not easily broken.

Abstract: A method for marking poor quality printed circuit board units of a printed circuit board strip for ball grid array semiconductor packages wherein at least one degradation-indicating hole is at least partially formed in a poor quality printed circuit board unit of the strip at a region defined between an outer edge of the resin seal molding region of the unit and a cutting line formed on the printed circuit board strip to separate the unit from the strip. Even when a plurality of printed circuit board strips are packed in a vacuum under the condition in which they are stacked, there is no phenomenon that those strips in the pack are permanently deformed, for example, permanently bent. Also, there is no phenomenon that melt resin is leaked from the mold, thereby causing it to be bled out onto the upper surface of the printed circuit board strip. Since no paint is used to mark poor quality printed circuit board units, there is no problem associated with the use of the paint such as a contamination.

Abstract: A semiconductor device includes a lead frame including a die pad having corners, inner leads having respective inner end portions, outer leads, a hanging lead reinforcement, first hanging leads, and second hanging leads; a semiconductor chip bonded to the lead frame; and metal wires bonding the chip to the lead frame. A length of one side of the semiconductor chip is 2.5 mm smaller than a side of a molded resin external dimension, one side of the largest dimension of the hanging lead frame reinforcement not being longer than one side of the semiconductor chip. The die pad is sunk where second hanging leads are connected to the hanging lead reinforcement and has a step where connected to the second hanging leads. The camber of the external shape of the semiconductor device is reduced and a semiconductor device with high quality and reliability is obtained.

Abstract: A semiconductor package (80) is provided that serves to support a semiconductor chip (12). A radial slot (54) is formed in an inner ring (26). Cross-slots (64) and (66) are formed in a corner member (38) of polyimide film (22). The slots (54), (64) and (66) serve to allow independent expansion of various portions of the polyimide film (22) and prevent breakage of contact leads (14), (16), (18) and (20) due to the differences in the thermal coefficient of expansion of the semiconductor material and the polyimide film material.

Abstract: Apparatus and method of increasing the distance of the gap between a lead frame and a semiconductor die surface in a package assembly. An adhesive layer and a gap increasing layer are disposed between the lead frame and the semiconductor die surface. The gap increasing layer has a thickness selected to reduce likelihood of package particles from being trapped between the lead frame and the die surface. The gap increasing layer includes silver plating, and has a thickness of at least about 300 to 500 microinches.

Abstract: A semiconductor device having a photosensitive thermosetting resin layer 64 provided on top of a protective film 13 for a semiconductor chip 10. A lead frame 11 is affixed to the surface of this photosensitive thermosetting resin layer 64 only at support pin sections 60, 61, and this lead frame 11 is electrically connected to the surface of semiconductor chip 10. Breakage of the wiring and chip cracking are prevented after the pressure-bonding mounting of the lead frame. Because package cracking and package warping are better controlled in thermal processes such as such as IR reflow and resin sealing, a lower cost semiconductor device and manufacturing method are enabled.

Abstract: A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool, which has features adapted to control the position of the lead.

Abstract: Leading and trailing metal features in a dense array of conductive lines bordering an open field are formed with side surfaces that gradually taper in the direction of the open field toward an underlying substrate. Each side surface bordering the open field is formed with a sufficient slope to reduce cracking of the subsequently deposited dielectric gap fill layer at high stress areas bordering the open field.

Abstract: A semiconductor chip carrier assembly which includes a flexible substrate having a metallicized path on one of its surfaces in electrical communication with a semiconductor chip. A stiffener is disposed adjacent to said flexible substrate and is bonded thereto by an adhesive composition. The adhesive composition which comprises a microporous film laden with a curable adhesive is disposed between the flexible substrate and the stiffener. A cover plate is adhesively bonded to the semiconductor chip and to the stiffener. A process of making the assembly involving disposition of the flexible substrate in a vacuum fixture upon which the adhesive composition and stiffener is placed followed by the application of heat and pressure to cure the curable adhesive is also described.

Abstract: In order to package an electronic component, a leadframe is provided having at least one flag portion (2) and at least one lead portion (7) extending towards the flag portion (2). The lead portion (7) includes an end portion (10) of reduced thickness adjacent the flag portion (2) and a channel (9) between the end portion (10) and the rest of the lead portion. The leadframe is etched to form the channel (9) and the end portion(10), which together form a locking step. The electronic component (3) is then mounted on the flag portion (2) and electrically connected to the end of the lead portion (7). The electronic component (3), the electrical connection (5), at least the end portion (10) and the intermediate portion (9) of the lead portion (7) and at least part of the flag portion (2) are encapsulated in a plastics molding compound, which enters and fills the locking step, and is then cured.

Abstract: An electrical contact element that solves many problems associated with making electrical connections to integrated circuit chips. The contact element fits in small areas, but in some configurations can provide compliance in multiple directions to provide the required compliance. The contacts are shaped to provide relatively large stroke and also large force for good electrical contact. Contact elements according to the invention are incorporated into contactors for making electrical contact to Ball Grid Arrays for testing. Contact elements according to the invention are also incorporated into Ball Grid Array packages, and used as a mounting point for solder balls. The contact elements make the electrical connection withstand stress associated with differential thermal expansion.

Abstract: A lead frame is prepared which has a plurality of leads whose inner lead portions are coupled to a support member and a notch formed across the bottom surface of each inner lead portion near at its front portion on the support member side. After an LSI chip is adhered to the support member, pads on the chip are connected via bonding wires to corresponding inner leads of the plurality of leads. The chip and inner lead portions are buried in an insulating layer made of resin or the like as protective coating. Each inner lead portion is cut with a cutting device such as laser beam at the notch position to separate the inner lead portion from the support member. Thereafter, the separated assembly unit is accommodated in a package made of resin or the like, and the outer leads are cut and shaped. For an assembly method of a semiconductor device including a wire bonding process, bonding defects to be caused by deformed leads can be reduced.

Abstract: A tape-fixed leadframe is provided, which prevents ion migration of metal contained in leads with a simple configuration. The leadframe is comprised of electrically-conductive lead fingers and an electrically-insulating tape for fixing the lead fingers. The tape includes an electrically-insulating base film and an electrically-insulating adhesive layer formed on a surface of the base film. The adhesive layer of the tape is adhered to the lead fingers, thereby fixing the lead fingers at their original positions. The adhesive layer has protruded parts located at respective sides of each of the lead fingers, intervening parts between two adjoining ones of the protruded parts, and depressed parts opposite to the lead fingers. The protruded parts are thicker than the intervening parts. The depressed parts are thinner than the intervening parts.

Abstract: A method for producing a lead frame having outer leads and inner leads, for use in constructing a resin-sealed semiconductor package comprises etching processes for etching a blank. A first resist pattern having a first opening and a second resist pattern having second openings are formed on the first and the second major surfaces of a blank. The first and the second major surfaces of the blank are etched through the first and the second resist pattern by a first etching process using a first etchant to form a first recess corresponding to the first opening and second recesses corresponding to the second recesses in the first and the second major surfaces, respectively. The first recess is filled up with an etch-resistant layer. The second major surface is etched through the second resist pattern by a second etching process using a second etchant so that portions of the blank corresponding to the second openings of the second resist pattern are etched through to form the tips of the inner leads.

Abstract: A lead frame, method of making same and semiconductor package containing the lead frame. The semiconductor package includes the lead frame which includes an essentially flat, planar lead frame body and lead frame leads extending from the lead frame body, the lead frame leads extending partially out of the plane of the lead frame body. A semiconductor chip is disposed on the lead frame and an encapsulant encapsulates the lead frame body, the semiconductor chip and a portion of the lead frame leads, with a portion of the lead frame leads extending external to the encapsulant. The two dimensional cross section can be essentially in the shape of a "U", essentially sinusoidal in shape, the sinusoidal shape having an odd number of half cycles of the sinusoidal shape or essentially in the shape of a "W".

Abstract: A semiconductor apparatus having an insulation coating section at an outer section of an outer lead so as to reduce the number of inferior products at the time of bonding a fine pitch outer lead, which includes an insulation coating section formed at an outer portion of an outer lead of a TAB tape so as to prevent electric short between outer leads which occurs due to a conduction ball contained in ACA/ACF during a TAB outer lead bonding.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: The present invention relates to an improved leadframe and method of attaching leads of a leadframe to contact pads on a carrier. The leadframe includes resilient engaging means or fingers for engaging the carrier and for exerting forces on the carrier to thereby support the carrier and accurately position and align the contact pads on the carrier with the leads. This invention overcomes the expense and inaccuracies of known leadframe designs and techniques in attaching leads to carrier contact pads using such things as fixtures for positioning the leadframe and carrier, visual alignment procedures and retaining tabs.

Abstract: In semiconductor device fabrication, warping of the support pins must be prevented so that the semiconductor element can be properly positioned during the wire-bonding and resin-sealing processes. The invention provides a process in which a V-shaped groove 33, for example, is formed in the mounting pad 31 and the support pins 32, imparting rigidity to the support pins 32.

Abstract: A method for forming an interconnect for establishing electrical communication with a semiconductor die is provided. The method includes: providing a microbump tape and then mounting the tape to a substrate with a compliant layer therebetween. The microbump tape includes an insulating film having a pattern of microbump contact members corresponding to a pattern of bond pads on the die. The compliant layer can be formed of a curable adhesive such as a silicone elastomer. A coupon containing a plurality of microbump tapes can be mounted to a substrate wafer which can then be singulated to form a plurality of interconnects. The interconnects can be used with a testing apparatus for testing unpackaged semiconductor dice.

Abstract: A semiconductor device with a LOC structure having a semiconductor device lead frame, TAB leads, and an insulating TAB tape, wherein the semiconductor device lead frame has a plurality of leads and is formed by fixing a semiconductor element on one surface side of the leads through insulating tapes. The leads are arranged to correspond to electrodes of the semiconductor element, wherein the TAB leads electrically connect the leads of the semiconductor device lead frame and the electrodes on the semiconductor element, and wherein the insulating TAB tape has electrical insulating characteristics and is fixed on the other surface side of the leads of the semiconductor device lead frame to surround a group electrodes of the semiconductor element, the insulating TAB tape serving to hold the TAB leads to be isolated from each other.

Abstract: A high frequency semiconductor device includes a molded resin package having side surfaces; a source lead for die-bonding, having a thickness, partially disposed within the package, and penetrating through the side surfaces of the package; gate and drain leads having the same thickness as the source lead and disposed adjacent to and spaced from the source lead by a distance shorter than the thickness of the source lead, the gate and drain leads being partially disposed within the package and penetrating through the side surfaces of the package; and a field effect transistor die-bonded to the source lead within the package and electrically connected within the package to the source, gate, and drain leads.

Abstract: A lead frame structure includes a lead frame skeleton and at least one die bar connected between the lead frame skeleton and a non-quadrangular die attach paddle. Each of a plurality of leads has an outer edge connected to the lead frame skeleton and an inner edge disposed adjacent to but separated from the periphery of the die attach paddle. Preferably, the inner edge of each lead is separated from the periphery of the die attach paddle by about 5-10 mils.

Abstract: A method and apparatus for a reinforced leadframe to substrate attachment in a semiconductor assembly. In one embodiment, a printed circuit board having a plurality of electrically coupled electrical contact regions and wire bond areas formed thereon has a leadframe attached thereto such that each of the bonding fingers of the leadframe is coupled to a respective electrical contact region on the printed circuit board. A ribbon of B-staged epoxy is disposed on the leadframe such that the leadframe is disposed between the ribbon of B-staged epoxy and the printed circuit board. An integrated-circuit die is mounted on the printed circuit board with the bonding fingers of the leadframe peripherally surrounding the integrated circuit die. The bonding pads on the integrated-circuit die are electrically coupled to respective wire bond areas on the printed circuit board.

Abstract: An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.

Abstract: A semiconductor device package includes a semiconductor chip and a plurality of inner leads, each having at least one slot formed along an upper surface of the inner lead. An adhesive layer is used to attach a bottom surface of the semiconductor chip to the upper surface of the inner lead. An encapsulant is allowed to flow in a package body mold, around the inner leads and through the slot. The slots prevent the production of turbulence along a side surface of the inner lead opposite to the flow direction, thereby avoiding problems associated with incomplete encapsulation such as the internal voids.

Abstract: A lead frame for a hollow plastic package is constructed with a source lead, a pellet mounting portion provided at the central portion of the source lead and mounting a pellet, a lead gate and a drain gate symmetrically provided across the pellet mounting portion at the both sides thereof. Then, each lead is provided with substantially equilateral trapezoidal cut-off having the upper bottom and the lower bottom along the extending direction of the lead on a part of the lead, so that a lead bending portion is formed with a narrow part thereat.

Abstract: A lead frame for LOC is provided which, even when an adhesive is applied to a lead prepared by stamping, can ensure insulation of a semiconductor element mounted from the lead. In applying an adhesive to a predetermined position of an inner lead 1 in a lead frame prepared by stamping to form an adhesive layer 4, the adhesive layer 4 is provided on the droop face of the inner lead 1. The droop face has no burr and a bulged center portion, permitting contact, derived from the burr, between a lead face and a semiconductor element, to be avoided, which ensures satisfactory insulation of the semiconductor element mounted from the lead.

Abstract: The resin-sealed package includes a lead frame having a supporting and heat spreading pad and inner and outer leads arranged to surround the supporting and head spreading pad. A tape automated bonding (TAB) structure is provided having a semiconductor chip having bonding pads formed on a periphery of a main surface of the semiconductor chip. A rear surface of the semiconductor chip is fixed to the supporting and head spreading pad. TAB leads are provided on the main surface of the semiconductor chip. One end of each TAB lead is connected with said bonding pads and the other end of each TAB lead is connected with one end of each inner lead of the lead frame. A resin molding is used for sealing the TAB structure and the supporting and head spreading pad and inner leads of the lead frame. An area of the supporting and head spreading pad is larger than that of the semiconductor chip of said TAB structure.

Abstract: A light-emitting diode (LED) device has a plurality of mutually separated terminal plates disposed on the bottom part of a horizontally elongated rectangular reflector case having an open front surface. Where a pair of these terminal plates is adjacent to each other with a gap in between, a LED chip is bonded to one of them and connected through a wire to the other. Terminal lead lines are extended from the terminal plates downward through the reflector case. The end parts of such a pair are shaped such that the gap therebetween has an horizontally extended part. When such a LED device is inserted into a groove formed in a light-conducting plate with a specified thickness to form an illuminator with a light-emitting surface, shearing stress is developed inside the reflector case as the terminal lead lines are passed through throughholes in the reflector case but is absorbed by the parts adjacent to such a horizontally extended portion of the gap.

Abstract: A rail of non-conductive material is applied to a semiconductor die and/or to the carrier substrate to which it is or will be bonded. The rail underlies those wires joining the die bond pads and substrate traces, which wires have an inordinate length, i.e. greater than about 100 mils for 1.0 mil diameter wires, to prevent sagging wires from contacting the die edge and breaking, or shorting to active areas on the die or substrate. A pattern of rails may be formed on the dice of an undivided wafer by, for example, screen printing. Rails may also be formed on the substrate, and rails on the substrate employed in combination with rails on dice carried thereon.

Abstract: A lead frame having a die pad of such a shape that prevents scattering of solder to lead when a chip is mounted on the lead frame, and a semiconductor device using such a lead frame are provided. The lead frame includes a die pad having a region surrounded by a first side, a second side opposing to the first side, a third side different from the first and second sides, and a fourth side opposing to the third side, and a lead formed of a conductor and electrically connected to a semiconductor element. The die pad includes a notch extending along the first and the second sides and positioned opposing to a main surface of the semiconductor element, and a through hole extending along the third and fourth sides and positioned opposing to the main surface of the semiconductor element. The semiconductor device employs the die pad.

Abstract: A lead frame module to be incorporated in data carriers is presented which is divided into two areas, namely a central area receiving the sensitive components of the module, and an outer area protruding beyond the edge of the central area and serving to glue the lead frame module to the data carrier. To prevent forces from being transmitted from the outer area of the electronic module to the central area upon bending loads of the data carrier, the outer area is decoupled mechanically from the central area. This can be done for example by providing partial discontinuities including relieving punchings in the transition between the central and outer area.

Abstract: An integrated circuit sensor assembly (10) is mounted to a solid surface (11) of a metal leadframe (12) by placing RTV adhesive (30-36) at the four corners of the substrate (14). The RTV material cover less than the entire surface area between the leadframe surface and the substrate. The RTV provides coplanar support for the sensor assembly while maintaining a gap between a significant portion of the surface area between the substrate and the leadframe surface. The metal leadframe undergoes compression and expansion stresses from temperature cycling during the manufacturing process. The gap decouples the sensor assembly from leadframe and provides stress isolation. Moreover, the flexibility and resiliency of the four corner RTV dots absorb stress induced by the leadframe.

Abstract: The present invention is characterized by providing leads not contributing to actual connection outside the corner leads to prevent the deformation of the corner leads and improve the yield of tape carriers. A device hole is made in a near-central place of an insulating resin film. Around the device hole, outer-lead holes are made. On the insulating resin film, a plurality of wiring patterns are provided and forced to project into the device hole. The plurality of wiring patterns are formed into a plurality of inner leads, of which the outermost ones are determined to be corner leads. On each corner of the device hole, an aligning mark is provided. Dummy leads are provided closer to the aligning marks. The dummy leads are made shorter than the inner leads and corner leads.

Abstract: A semiconductor chip connection component having numerous leads extending side-by-side across a gap in a support structure, each lead having a frangible section to permit detachment of one end of the lead from the support structure in a bonding process. The frangible sections are formed by treating the lead-forming material in an elongated treatment zone extending across the regions occupied by numerous leads. The process avoids the need for especially fine etching to form notches in the lateral edges of the leads.

Abstract: Resin tie bars are formed between leads of external leads extending out from a resin-sealed region. The external leads are formed such that lead width at portions beyond the portion where the resin tie bars are formed is less than the lead width at portions where the resin tie bars are formed. With this construction, resin extending between the leads from the periphery of the resin-sealed region, including the resin tie bars, can be easily removed after resin-sealing when the resin tie bars are subjected to water sprayed at high pressure.

Abstract: A semiconductor chip package includes a substrate having a first surface and a second surface and a gap extending from the first surface to the second surface. The substrate defines a plane which is substantially parallel to the first and second surfaces. The substrate has conductive terminals accessible and the second surface and bond pads. Conductive leads extend across the gap whereby each lead electrically interconnects one of the conductive terminals and one of the bond pads. Each lead includes an expansion section within the gap which is laterally curved with respect to the plane. A semiconductor chip having a back surface and a face surface is assembled to the substrate. The face surface includes a plurality of contacts on the periphery of the face surface of the chip whereby the chip contracts are electrically connected to the bond pads on the substrate.

Abstract: A semiconductor device has a semiconductor chip mounted on the mounting portion of a lead frame and sealed with resin. The chip is affixed to the lead frame by melting. A groove is formed in the lead frame in a cruciform, radial, lattice or similar pattern capable of reducing thermal stress during intermittent performance test and cycling test while insuring heat radiation.

Abstract: An electronic system utilizing at least one integrated circuit including a semiconductor integrated circuit chip housed in a package providing external electrical connections for the circuit chip. The system package has only a limited number of external connections available for such use. The system package includes an internal buss, or plurality of busses, which are electrically connected to the circuit chip and to selected external connections or the package to improve the efficiency of utilization of external connections on the package, as well as improving operating characteristics of the integrated circuit chip by improvements to voltage and current distributions to the chip, and also eliminating in some cases the consequences of a poor quality of external electrical connection to the system package itself.

Abstract: On an insulating substrate through which a plurality of through holes are formed, the following components and members are provided: LED chips, each of which consists of a p-side semiconductor layer and an n-side semiconductor layer that are joined into a p-n junction, and is placed between the adjacent through holes; a first electrode which is formed in one of the adjacent through holes, and connected to the p-side semiconductor layer so as to form electrical connections on the bottom surface of the insulating substrate; and a second electrode which is formed in the other adjacent through hole in a separate manner from the first electrode, and connected to the n-side semiconductor layer so as to form electrical connections on the bottom surface of the insulating substrate. Further, each through hole is sealed by a sealing member such as a conductive bonding agent. Moreover, the LED chips are sealed by a light-transmitting resin.

Abstract: A semiconductor device including a plurality of grooves (21) formed on a top surface of a heat sink (51). A sealing resin (2) fills a portion between a lead frame (5) provided facing the top surface and the heat sink (51). The grooves (21) are formed on both sides of a center region (22) extending so as to divide the top surface in two. A power semiconductor element (11) is disposed above the center region (22) and a controlling semiconductor element (16) controlling the power semiconductor element (11) is disposed above the region where the grooves (21) are formed. The above construction suppresses thermal resistance interposed in a path through which heat loss in the power semiconductor element (11) is radiated to the heat sink (51) and improves heat radiating efficiency while maintaining close contact between the sealing resin (2) and the heat sink (51).

Abstract: A semiconductor chip packaging device includes a lead frame electrically connected to the chip and mechanically supporting the chip; a metal layer guard ring formed along at least one peripheral edge of an active surface of the chip; at least one slit formed at corner parts of the chip; a passivation layer covering the metal layer guard ring, the chip and the lead frame; and a package body made of a molding resin encapsulating the passivation layer, the lead frame, the metal layer and the chip; the metal layer guard ring being chamfered or rounded at corner parts of the chip to reduce shear stresses at the corner parts of the chip.

Abstract: An ultra-thin resin molded semiconductor device of high reliability with low cost and with easy repair at time of mounting. A plurality of these semiconductor devices are stacked to provide a semiconductor module which has a higher function than semiconductor devices in the same volume, and a card type module utilizing assembled by the stacked semiconductor module is provided. In manufacturing the semiconductor module, an extremely thin lead frame and an LSI chip are directly connected together, and the mirror surface of the LSI chip is exposed by using a low viscosity epoxy resin to have a thin molding. The mirror surface is grinded to have a further thin thickness of the whole structure of the semiconductor device. A part of the lead frame is formed as a reinforcing member, a heat radiation path, a light shielding part for shielding the LSI from harmful light beams, or a positioning base for mounting a substrate.

Abstract: The present invention relates generally to a lead frame which is bended with a predetermined angle many times in order that a sectional area of a punch to form two lead lines which are located in the center of tie bars is increased, and increase the inertial moment as to a sectional area in making a lead frame of a desired shape. And the above-mentioned lead frame comprises a dambar; inner leads which has a certain angle at the part being below half the distance from lead tips to the above-mentioned dambar, and is connected to the above-mentioned dambar; outer leads which is connected to the above-mentioned dambar, and is populated on a circuit board; and tie bars which support the above-mentioned inner leads in case of taping.