Abstract: A semiconductor device having a semiconductor chip on a TAB (Tape Automated Bonding) tape with high reliability is provided. The semiconductor device of the present invention includes a TAB tape which has a base film provided with a device hole in a position where a semiconductor chip is mounted, a wiring pattern whose end portions constitute inner leads connected to the semiconductor chip and terminal connecting portions provided with solder balls, and a photo-solder resist which protects the wiring pattern. Chamfered portions which relieves internal residual stress caused in the photo-solder resist due to the difference in thermal expansion coefficient between the base film and the photo-solder resist are formed at locations on the photo-solder resist facing the corners of the device hole.

Abstract: A semiconductor device is formed of a casing, a substrate situated in the casing, at least one semiconductor chip fixed on the substrate, and at least one lead-out terminal for connecting the semiconductor chip to outside. The lead-out terminal includes a soldered portion soldered to the substrate, and a fixed portion fixed to the casing. A stress relaxing device or cutout is formed between the soldered portion and the fixed portion of the lead-out terminal to relieve stress along three axial directions orthogonal to each other. Thus, the crack formation is prevented in the soldered portion of the lead-out terminal while the resistance and impedance of the lead-out terminal are maintained at low values.

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions. A method of making a connection component includes removing material from the conductive structures or the support layer or both to form the anchors.

Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.

Abstract: A lead member includes a plurality of conductors arranged in parallel and an insulating film fixing the conductors at a predetermined pitch. Each conductor includes a first end portion, a second end portion, and a flat portion extending between the first and second end portions. The flat portion is located on a plane different from a plane on which the first end portion and the second end portion lie. The flat portion may be formed by bending the lead member along a bent line such that the bent line is kept straight. Preferably, each conductor includes a narrow portion and a wide portion, wherein a width of each conductor along the bent line is greater than half of the pitch between adjacent conductors.

Abstract: Fabrication of a semiconductor device, with an improved level of exposure of the rear surface of a die pad is enabled during the fabrication of which deformation of a die pad in a resin-encapsulating step is prevented from occurring, and which can be mounted on a printed wiring board with a sufficient soldering strength. In a resin-encapsulated semiconductor device in which a semiconductor element is placed on the front surface of a die pad of a lead frame including: the die pad; and support bars of the die pad that protrude outwardly from sides of the die pad, the semiconductor element and its periphery are encapsulated with a resin material while the rear surface of the die pad is exposed to the external environment, a groove is formed on the rear surface of the support bar so that the groove traverses the support bar in the neighborhood of the boundary between the support bar and the die pad along a direction intersecting a protruding direction of the support bar.

Abstract: The present invention is directed toward an apparatus and method of reinforcement of lead bonding in microelectronics packages. In one embodiment, a microelectronics package includes a microelectronics device having a bond pad, a conductive lead having a first end bonded to the bond pad to form a lead bond, an encapsulating material at least partially disposed about the conductive lead, and a reinforcement portion at least partially disposed about the lead bond and at least partially coupling the first end to the bond pad. The reinforcement portion has a greater modulus of elasticity and/or a greater bond strength than the encapsulating material. During thermal cycling of the microelectronics package, bond liftoff due to CTE mismatch is prevented by the reinforcement portion.

Abstract: A TSOP type semiconductor device having a LOC structure employing a copper (alloy) type frame prevents resin cracks that occur in a reliability test such as a temperature cycle test. The TSOP type semiconductor device has narrower common inner leads where a resin crack would be likely to occur first, and has a thinner chip.

Abstract: A semiconductor device package includes a die pad to which a semiconductor chip is vertically attached, having a smaller horizontal size than a horizontal size of the semiconductor chip. The package includes a plurality of inner leads which are electrically connected to the semiconductor chip, a plurality of outer leads each of which is integral with a respective one of the plurality of inner leads, a tie bar, and a package body for encapsulating the semiconductor chip, the die pad, and the plurality of inner leads. The tie bar for supporting the die pad has a downward bend effecting a downward vertical displacement from the die pad, and has a laterally spaced apart upward bend effecting an upward vertical displacement from the die pad. This package prevents imperfect encapsulation and resulting problems such as cracking of the package, and reduces damage to the die pad, such as warping of the die pad.

Abstract: A packaged semiconductor device is provided which includes a semiconductor chip, a die pad for mounting the semiconductor chip, and at least one bondwire. The bondwire has a first end connected to the semiconductor chip, a second end opposite to the first end, and a transitional portion extending from the second end. The semiconductor device also includes at least one lead having an inner portion connected to the second end of the bondwire and an outer portion, and a resin package for enclosing the semiconductor chip, the die pad, the bondwire and the inner portion of the lead. An angle defined between the inner portion of the lead and the transitional portion of the bondwire is no greater than 15 degrees.

Abstract: A method of treating a lead in a chip package. A conductive lead is positioned such that it extends across a gap in a dielectric substrate and is secured at either end to a first surface of the substrate. Directed energy is then applied to a desired portion of the surface of the lead within the gap. As a result of the application of energy, a surface layer of the lead is recrystallized thereby creating a fine grain, dense surface layer of lead material. Surface contaminates may be vaporized and contaminants at the grain boundaries of the recrystallized surface layers may be driven away from the grain boundaries such that a treated lead is more ductile and has better resistance to thermal cycling after the lead has been attached to a chip contact.

Abstract: The leadframe of the present invention comprises a supporting bar having the first terminals and the second terminals, wherein the first terminals are coupled to the separating portion of the leadframe and the second terminals are used to support the chip. A plurality of inner leads connected to the supporting bar. A plurality of external leads connected to the inner leads; Adhesive material, formed on the leadframe and used to attach the chip to the inner leads, wherein the area of adhesive material is smaller than that of said chip. A plurality of bonding wires is used to couple the chip to the leadframe. Finally, the chip is encapsulated with the molding compound to protect the chip and the bonding wires.

Abstract: An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.

Abstract: An assembly for upgrading or remediating semiconductor devices utilizing a remediation, adaptation, modification or upgrade chip in a piggyback configuration with a primary bare chip to achieve an upgrade, modification or adaptation of the primary chip or remedy a design or fabrication problem with the primary chip.

Abstract: A semiconductor chip is bonded to lead terminals via insulating layers. The semiconductor chip is electrically connected to the lead terminals in bonding parts on the tip of inner leads by bonding wires, respectively. Indentation having smaller width than that of the bonding parts are provided in the portion where the lead terminal is bonded to the insulating layer. A bent part is provided in the lead terminal is bonded to the insulating layer. Sealing the semiconductor chip, the lead terminals, the insulating films and the bonding wires by resin, a semiconductor device is completed.

Abstract: A lead frame for a semiconductor package. The lead frame includes a die pad and a plurality of leads. One surface of the die pad supports a silicon chip while the other surface has a plurality of annular grooves all having the same geometric center. The inner lead portion of the leads surrounds the die pad, but the die pad and the leads are on different planar surfaces.

Abstract: A ball grid array (BGA) semiconductor package includes a paddle, a semiconductor chip on the paddle, a plurality of first leads around a periphery of the paddle, a plurality of second leads attached to a lower surface of each of the first leads, a plurality of conductive wires electrically connecting the semiconductor chip and the first leads, a molding unit sealing the paddle, the semiconductor chip, the first leads, the second leads, and the conductive wires, except for a lower portion of the second leads, and a plurality of solder balls attached to the lower portion of the second leads.

Abstract: There is disclosed a plastic mold type semiconductor device comprising: a semiconductor chip, leads each having one end portion positioned outside the semiconductor chip in a manner spaced therefrom and the other end portion extending to the portion above the semiconductor chip, and bonding wires for connecting the semiconductor element and the leads, each of the leads being provided with a bonding portion positioned outside of the semiconductor chip. Even if the size of the semiconductor chip and that of the envelope are extremely close to each other, the lead has sufficient length within the molded plastic material so that the lead may not be pulled out.

Abstract: A cavity-type chip module. The module is formed with an adhesive joining layer of photoimageable material interposed between a metal stiffener and a laminate top layer with a central aperture defined in the top layer. The photoimageable material is exposed to actinic radiation, except for an area corresponding to the aperture in the top layer. The unexposed area of photoimageable material is developed away to form a window in the joining layer. The top layer, joining layer, and stiffener are laminated together with the window and aperture aligned, and with a portion of the stiffener spanning the aperture to define a cavity in the resulting substrate. The removal of the unexposed photoimageable material, and the selective exposure of the joining layer to actinic radiation, keep the cavity free of photoimageable material and inhibit bleeding of the photoimageable material into the cavity from its inner edge.

Abstract: A flexible printed circuit unit includes a flexible printed circuit board having one or more electronic parts mounted on a front surface thereof. A reverse side reinforcing plate is provided at a location of the reverse side of the flexible printed circuit board corresponding to a region in which the electronic parts are mounted. An upper reinforcing structure is provided on the front surface of the flexible printed circuit board for covering at least one of the electronic parts.

Abstract: This invention relates to a semiconductor package having a separated die pad, which is comprised of an integrated circuit chip having a plurality or bonding pads mounted on its surface; a die pad providing its upper surface for the chip to be attached to, which comprises the first plate and second plates disposed a space apart, and an adhesive film attached to the under surface of the first and second plates; a plurality of leads, the near end portions of the leads which can be electrically connected to the bonding pads of the chip, wherein the far end portions are exposed to the exterior surface of the semiconductor package; and a package body made of insulating material, wherein the chip, the die pad and the leads including parts of their near end portions are encapsulated.

Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component with a short signal pass length to achieve a high frequency operation. The packaging and interconnection is formed of a contact structure made of conductive material and formed on a contact substrate through a photolithography process, a contact trace formed on the contact substrate and electrically connected to the contact structure at one end, and the other end of the contact trace is extended toward an edge of the contact substrate, a connection target provided at an outer periphery of the contact structure to be electrically connected with the other end of the contact trace, an elastomer provided under the contact substrate for allowing flexibility in the interconnection and packaging of the contact structure, and a support structure provided between for supporting the contact structure, the contact substrate and the elastomer.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have a PECVD SiO2 layer formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, an insulating PECVD SiO2 layer is formed on the bonding wires to prevent short-circuits with adjacent wires. An SiO2 layer is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A semiconductor device includes a semiconductor element having a plurality of electrodes on an upper surface thereof. A first substrate has a plurality of conductors on an upper surface thereof. The first substrate is mounted on the upper surface of the semiconductor element and is smaller in area than the semiconductor element. A second substrate has a plurality of solderballs on an upper surface thereof. The second substrate is mounted on the upper surface of the first substrate and is smaller in area than the first substrate. An adhesive layer is disposed between the first substrate and the semiconductor element, and causes the first substrate to be affixed to the semiconductor element. A plurality of metal wires electrically couple the electrodes on the semiconductor element to the conductors on the first substrate. A sealing frame is attached to the semiconductor element. A cap is bonded to both the second substrate and the sealing frame.

Abstract: The power semiconductor component has a semiconductor body which is electrically supplied through a contact clip. A solder ball connects the semiconductor body to the contact clip. The contact clip has a meandering electrical supply to a solder land, into which the solder ball is inserted.

Abstract: A lead frame and a semiconductor package using the lead frame are disclosed in which one lead frame can be used to perform the package process regardless of the size of a chip. The size of the chip can be varied within the limit that the number of bonding pads of the chip does not exceed the number of corresponding inner leads. The lead frame includes a plurality of tie bars extended toward the center from edges of a lead frame body, a die pad supported by the tie bars on which a semiconductor chip can be bonded and a plurality of inner leads disposed around the die pad. The tie bars, the die pad and the inner leads are preferably in the same plane. The inner leads are electrically coupled with bonding pads of the chip. A plurality of outer leads respectively coupled with the inner leads and exposed outside a molded package.

Abstract: A stress-isolated integrated circuit includes a semiconductor die (24) having first and second surfaces (28, 32) and a semi-circumferential trench (44) formed into the first surface of the die to define a stress-isolated region (48). At least some of the active IC components are located in the stress-isolated region. A cavity (46) is formed into the second surface of the die, the cavity being sized so that the trench opens into the cavity to create a cantilevered stress-isolated region extending from the remainder of the die. The second surface of the die is secured to a lead frame (36), the lead frame having bond wires (42) secured to bond pads (26) on the die. A molding compound (54) encapsulates the die, the cap, the bond wires and a portion of the lead frame to create a molded IC device (20).

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: A semiconductor device comprises a semiconductor chip having a major surface, a plurality of bonding pads provided on the major surface of the semiconductor chip, an adhesive tape provided on a selected part of the major surface of the semiconductor chip, and a plurality of inner leads mounted on the adhesive tape, each adhered at a lower surface thereof to the adhesive tape. The device further comprises a wiring lead, bonding wires, and a resin-molded package. The wiring lead has at least one end portion and spaced apart from the major surface of the chip. The at least one end portion is depressed from the inner leads toward the semiconductor chip, located outside the adhesive tape and formed integral with at least one of the inner leads.

Abstract: A thin enhanced TAB BGA package includes an IC chip, a substrate having a center opening and one side laid with a metallic circuitry which has a plurality of inner leads extending to the center opening, a plurality of metallic solder balls attached to the substrate at one side and coupling with the metallic circuitry, and a heat dissipating member adhering partly to the a side of the chip and partly to the substrate for heat dissipating, positioning and supporting the IC chip and the substrate. The IC chip has a another side exposed to ambience to add heat dissipating effect. The heat dissipating member has about same thickness as the substrate. Hence the ball grid array package may be made of a small size and thin thickness. The adhering of heat dissipating member to the chip and substrate may be done at the same process of bonding the inner leads to the IC chip. Thus the thin enhanced TAB BGA package of this invention may be produced at low cost without additional equipment or process.

Abstract: A method for producing chip scale IC packages includes the step of mounting a lead frame panel on a temporary support fixture in order to provide support and protection during the manufacturing process. An embodiment of the temporary support fixture includes a sheet of sticky tape secured to a rigid frame. The rigid frame maintains tension in the sheet of sticky tape to provide a stable surface to which the lead frame panel can be affixed. Installation of IC chips and encapsulation in protective casings is performed as in conventional IC package manufacturing. If encapsulant material is to be dispensed over the IC chips, an encapsulant dam can be formed around the lead frame panel to contain the flow of encapsulant material. The temporary support fixture can be used in any IC package manufacturing process in which lead frames require supplemental support.

Abstract: A leadframe includes a leadframe finger support for supporting elongate leadframe fingers. These elongate leadframe fingers are subject to damage prior to or during the assembly process. Through the provision of the leadframe finger support, the leadframe fingers may be supported at an intermediate position along their length as necessary to prevent bending. The support may be severed from the dam bar in the course of singulation.

Abstract: A lead frame and method of making the same are provided. The lead frame includes a die mounting portion, first and second pairs of tie bars, and first and second tie bar bridges extending between respective second extension portions of each tie bar pair. First and second pairs of tie bars are mechanically coupled to respective first and second ends of the die mounting portion. Each of the tie bars includes a first extension portion, a second extension portion, a tie bar span mechanically coupled to the first end of the die mounting portion via the first extension portion, a tie bar flap formed along a longitudinal reinforcement crease, and a lateral reinforcement portion extending from said first extension portion to said die mounting portion. The tie bar flap and the tie bar span lie in intersecting planes and are connected along the longitudinal reinforcement crease between the first extension portion and the second extension portion.

Abstract: In a lead frame with a reinforcing ring surrounding a semiconductor element which are electrically connected to leads through electrodes is integrally formed through suspending portions, reinforcing portions for reinforcing the suspending portions are provided on the suspending portiones. Upon application of a lead frame forming technique in which a laminate plate of three or more layers is used as a base, and inner leads are formed at one side while outer leads are formed by the surface layer at the other side, the lead frame is formed by forming a ring in place of outer leads, for example. A semiconductor package is formed by mounting the lead frame on a semiconductor chip.

Abstract: A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

Abstract: A semiconductor element such as a CCD chip is contained in a recess portion of an opaque package made of plastic, and the upper surface thereof is covered with a transparent cap made of plastic. The cap has a different thermal expansion coefficient from that of the package and is formed in a thickness of 0.5 mm which is thinner than that of the prior art. The semiconductor element is connected with leads and these leads project outside the package. This semiconductor device is mounted to a printed circuit board.

Abstract: A resin mold type semiconductor device, which is crack resistant and can be made relatively thin, includes a semiconductor chip, a lead member arranged in a manner such that an one side face of a head portion thereof touches a surface of the semiconductor chip, a wire for electrically connecting the surface of the semiconductor chip and another side face of the lead member, an adhesive member for adhering the one side face of the lead member and a peripheral face of the semiconductor chip, and a package for molding the semiconductor chip, a part of the lead, the wire and the adhesive member by synthetic resin. Further, the lead member may be provided with a concave portion in the one side face and possibly also a groove extending from the concave portion to an end of the lead.

Abstract: A lead frame and a semiconductor chip package includes supporters on a lead frame paddle and tiebars using the same for preventing undesired paddle bending which may occur due to the pressure of an epoxy molding compound during the molding process. The supports also allow improved heat dissipation during the molding process of the semiconductor chip package and mounting process of the package onto a printed circuit board.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.

Abstract: A multi-chip stack package does not include a die pad. The elimination of the die pad provides more room for elements in the package which. Thus, a balanced inner package structure can be achieved, and a poor molding which may expose one of the package elements can be avoided. In the package, an upper chip is bonded to the top surface of a lower chip. To stabilize the chips, auxiliary or inner leads of a lead frame attach to the top surface of a lower chip. This shortens wire lengths between the chips and the inner leads. The shorter wires reduce wire loop heights and thus reduce the probability of exposing wires in a subsequent transfer-molding. A multi-chip stack package which includes an auxiliary lead(s) is also disclosed. The auxiliary leads attach to the top surface of the lower chip and can provide a stable support of a semiconductor chip and prevent the chip from tilting and shifting in transfer-molding. An auxiliary lead can be between the lower and upper chips.

Abstract: A tape carrier for TAB includes a base material having an insulating property and an elongated shape. The base material has peripheral edges defining an opening for disposing an integrated circuit component. A first pair of portions of the peripheral edges face each other, and a second pair of portions of the peripheral edges face each other. A plurality of connection leads extend from the first pair of portions into the opening. A plurality of dummy leads extend from the second pair of portions into the opening.

Abstract: A semiconductor device assembly having a support such as a lead frame paddle comprises a coating thereon to reduce or eliminate the flow of die attach adhesive from under the die and over bond sites or encapsulation regions. Thus undesirable effects resulting from this flow of adhesive, such as wire bonding problems and encapsulation problems, are reduced. A method for forming the assembly is also described.

Abstract: A semiconductor lead frame, and a semiconductor package fabricated using the lead frame, are provided. The lead frame includes side rails; patterns of lead fingers; and multiple die mounting paddles. Each die mounting paddle is configured to mount a semiconductor die for wire bonding to an associated pattern of lead fingers. In addition, each die mounting paddle includes support members on opposing sides, each having at least two downset segments. The downset segments of the support members offset the die mounting paddles from the lead fingers. In a first lead frame embodiment, the support members include downset segments oriented at opposing angles with respect to a longitudinal axes of the mounting paddles. In a second embodiment, the support members include two or more downset segments oriented along axes that are generally parallel to the die mounting paddles.

Abstract: A semiconductor package includes a base plate, a semiconductor die having top and bottom surfaces, the bottom surface being mounted to the base plate, and a conductor tab having first and second ends, the first end being adapted to communicate with and couple to external circuitry, the second end including a relatively wide foot having a plurality of finger portions separated by gaps, the finger portions being mounted to an covering a substantial portion of the top surface of the semiconductor die.

Abstract: In encapsulating an optocomponent a leadframe (51) is used for the electrical connection of the component, the leadframe having a flag (53), to which the main body of the optocomponent is attached. The flag (53) is located asymmetrically at an outer edge of the leadframe and is, in the encapsulating operation, placed close to a sidewall in a mould cavity in a mould. Thereby an optical interface of standard type can be obtained in the wall of the capsule. Further, the flag (53) is flexibly attached, by means of zigzag-shaped bridges (67), to other portions of the leadframe so that the flag and thus the optocomponent will have a possibility to be resiliently and flexibly displaced a little at the positioning thereof in the mould cavity in the mould in relation to the other portions of the leadframe, in particular to its outer frame portions (61) and bridge portions (59).

Abstract: The invention relates to a single piece leadframe that can be used in current semiconductor device production. The leadframe has a plurality of segments in a horizontal plane, a chip mount pad in a different horizontal plane, and another plurality of segments connecting said chip mount pad with said leadframe. The latter plurality of segments has a geometry designed so as to tolerate bending and stretching beyond the limit of simple elongation based upon the inherent material characteristics. The chip mount pad of said leadframe provides direct thermal contact to an external heat conductor or heat sink by being designed so as to extend through the encapsulating package. The exposed chip pad can also be used electrically as a ground connection.

Abstract: The present invention is directed to a packaged semiconductor chip that utilizes a multilevel leadframe that positions the lead fingers close to the bond pads while positioning the bus bars on a different level and behind or outboard of the lead finger connections such that it is unnecessary for any wires to cross over the bus bars or the lead fingers. The leadframe may comprise a multi-part frame, or be fabricated from a single sheet of metal.

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads on its top surface, a plurality of inner leads located above the semiconductor chip and electrically connected to the bonding pads by wire, a plurality of outer leads extending from the respective inner leads, and at least one bus bar formed lower than the inner leads, to prevent electrical shorts and improve reliability of the package.

Abstract: In a tape carrier, one or a plurality of overhang patterns, each being shorter than a length that reaches an edge of a semiconductor chip, is provided in an area where the pitch between adjacent inner leads is relatively large or in a corner area of the device hole where inner leads are not provided, depending upon the size of such area. An average of resin sealing ranges on the rear surface of the tapes is 0.8 mm and the diversification is 0.06 mm.

Abstract: A low-stress silicon-backed light valve package assembly that includes a matched coefficient of thermal expansion (CTE) substrate with a CTE no greater than 300% of the CTE of silicon, a silicon-backed light valve adhered to the matched CTE substrate by a soft adhesive layer, a flexible circuit adhered to the matched CTE substrate and electrically connected to the silicon-backed light valve, an encapsulant dam surrounding the silicon-backed light valve and a soft encapsulant layer filling the cavity defined by the encapsulant dam. Both the soft encapsulant layer and the soft adhesive layer have a Shore A hardness of less than 5. The combination of a soft encapsulant layer, soft adhesive layer and matched CTE substrate insure sufficiently low mechanical stress levels to avoid the presence of optical interference patterns in the light valve display.