Abstract: The present invention is directed toward apparatus and methods for providing substrate structures having metallic layers for microelectronics devices. In one embodiment of the invention, an apparatus includes a substrate layer, and a metallic layer attached to the substrate layer, the metallic layer being attachable to a bottom surface of the microelectronics device. The metallic layer may advantageously provide a surface free from voids or irregularities for improved attachment of microelectronics devices. The metallic layer may also provide improved conduction of thermal energy away from the device, shielding from electromagnetic interference, a vapor barrier between the device and the substrate, and may serve as a convenient ground channel. In one embodiment, the metallic layer may be continuous layer. Alternately, the metallic layer may be segmented into a plurality of closely-fitted pieces, or a plurality of spaced-apart pieces separated by expansion joints.

Abstract: A leadframe structure for use with an integrated circuit chip, comprising a chip mount pad having an area smaller than said chip intended for mounting; a plurality of support members, each attached externally to the perimeter of said pad and internally to said leadframe; and each said support member having at least one portion located within the perimeter of said chip in a configuration operable to absorb thermally induced deformations of said support member.

Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.

Abstract: A semiconductor chip is mounted over a flexible base plate. The base plate has an array of bubbles. Each bubble is coated with a metal tip, which is coupled by printed and leads bonds to the bonding pads of the chip. The metal tips are for making contacts to a printed circuit board when the package is mounted to a printed circuit board.

Abstract: An improved flip chip assembly is disclosed of the type where a semiconductor chip having a certain thermal expansion coefficient is directly mounted via solder bumps on the metallization pattern of a circuit substrate having a different thermal expansion coefficient. A base layer comprised of a polymer material is disposed over the surface of the chip, between the chip and the substrate, and the solder bumps are placed over the base layer; the base layer modifies the effective thermal expansion coefficient of the solder bumps to approximate that of the substrate, thus reducing the thermal expansion coefficient differential at the junction of the chip and the substrate.

Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.

Abstract: The present invention relates to a stress-free lead frame (1) for a semiconductor. The stress-free lead frame (1) is provided with a stress-relief means (15) and an interlocking means (16) at the outer periphery. The stress-relief means (15) is capable of accommodating expansion and compression while the interlocking means (16) take care of shock and vibration during handling to thereby eliminate delamination of the lead frame (10).

Abstract: An embodiment of the invention in a quad flat no-lead package is described. The package is produced by encapsulating an integrated circuit chip, a die pad to which the chip is affixed, and leads which are connected to the chip in a molding compound. Leads are positioned on all four sides of the package, the exposed (bottom) portions of the leads are coplanar with the bottom of the package, and the leads do not extend, or extend only slightly, beyond the area of the package. The package includes a die pad also having an exposed (bottom) portion that is coplanar with the bottom of the package. The top portions of the leads are coplanar with the top surface of the die pad, and are flat.

Abstract: In apparatus and method for shaping a lead frame for a semiconductor device, there are provided a lower die having a concave shape for forming a step portion on the lower surface of the lead frame through a slope shape, an upper die having a convex shape which is downwardly moved to press a part of the lead frame in cooperation with the lower die and form a step portion through a slope shape on the upper surface of the lead frame, and a press portion which is disposed around the upper die and presses the outer portion of the lead frame at the outside from the semiconductor element mount portion, wherein the lower die is divided into an outside portion having an inside surface whose outlook is coincident with that of the inside surface of the press portion, and an inside portion located so as to be adjacent to and extend inwardly from the outer portion, and the outside portion and the inside portion are designed so as to be relatively movable in up-and-down direction.

Abstract: A process for forming a true chip scale package comprising the sandwiching of a silicon wafer with a large number of identical die therein between top and bottom metal contact plates of the same size as the wafer. The sandwich is secured together as by soldering, and the die and contact plates are singulated in the form of a final chip scale package. The edge of each chip may have an insulation band formed thereon. Slots may be formed in the top contact to define, with the edge saw cuts, a separate contact area on each top contact.

Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.

Abstract: The present invention relates to a semiconductor package and a fabricating method thereof, more particularly, to a chip size package of a wafer level and a fabricating method thereof. Accordingly, the present invention eases sufficiently the thermal stress generated from the difference of heat expansion rates between the semiconductor chip and the PCB substrate, increases the reliance of the wires as the stress on the wires are greatly reduced, simplifies the fabrication process, and reduces the product cost owing to simplified processes as equipments for metal deposition, metal plating and etch arc not necessary. The present invention, as embodied and broadly described, the present invention includes a semiconductor chip, a chip pad in a first area of the semiconductor chip, a stress-easing layer formed in a second area of the semiconductor chip, a conductive wire connecting the chip pad to the stress-easing layer, and an electrical conductor on the conductive wire over the stress-easing layer.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A semiconductor package and a manufacturing method prevent electrical shorts that otherwise result from bonding wires contacting the edge of a semiconductor chip. An insulating region at the edge of a semiconductor chip prevents the shorts. One method for forming the insulating region leaves a polyimide layer on the scribe area of a wafer and cuts through the polyimide layer. To avoid chipping, the cutting uses a fine grit blade and a slow cutting rate. An alternative process removes the polyimide from the scribe area and forms the insulating region on the edge of the semiconductor chip. A potting method can deposit the insulating region on a semiconductor chip after cutting a wafer and after attaching a separated chip to a substrate. Alternatively, plotting or printing can apply insulating material on the wafer. A cutting process then cuts through the insulating material and the wafer and leaves insulating regions on each separated chip.

Abstract: A semiconductor device comprising a patterned wiring including a connector for external connection formed on an elongate base film, a semiconductor element or the semiconductor element and a component other than the semiconductor element mounted on and electrically connected with a portion for connection of the patterned wiring, an elongate reinforcement member provided on a surface of the base film opposite to a surface on which the patterned wiring is formed, the reinforcement member having sprocket holes at positions corresponding to the lengthwise sides of the base film, wherein the reinforcement member is further provided on said opposite base film surface in a region corresponding with a region on which the connector for external connection is formed.

Abstract: A substrate for an electronic circuit, the substrate comprising a wafer of silicon Si having a top face covered in an electrically insulating layer of silicon nitride SiN, said electrically insulating layer of silicon nitride supporting one or more conductive tracks obtained by metallizing the top face of said electrically insulating layer for the purpose of enabling one or more electronic components to be connected.

Abstract: A multiple dielectric device and its method of manufacture overlaying a semiconductor material, comprising a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.

Abstract: A component for making microelectronic units includes a grid of interspersed leads with ends of the various leads being connected to one another by frangible elements. One end of each lead is bonded to a top element and the other end of each lead is bonded to a bottom element. The top and bottom elements are moved away from one another, thereby breaking the frangible elements and deforming the leads towards a vertically extensive disposition. A flowable composition such as dielectric material may be injected around the leads during or after the moving step. The resulting unit may be used to form permanent or temporary connections between microelectronic elements.

Abstract: A package is provided for surface mounting a semiconductor device to a board such that a first pad of the semiconductor device is operatively connected to a second pad on the board. The package includes a paddle having a front side and a back side with the front side being mated to the semiconductor device and at least partially enclosed in an encapsulant material and the backside being substantially exposed. In addition, the package has a region of the paddle that is at least partially isolated by the encapsulant material and aligned with the second pad an interconnect connected to the first pad of the semiconductor device and bonded to the region such that a conductive path is formed with the first pad, the region and the second pad when the backside is mated with the board.

Abstract: An encapsulated device and method for making such encapsulated device containing a bladder disposed between a wall of the case and the encapsulant. The bladder defines a space devoid of encapsulant and contains a collapsible insert such as an open cell foam material, thereby allowing the unimpeded thermal expansion of the encapsulant. By reducing thermal expansion stresses on the encapsulated devices, the reliability of the encapsulated device is improved.

Abstract: This invention prevents deterioration in characteristics of a semiconductor device having a lead frame that is thin and uniform in thickness. More specifically, this invention relieves resin distortion caused by a difference in thermal expansion coefficients between the lead frame and the sealing resin in order to prevent the characteristic deterioration caused by some factors such as moisture invasion from outside and mechanical pressure. A lead frame for a resin-sealed semiconductor device of this invention is composed of an element-mount part, a horizontal part for fixing the lead frame for resin sealing, and a central lead having side leads formed in parallel on both sides thereof. The element-mount part, the horizontal part and the central lead are formed integrally. In the lead frame, at least one pair of resin-anchoring parts are formed on two opposing sides on the periphery of the element-mount part.

Abstract: A strip mainly includes a plurality of guide holes, a plurality of position holes, a plurality of separation holes, a plurality of second slots and a plurality of substrate areas. Guide holes are arranged on two sides of the strip for carrying during processing, and position holes are arranged at four corners of the strip for positioning on the machine during processing. Separation holes and slots are to be contiguous to the substrate areas and separate the substrate areas from one another so that the discontinuous warpage of the substrate area affects the peripheral substrate areas. Therefore, it can reduce the chance of breaking chip in the substrate area. The two ends of the substrate are adjacent to the slots to reduce the stress of other substrates in the longitudinal direction actuating the chip during heat treatment in processing. The strip further includes a metal layer surrounding the substrate areas to increase the stiffness of the entirety of the strip.

Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component. The packaging and interconnection includes a contact structure made of conductive material and formed on a contact substrate, a contact trace horizontally extended on the contact substrate and connected to the contact structure, a contact pad formed on a bottom surface of the contact substrate remote from the contact structure, a contact target provided at an outer periphery of the contact structure in a side-by-side fashion to be electrically connected with the contact pad, a conductive lead for electrically connecting the contact pad and the contact target, an elastomer for achieving flexibility, and a support structure for supporting the contact structure, contact substrate and elastomer.

Abstract: The present invention relates to a packaged semiconductor that includes a semiconductor having a plurality of leads extending therefrom. The leads are formed by mounting the semiconductor device in a lead frame and punching and sealing the leads in the semiconductor device using a resin, wherein the leads have been bent to a predetermined configuration. A connector is further provided to connect leads to the frame, and the connector is bent at substantially the same time as when the leads are bent to the predetermined configuration. According to the packaged semiconductor, a lead is not cut off from a lead frame, and the connection between the two can be maintained even after a bending process is finished.

Abstract: A tape carrier package formed by a TAB technique is provided. This tape carrier package includes a semiconductor chip and a TAB tape. The TAB tape has a rectangular device hole in which the semiconductor chip is situated, and inner leads extending inward in the device hole and bonded to the electrode bumps of the semiconductor chip. The inner leads (corner leads) at each corner of the device holes are reinforced by reinforcing leads.

Abstract: A tape carrier for TAB includes a base material having an insulating property and an elongated shape. The base material has peripheral edges defining an opening for disposing an integrated circuit component. A first pair of portions of the peripheral edges face each other, and a second pair of portions of the peripheral edges face each other. A plurality of connection leads extend from the first pair of portions into the opening. A plurality of dummy leads extend from the second pair of portions into the opening.

Abstract: The present invention includes a package for housing an integrated circuit device. The present invention also includes leadframes and methods for making such packages. In one embodiment, the package includes an integrated circuit device on a metal die pad. A metal ring is between the die pad and leads and surrounds the die pad. The ring is connected to the die pad by a nonconductive adhesive tape. Encapsulant material covers the entire structure, except for portions of the leads. The ring is electrically connected to a lead identified for connection to an external power voltage supply. The ring in turn is electrically connected to a power voltage input pad on the integrated circuit device. The potential of the die pad may float, or the die pad may be electrically connected through a lead to an external ground voltage. The package is made from a leadframe that has a die pad, a metal ring between the die pad and radiating leads, and a nonconductive adhesive tape that connects the ring to the die pad.

Abstract: In encapsulating an optocomponent, a leadframe is used for the electrical connection of the component, the leadframe having a flag, to which the main body of the optocomponent is attached. The flag is located asymmetrically at an outer edge of the leadframe and is, in the encapsulating operation, placed close to a sidewall in a mold cavity in a mold. In this way, an optical interface of standard type can be obtained in the wall of the capsule. Further, the flag is flexibly attached, by zigzag-shaped bridges, to other portions of the leadframe so that the flag and thus the optocomponent will have a possibility to be resiliently and flexibly displaced a little at the positioning thereof in the mold cavity in the mold in relation to the other portions of the leadframe, in particular to its outer frame portions and bridge portions.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: A molded plastic package for semiconductor devices incorporating a heat sink, controlled impedance leads and separate power and ground rings is described. The lead frame of the package, separated by a dielectric layer, is attached to a metal heat sink. It has more than one ring for power and ground connections. The die itself is attached directly onto the heat sink through a window on the dielectric and provides high power dissipation. The package is molded using conventional materials and equipment.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: Frame F comprises plural lead frames 10 arranged through grid-leads L in matrix. Semiconductor devices are mounted on individual lead frames 10 of frame F, respectively and collectively molded with molding compound. Thereafter, the collectively molded semiconductor devices are cut at grid-leads L by means of dicing saw so that individual semiconductor packages are obtained. The frame F further has groove portions. The groove portions are formed by half-cutting by etching a metal of frame F from the front or back at areas corresponding to grid-leads, so that grid-frames are made thin. When a width of groove portions is larger than a width of dicing saw, cut burrs are reduced. When a width of groove portions is smaller than a width of dicing saw, the occurrence of metal powder dusts is restrained and time required for cutting becomes smaller.

Abstract: A printed circuit board, on which an electronic component with leads is mounted, includes a first conductive layer; an insulating layer formed on the first conductive layer; a second conductive layer formed on the insulating layer; and a buffer region. The second conductive layer is provided with pads to be connected to the leads of the electronic component. The buffer region has a thermal expansion coefficient lower than the first conductive layer and is arranged between the first conductive layer and the insulating layer to ease thermal expansion of the first conductive layer.

Abstract: A metallic or an electrical trace having a terminus and a stress relief bend formed in the trace adjacent the terminus. The electrical trace may have a portion carried by a flexible substrate to form a flexible circuit. The stress relief bend may be free floating and extend from the flexible substrate or may be encapsulated by the flexible substrate. The electrical circuit and the flexible circuit each have a generally planar portion extending in the X and Y axis, with the stress relief bend projecting into the Z axis. This allows electrical traces to be spaced with a very narrow pitch because the stress relief bend does not consume any valuable real estate on the flexible circuit or the substrate to which the electrical trace is applied.

Abstract: A leadframe for making an electric connection to a semiconductor die contains a plurality of notches which correspond to the edges of the die. Shorts are thereby prevented between the leadframe and electrical elements near the edge of the die, even when the leadframe is bent in the direction of the die to make a surface mount package. Alternatively or additionally, the leads in the leadframe may contain moats which prevent the epoxy or solder used to attach the leadframe to a die from spreading outward and thereby creating electrical shorts with other leads.

Abstract: A lead frame and method of making the same are provided. The lead frame includes a die mounting portion, first and second pairs of tie bars, and first and second tie bar bridges extending between respective second extension portions of each tie bar pair. First and second pairs of tie bars are mechanically coupled to respective first and second ends of the die mounting portion. Each of the tie bars includes a first extension portion, a second extension portion, a tie bar span mechanically coupled to the first end of the die mounting portion via the first extension portion, a tie bar flap formed along a longitudinal reinforcement crease, and a lateral reinforcement portion extending from said first extension portion to said die mounting portion. The tie bar flap and the tie bar span lie in intersecting planes and are connected along the longitudinal reinforcement crease between the first extension portion and the second extension portion.

Abstract: A semiconductor lead frame, a semiconductor package, and a method for fabricating semiconductor packages, are provided. The lead frame includes side rails and multiple patterns of lead fingers. The lead frame also includes die mounting paddles associated with the patterns of lead fingers, and support members that attach the mounting paddles to the side rails. The mounting paddles include stiffening members such as indentations, ridges or corrugations formed in a die mounting surface thereof. The stiffening members prevent bowing of the mounting paddles, provide an increased surface area for bonding dice to the mounting paddles, and allow the mounting paddles to flex to accommodate thermal stresses. The support members for the mounting paddles can also have a stiffening cross sectional configuration to help maintain a planar orientation and location of the mounting paddles.

Abstract: In the present semiconductor device, a chip with an LSI circuit is secured to a board 3 (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.

Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by P the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.

Abstract: A chip carrier constituted of an organic laminate which incorporates structure compensating for thermal deformation of the carrier. Moreover, disclosed is a method of counteracting the thermal deformations encountered by chip carriers, especially during solder reflow, which is predicated on the uniformly, equidistant positioning of metal-plated through-holes (PTH) formed in the chip carrier relative to contact pads. A plurality of plated through-holes (PTH) are positioned equidistantly relative to contact (BGA) pads on a surface of a substrate which is constituted of an organic laminate material, so as to be able to control both in-plane and out-of-plane thermal deformations in the chip carrier material which may be occasioned in a solder reflow furnace or oven.

Abstract: A high density integrated circuit module having complex electrical interconnection is described, which includes a plurality of stacked level-one integrated circuit devices, wherein each level-one device includes an integrated circuit die and a plurality of electrical leads extending from the die; and a plurality of non-linear rails adapted to electrically and thermally interconnect selected leads of selected stacked level-one devices within the module, wherein at least some of the plurality of non-linear rail include a lead interconnect portion which is adapted to at most partially surround and receive a selected lead from one of the stacked level-one devices. Other embodiments include TSOP modules having leads reduced in width to allow additional selected non-linear rails to interconnect with select leads in the module. Strain relief for the rail/circuit board substrate connection in harsh environment applications is also provided.

Abstract: The chip module is particularly suitable for implanting in a smart card body. The module has a carrier and a chip fitted on the carrier. A pedestal or base-type elevation formed on the carrier laterally surrounds the chip completely or partly.

Abstract: A semiconductor electronic device comprises a chip of a semiconductor material, a set of metal conductors adjacent to the plate, a set of wire leads joining selected points on the chip to the metal conductors, and a supporting metal plate formed of three portions having a total surface area which is substantially less than the surface area of the chip, and forming a H-shaped supporting structure. All this, except the ends of the metal conductors, is encapsulated within a plastic material body.

Abstract: A molding equipment for a resin shielding semiconductor device includes a lower platen having a lower cavity, and an upper platen having an upper cavity, and a recess which is adjacent to the upper cavity. A lead frame has an opening serving as a passage of resin. The opening has one end rounded.

Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.

Abstract: This is a semiconductor device made by using a film carrier tape and method of making the same, wherein the package size is close to the chip size and connection portions for electrodes of a semiconductor chip are not exposed. Electroplating is performed in a state where connection leads 24, plating leads 26 and plating electrodes 28 are all conductive, the connection leads being are formed within a region to be filled with a molding material 36 and being connected to electrodes 42 of a semiconductor chip 40 and pad portions 22, the plating leads 26 being connected to the connection leads 24, and plating electrodes 28 being connected to the plating leads 26. The connection portions 29 are punched out into the region to be filled with the molding material, the connection leads 24 and the electrodes 42 are connected, and the molding material 36 is poured in. The end surfaces of the connection leads 24 that are exposed from the holes 32 are also covered by the molding material 36 so as not to be exposed.

Abstract: Thin semiconductor die, approximately 0.004 to 0.007 inches thick, are positioned substantially on the neutral plane of a smart card, the neutral plane defined as the plane of substantially no mechanical strain during flexure of the smart card, thereby providing smart cards having improved resistance to mechanical flexure, and/or smart cards having improved RF performance.

Abstract: A lead frame and a semiconductor device wherein a through hole is formed in the center of a semiconductor chip-mounting surface of a chip pad at the center of the lead frame, the through hole being tapered or being one which corresponds to a surface area that is greater on the surface of the chip-mounting surface of the chip pad than on the surface of the side opposite to the chip-mounting surface thereof. This prevents the occurrence of cracks in the sealing plastic portion in the step of reflow soldering of the lead frame to the substrate.