Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.

Abstract: A semiconductor module includes a semiconductor chip, a lead frame having lead fingers, and a down set member within an encapsulant for reduce warpage and providing a more planar package by balancing thermal stress between the lead fingers and the encapsulant. The down set member can be a bent portion of the lead frame. It can also be a separate body, such as a dummy semiconductor chip.

Abstract: An integrated circuit assembly 10 is provided, including a substrate 14 having at least one substrate contact surface 18, an integrated circuit device 12 having at least one first contact surface 16, and a bar bond element 22. The bar bond element 22 provides communication between the at least one substrate contact surface 18 and the at least one first contact surface 16. The bar bond element 22 includes a conductive plate element 23 having an integrated circuit foot portion 24, a substrate foot portion 26 and a strain relief loop 46 positioned between the integrated circuit foot portion 24 and the substrate foot portion 26.

Abstract: An LOC die assembly including a die dielectrically adhered to the under of lead frame. The adhesive is applied over a minimum cross-sectional area and number of attachment points to maximize flexure of leads extending over the active surface of the die. In this manner, flexure of the leads to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant is maximized, and the point stresses on the active surface caused by the filler particles are reduced by the lead flexure.

Abstract: An encapsulated device and method for making such encapsulated device containing a bladder disposed between a wall of the case and the encapsulant. The bladder defines a space devoid of encapsulant and contains a collapsible insert such as an open cell foam material, thereby allowing the unimpeded thermal expansion of the encapsulant. By reducing thermal expansion stresses on the encapsulated devices, the reliability of the encapsulated device is improved.

Abstract: A quad flat non-leaded package comprises: a die pad having a first upper surface and a corresponding first lower surface thereon a plurality of interlacing slots are formed, each of the interlacing slots extending to the edges of the die pad to form a plurality of island-like blocks; a plurality of leads disposed at the periphery of the die pad, wherein each of the leads has respectively a second upper surface and a corresponding second lower surface coplanar to the surface of the island-like blocks; a chip having an active surface and a corresponding back surface adhered onto the first upper surface of the die pad; and a molding compound encapsulating the chip, the second upper surface, the first upper surface and the interlacing slots while exposing the surface of the island-like blocks and the second lower surface of the leads.

Abstract: First pad electrodes for connection to leads and second pad electrodes for an internal interface, are provided over a main surface of a first LSI chip. Third pad electrodes of a second LSI chip and the second pad electrodes of the first LSI chip are respectively electrically connected to one another by wires. Circuits required as for a system LSI, which are not included in the first LSI chip, are placed over the second LSI chip, to implement a desired function used as for a system LSI by the two LSI chips. The system LSI is easily implemented by a semiconductor device wherein a plurality of LSI chips are sealed with a resin.

Abstract: A stress shield made of a material having a CTE similar to that of the material used in the fabrication of a microelectronic die, including but not limited silicon, molybdenum, and aluminum nitride, which abuts at least one corner and/or edge of the microelectronic die. When the stress shield is positioned to abut the microelectronic die corners and/or edges, the mechanical stresses on the microelectronic die are greatly reduced or substantially eliminated.

Abstract: A stress shield made of a material having a CTE similar to that of the material used in the fabrication of a microelectronic die, including but not limited silicon, molybdenum, and aluminum nitride, which abuts at least one corner and/or edge of the microelectronic die. When the stress shield is positioned to abut the microelectronic die corners and/or edges, the mechanical stresses on the microelectronic die are greatly reduced or substantially eliminated.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first conductive bump on a substrate, forming a second conductive bump on a semiconductor chip, forming a plurality of spaced apart dielectric supporting pads on one of the substrate and the semiconductor chip, mounting the semiconductor chip on the substrate to confine therebetween a gap, bonding together the first and second conductive bumps, and forming an insulating layer that fills in the gap and that encapsulates the supporting pads and the first and second conductive bumps.

Abstract: A leadframe including offsets extending from a major plane thereof. The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high temperatures or changes in temperature.

Abstract: A stress shield made of a material having a coefficient of thermal expansion similar to that of the material used in the fabrication of a microelectronic die, including but not limited to silicon, molybdenum, and aluminum nitride. The stress shield abuts at least one corner and/or edge of the microelectronic die. When the stress shield is positioned to abut the microelectronic die comers and/or edges, the mechanical stresses on the microelectronic die are greatly reduced or substantially eliminated.

Abstract: A semiconductor package with a crack-preventing member is proposed, in which a chip is mounted on a chip carrier by means of an adhesive and is electrically connected to the chip carrier. The crack-preventing member is formed at a proper position on the chip, and generates compression stress on the chip to sufficiently counteract tension stress produced from the chip carrier and adhesive in a molding process. This can effectively prevent the chip from cracking during molding, and thus improve the quality of fabricated products.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: A structure of a stacked-type multi-chip stack package of the leadframe, the shape of the stair-like inner leads can be regulated for the high and the amount of stacked chips and to match different bonding technology. The process for forming the present structure can be easily performed by visible equipment and materials, and the present structure can raise the reliability of bonding process. The present invention can stack multi-chip (more than two).

Abstract: A semiconductor device which includes a semiconductor chip, an insulating film formed on the semiconductor chip, a plurality of projected stress relaxation materials formed on the insulating film, projected electrodes covering at least tops of the stress relaxation materials, and wiring lines for electrically connecting the projected electrodes and element electrodes of the semiconductor chip.

Abstract: A stress-balancing layer formed over portions of a spring metal finger that remain attached to an underlying substrate to counter internal stresses inherently formed in the spring metal finger. The (e.g., positive) internal stress of the spring metal causes the claw (tip) of the spring metal finger to bend away from the substrate when an underlying release material is removed. The stress-balancing pad is formed on an anchor portion of the spring metal finger, and includes an opposite (e.g., negative) internal stress that counters the positive stress of the spring metal finger. A stress-balancing layer is either initially formed over the entire spring metal finger and then partially removed (etched) from the claw portion, or selectively deposited only on the anchor portion of the spring metal finger. An interposing etch stop layer is used when the same material composition is used to form both the spring metal and stress-balancing layers.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: In a semiconductor device, a lead frame is adhered to a base substrate for heat dissipation via an insulating layer, and an outward guided terminal portion is formed by perpendicularly upwardly bending an end of the lead frame after the mounting of one or more of power semiconductor elements on the lead frame. A recessed portion is formed beforehand in a portion of the lead frame to be bent, and it is ensured that the lead frame does not adhere to the surface of the base substrate in this recessed portion when the lead frame is adhered to the base substrate via the insulating layer before the bending of the lead frame. By virtue of this structure, manufacturing is simplified and manufacturing costs are reduced.

Abstract: A FPC board 400 is manufactured by patterning copper foils which are bonded onto both sides of a base film 410 having insulation and flexibility without an adhesive layer, and forming an input wiring 420a and an output wiring 420b on a mounting surface of an electronic component while forming a dummy wiring layer 422 on the surface opposite the mounting surface. A dummy wiring layer 422 is set to be slightly larger than an area where an IC chip 450 is mounted, and has moisture resistance and light shielding properties. An input electrode 450a of the IC chip 450 is electrically connected to the input wiring 420a and an output electrode 450b is electrically connected to the output wiring 420b through electrically conductive particles 460a dispersed into an adhesive agent 460, such as an epoxy resin, at an appropriate ratio, and the adhesive agent 460 encapsulates the connection regions.

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions.

Abstract: A semiconductor. device comprises a semiconductor chip on which a plurality of grooves are defined, thus acting as a resisting member, the effect of which is to prevent the semiconductor chip from bending. Consequently, the thickness of the lower portion of the plastic layer becomes greater, thereby preventing cracks from occurring on the semiconductor chip.

Abstract: A lead frame device having a lead frame made of copper, copper alloy or copper compound having a die pad area, within which a chip is to be mounted, and having a multiplicity of leads, which are arranged around the die pad area; and having a die pad made of silicon which is mounted in the die pad area on the lead frame to accommodate the chip.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device (10) having a semiconductor chip (12) with electrodes (16), a stress-relieving layer (14) prepared on the semiconductor chip (12), a wire (18) formed across the electrodes (16) and the stress-relieving layer (14), and solder balls (19) formed on the wire (18) over the stress-relieving layer (14); and a bare chip (20) as a second semiconductor device to be electrically connected to the first semiconductor device (10).

Abstract: An ultra-thin semiconductor package device comprises a heat-resistant film-type adhesive support tape which connects a semiconductor chip to a plurality of individual lead frames, wherein each lead frame is connected to an associated one of a plurality of electrode pads of the semiconductor chip by a plurality of bonding wires. An encapsulating molding material provides environmental protection for the completed package. Within the encapsulating molding, the semiconductor chip is mounted on a same underside of the support tape as the plurality of lead frames, such that the bottom of the semiconductor chip is aligned with the bottom of an encapsulating molding, and the height of a loop in each bonding wire is minimized.

Abstract: An integrated circuit carrier includes a plurality of receiving zones. Each receiving zone includes electrical contacts and each receiving zone is configured to receive a particular type of integrated circuit. A plurality of island-defining portions is arranged about each receiving zone. Each island-defining portion has an electrical terminal electrically connected to one electrical contact of its associated receiving zone. A rigidity-reducing arrangement connects each island-defining portion to each of its neighboring island-defining portions.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: A semiconductor package assembly is disclosed having a semiconductor die receiving member configured to accept a semiconductor die in either the flip-chip or the wirebond orientations. First contact sites on a die receiving surface provide electrical connection with a flip-chip component. Second contact sites provide electrical connection with a wirebond component. Electrically conductive traces connect the first and second contact sites with terminal contact sites. The semiconductor package assembly may further include the flip-chip or wirebond component mounted over the die receiving surface. Further, the assembly may also include a mounting substrate in electrical connection with the terminal contact sites.

Abstract: The present invention provides a technique capable of improving a mounting failure in a resin encapsulated semiconductor device and repairability thereof. The present semiconductor device includes a resin encapsulater, a semiconductor chip located within the resin encapsulater and having a plurality of electrodes on one main surface, a semiconductor chip loading portion disposed within the resin encapsulater and having a loaded surface for mounting the semiconductor chip thereon and an unloaded surface provided on the side opposite to the loaded surface, and a plurality of input/output leads which are connected to the plurality of electrodes to input signals to the plurality of electrodes of the semiconductor chip or output signals from the plurality of electrodes thereof and which extend outside the resin encapsulater.

Abstract: According to a typical invention of the inventions disclosed in the present application, a semiconductor chip with an electronic circuit formed therein is fixed to a die pad for a lead frame having projections formed on the back thereof, with an organic dies bonding agent. Pads on the semiconductor chip, and inner leads are respectively electrically connected to one another by metal thin lines. These portions are sealed with a molding resin. Further, each inner lead extends to the outside of the molding resin and is processed into gull-wing form for substrate mounting. Moreover, the inner lead is processed by soldering so that an external terminal is formed. Thus, since the projections are provided on the back of the die pad, the back of a packing material is brought into point contact with that of the die pad as compared with the conventional face-to-face contact. It is therefore possible to minimize the transfer of organic substances from the packing material.

Abstract: Provided is a semiconductor memory module including semiconductor devices using solder balls as outer connection terminals, which reduces the deterioration of solder joint reliability (SJR) due to the difference in the thermal expansion coefficients of the module components. The memory module includes a module board, an upper heat sink, a lower heat sink and a linking means. The linking means is formed to have a structure that makes it possible to absorb contraction and expansion within the semiconductor module due to the different thermal expansion coefficients of the upper heat sink, the lower heat sink and the module board.

Abstract: A leadframe structure for use with an integrated circuit chip, comprising a chip mount pad having an area smaller than said chip intended for mounting; a plurality of support members, each attached externally to the perimeter of said pad and internally to said leadframe; and each said support member having at least one portion located within the perimeter of said chip in a configuration operable to absorb thermally induced deformations of said support member.

Abstract: A process for manufacturing a semiconductor circuit device includes the steps of forming a plurality of semiconductor chips (2) across dicing lines (3) on a wafer (1), dividing each chip from the wafer, die-bonding the chip onto a die-pad (11) of the lead-frame, connecting a pad electrode (12) of the chip and a terminal (14) of the lead-frame with a wire (15), and forming a resin seal (16) covering the connection between the pad electrode and the terminal. Then, the dicing line has a predetermined width for dividing each chip, and the dicing line includes a test element group (4) and an adjusting mark (5). Accordingly, in the step of forming the plurality of chips, a cross line (6) having no test element group and no adjusting mark is provided on the dicing line for connecting between the pad electrode and the terminal with the wire.

Abstract: A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies inside is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on a respective main plane of the semiconductor element and a main electrode plate.

Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by e.g.

Abstract: A method and structure for isolating a die from thermally induced or pressure induced differential stresses between a die and a package includes providing an intermediate layer having therein a plurality of relief channels arranged to provide a flexure for absorbing such differential stresses. The relief channels define interior and peripheral portions of the intermediate layer, and the die is typically mounted on the interior portion. The peripheral portion of the intermediate layer is then bonded to the package. The channels may be disposed along both the upper and lower surfaces of the intermediate layer, or may be disposed on only one surface. Likewise, the channels may be disposed along one or both of the length and width of the upper or lower surfaces. Reservoir channels may also be provided to prevent adhesive from flowing and bridging the relief channels.

Abstract: The present invention provides an integrated semiconductor module comprising a chip, interposer, and substrate. The module is adapted to be mounted on a traditional circuit card carrying multiple other components. The chip of the present invention can be a conventional IC chip or chip package, including ball grid array packages, and will simply be referred to hereinafter as a “chip.” The interposer of the present invention is a conventional thin film interposer, such as those composed of a polyimide material and fabricated on a glass carrier plate. The substrate of the present invention is a conventional circuitized substrate, such as a BGA or laminate substrate, that is commonly employed in carrying a chip on a circuit card.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: A semiconductor package and a method for fabricating a semiconductor package are disclosed. The semiconductor package includes semiconductor chip attached to a circuit board that includes at least one lateral slot formed through the circuit board. Provision of the slot reduces stresses in the circuit board that are manifested by warpage. The semiconductor chip may be positioned in a central aperture of the circuit board and held therein by hardened encapsulant material.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.

Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Abstract: A microelectronic assembly includes a microelectronic element having a first surface including a central region and a peripheral region surrounding the central region, the microelectronic element including a plurality of contacts disposed in the central region. The microelectronic assembly also includes a compliant layer over the peripheral region of the first surface, the compliant layer having a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. A plurality of flexible bond ribbons are disposed over the compliant layer so that the bond ribbons extend over the top surface and one or more of the edge surfaces and the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.

Abstract: A semiconductor package is proposed, in which a lid is attached to a semiconductor chip and appropriately spaced apart from a heat sink having a top surface thereof exposed to the outside an encapsulant, so as to prevent external moisture from condensing on the semiconductor chip and reduce a thermal stress effect on the semiconductor chip. Moreover, a thermal conductive path is reduced in a portion passing through the encapsulant, allowing the heat-dissipating efficiency to be improved. In addition, with no contact between the heat sink and the semiconductor chip, quality of the semiconductor package is assured with no damage to the semiconductor chip.

Abstract: This invention provides a method apparatus for electrically connecting a semiconductor die, such as a power MOSFET, to a substrate on which the die is mounted, e.g., a lead frame, with a conductive strap, such that the connection is resistant to the shear stresses incident upon it with changes in temperature of the device. The method includes providing a conductive strap, and in one embodiment thereof, forming a recess in the top surface of the substrate. The bottom surface of a flange portion of the strap is attached to the floor of the recess such that the recess captures the flange and prevents relative horizontal movement of the flange and substrate with variations in the temperature of the device. Other embodiments include attaching the strap to the die and substrate with joints of a resilient conductive elastomer, and forming apertures in the strap and substrate that cooperate with a conductive joint material to reinforce the connection against temperature-induced shear forces.

Abstract: According to a typical invention of the inventions disclosed in the present application, a semiconductor chip with an electronic circuit formed therein is fixed to a die pad for a lead frame having projections formed on the back thereof, with an organic dies bonding agent. Pads on the semiconductor chip, and inner leads are respectively electrically connected to one another by metal thin lines. These portions are sealed with a molding resin. Further, each inner lead extends to the outside of the molding resin and is processed into gull-wing form for substrate mounting. Moreover, the inner lead is processed by soldering so that an external terminal is formed. Thus, since the projections are provided on the back of the die pad, the back of a packing material is brought into point contact with that of the die pad as compared with the conventional face-to-face contact. It is therefore possible to minimize the transfer of organic substances from the packing material.

Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.