Abstract: A method for annealing amorphous silicon film to produce polycrystalline film suitable for thin-film transistors fabricated on glass substrates is provided. The method involves using the selective location of nickel on a predetermined region of silicon to define the pattern of the lateral growth front as the silicon is crystallized. The method defines the resistivity of the silicide formed. The method also defines a specific range of nickel thicknesses to form the nickel silicide. A minimum thickness ensures that a continuous layer of nickel silicide exists on the growth front to promote an isotropic lateral growth front to form a crystalline film having high electron mobility. A maximum thickness limit reduces the risk of nickel silicide enclaves in the crystalline film to degrade the leakage current. Strategic placement of the nickel helps prevent nickel silicide contamination of the transistor channel regions, which degrade the leakage current.

Abstract: A semiconductor device and a method for forming the same. The semiconductor device comprises an insulating or semiconductor substrate, a thermally-contractive insulating film which is formed on said substrate and provided with grooves, and semiconductor film which is formed on the thermally-contractive insulating film and divided in an islandish form through the grooves. The thermally-contractive insulating film is contracted in a heat process after the semiconductor film is formed.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure.

Abstract: A polycrystalline silicon TFT of a top-gate type having a polycrystalline silicon film functioning as an active layer on a transparent insulating substrate. A gate electrode is provided on a channel region of the polycrystalline silicon film via a gate insulating film. On both sides of the channel region, source-drain regions of LDD structure consisting of low impurity concentration regions and high impurity concentration regions are provided. In the channel region of the polycrystalline silicon film, multiple monocrystal regions connecting source-drain regions are provided perpendicular to the transparent insulating substrate. Though electrons cannot smoothly pass through the channel region of the polycrystalline silicon film because of crystal grain boundaries and crystal defects therein, electric field effect mobility can be heightened by providing monocrystal regions, since electrons can smoothly pass through the monocrystal regions.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: A semiconductor device having an SOI structure capable of effectively preventing diffusion of an impurity from a source/drain region on an endmost portion of a silicon layer under a gate electrode is disclosed. In this semiconductor device, nitrogen is introduced into at least either a source/drain region or an end portion of a semiconductor layer located under a gate electrode, and the concentration profile of the nitrogen has a first concentration peak at least in either one of an endmost portion of the source/drain region in the direction where the gate electrode extends and an endmost portion of the semiconductor layer located under the gate electrode. Due to this concentration profile of nitrogen, point defects or the like serving as mediation for diffusion of an impurity are trapped, whereby diffusion of the impurity from the source/drain region is inhibited as a result. Thus, generation of an abnormal leakage current or the like is prevented.

Abstract: The specification describes thin film transistor integrated circuits wherein the TFT devices are field effect transistors with inverted structures. The interconnect levels are produced prior to the formation of the transistors. This structure leads to added flexibility in processing. The inverted structure is a result of removing the constraints in traditional semiconductor field effect device manufacture that are imposed by the necessity of starting the device fabrication with the single crystal semiconductor active material. In the inverted structure the active material, preferably an organic semiconductor, is formed last in the fabrication sequence.

Abstract: An SRAM cell comprising, at least, two driving transistors and two transfer transistors, and two load transistors each comprised of a TFT and disposed on these transistors through a layer insulation film, the load transistors having an active region comprising an Si film having improved crystallizability of amorphous Si by the solid phase growth technique using a catalytic element, and a barrier layer for preventing the catalytic element from diffusion into the driving transistors and the transfer transistors which is disposed between the layer insulation film and the load transistors.

Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer of the first silicon layer and of the anti-reflection layer. A portion of the gate insulator layer is removed to have undercut spaces under the first silicon layer. A dielectric layer is then formed on the semiconductor substrate, on the sidewalls of the gate region, and within the undercut spaces. A spacer structure containing first type dopants is then formed on the sidewalls of the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second type dopants is formed over the semiconductor substrate and the first silicon layer.

Abstract: Semiconductor devices having a gate electrode shared by two sets of active regions and methods of manufacture thereof are provided. In one embodiment, a first substrate is provided and a gate electrode is disposed over the first substrate. A second substrate is disposed over the gate electrode. A first set of active regions is disposed in portions of the first substrate adjacent the gate electrode and a second set of active regions is disposed above the gate electrode and adjacent the second substrate. The two sets of active regions may be coupled together or used separately.

Abstract: A thin film transistor includes a thin film transistor layer having a source region, a channel region and a drain region. In one implementation, a gate of the transistor is disposed laterally proximate the thin film channel region and comprises an annulus which laterally encircles the laterally proximate thin film channel region. In another implementation, a channel region of a thin film transistor extends elevationally away from a substrate. Source and drain regions are operatively associated with the channel region and are elevationally spaced therealong and apart from one another. A gate is disposed over the substrate and laterally proximate the channel region.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer.

Abstract: A liquid crystal display is disclosed having switching devices corresponding to pixel electrodes formed on the same semiconductor layer that has a drive circuit therein. The drive circuit is formed on the semiconductor layer in a single crystal semiconductor region and the switching devices are formed either in a second single crystal semiconductor region or in a non-single crystal semiconductor region. The second single crystal semiconductor region or the non-single crystal semiconductor region bearing the switching devices has a higher density of defects than the first semiconductor region.

Abstract: A process for integrating a vertical power device, such as an IGBT device, with suitable control circuitry, such as circuitry that provides self-protection from over-temperature (OT), over-voltage (OV) and over-current (OC) conditions. The process yields a vertical power device that is monolithically integrated with, and dielectrically isolated from, its control circuitry with the use of wafer-bonded silicon-on-insulator (SOI) material that yields a buried oxide layer. The process includes simultaneous fabrication of the power device below the buried oxide layer and its control circuitry above the buried oxide layer, in the SOI layer.

Abstract: In forming an electrode on a silicon oxide film on a semiconductor substrate through a silicon oxide film, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers. The portion of the gate electrode is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and of crystallizing (recrystallizing) this amorphous material. Depositing of the amorphous layers is carried out a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and crystallizing the amorphous material are repeated, whereby a laminated structure of polycrystalline layers having a necessary film thickness is obtained.

Abstract: A TFT formed on a semiconductor substrate of a first conductivity type, includes a first doped portion of a polysilicon layer over FOX regions and a first insulating layer. A buried contact extends through the first portion of a polysilicon layer and the first insulating layer to the surface of the substrate adjacent to a FOX region. A second doped portion of the polysilicon layer overlies the first portion and forms a buried contact between the second portion and the substrate. The polysilicon layer forms a gate electrode and a conductor from the buried contact. Doped source/drain regions in the substrate are juxtaposed with the gate electrode. An interelectrode dielectric layer over the gate electrode and the conductor has a gate opening therethrough down to the substrate. A gate oxide layer is formed on the surface of the substrate at the gate opening. A semiconductor film extends over the interelectrode dielectric layer and over the surface of the substrate through the gate opening.

Abstract: A circuit and method for an improved inverter is provided. The present invention capitalizes on a switched source impedance to prevent subthreshold leakage current at standby in low voltage CMOS circuits. The switched source impedance is provided by dual-gated transistors. The dual gates of the transistors are biased to modify the threshold voltage of the transistors (V.sub.t). This design provides fast switching capability for low power battery operated CMOS circuits and systems. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.

Abstract: Semiconductor devices such as thin-film transistors formed by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

Abstract: A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

Abstract: In producing a semiconductor device by annealing with laser light irradiation, while a linear laser light is scanned in a direction perpendicular to a line, the annealing is performed for a semiconductor material. In this state, since an anneal effect in a beam lateral direction corresponding to a line direction is 2 times or more different than that in the scanning direction, a plurality of semiconductor elements are formed along a line direction in which the linear laser light is irradiated. Also, a line direction connecting the source and drain region of a thin film transistor is aligned to the line direction of the linear laser light.

Abstract: A vertical thin film transistor formed in a single grain of polysilicon having few or no grain boundaries for use in memory, logic and display applications. The transistor is formed from a thin film of polysilicon having large columnar grains, in which source and drain regions have been formed. The large grain size and columnar grain orientation of the thin film are provided by recrystallizing a thin amorphous silicon film, or by specialized deposition of the thin film. Use of a thin film permits the transistor to be formed on an insulating substrate such as glass, quartz, or inexpensive silicon rather than a semiconductor chip, thereby significantly decreasing device cost.

Abstract: The disclosure includes preferred semiconductor transistor devices utilizing thin film transistors, as well as preferred methods of forming such devices. Specifically, a bottom thin film transistor gate is formed having a top surface. An insulating filler is provided adjacent the thin film transistor gate to an elevation at least as high as the thin film transistor gate top surface, and subsequently levelled to provide generally planar insulating surfaces adjacent the thin film transistor gate. The planar insulating surfaces are substantially coplanar with the thin film transistor gate top surface. A planar semiconductor thin film is then formed over the thin film transistor gate and over the adjacent planar insulating surfaces. The thin film is doped to form source and drain regions of a thin film transistor which is bottom gated by the thin film transistor gate.

Abstract: A liquid crystal display panel includes a counter substrate having a counter electrode and a multi-layered dielectric film both formed thereon, and an array substrate formed with pixel electrodes and thin-film transistors serving as switching elements. A layer of polymer dispersed liquid crystal material containing a UV-curable resin component and a liquid crystal component is sandwiched and sealed between the counter and array substrates. A light shielding film is formed over each thin-film transistor. The multi-layered dielectric film is a laminated structure of alternating thin-films of SiO.sub.2 and HfO.sub.2. Since the multi-layered dielectric film is of a nature capable of transmitting UV-rays of light therethrough, the UV-curable resin component positioned underneath the multi-layered dielectric film can be cured during the manufacture.

Abstract: A thin film effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; (c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; (d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.

Abstract: A pixel circuit construction for image sensing includes a photosensor, an amplifier, a selector switch and, and a reset switch. The amplifier may be a single polycrystalline silicon (channel) transistor for high gain. The selector switch may also be a single polycrystalline silicon (channel) transistor for high conductivity. The reset switch may a single amorphous crystalline silicon (channel) transistor for low leakage current. The photosensor and amplifier may be connected to a shared bias line or may be connected to separate bias and drive lines, respectively. The selector and reset switches may be connected to a shared data line or may be connected to separate data and reset lines, respectively. Laser crystallization and rehydrogenation techniques are well suited to obtaining devices described herein.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate.

Abstract: An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips.

Abstract: In a circuit including at least one thin film transistor formed on an insulating substrate, a region 105 to which metal elements that promote crystallinity are added is disposed apart from a semiconductor island region 101 that forms the thin film transistor by a distance y, has a width w, and extends longitudinally over an end portion of the semiconductor island region 101 by a distance x. Also, in a TFT manufactured in a region which is not interposed between the nickel added regions, another nickel added region is disposed (resultantly, which is interposed between two nickel added regions). Further, all the intervals between the respective nickel added regions are preferably identified with each other. Thus, a thin film transistor circuit being capable of a high speed operation (in general, some tens of Mhz and more) is formed. In particular, correcting the difference of crystal growths, using a crystalline silicon film added with nickel, TFTs with uniform characteristics can be provided.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: In a memory cell of an SRAM, a load transistor has a pair of source/drain regions formed to define a channel region, and a gate electrode layer being opposite to the channel region with an insulating layer therebetween. A VVP layer is formed to sandwich the channel region with the gate electrode layer to be opposite to channel region with an insulating layer therebetween. This VVP layer is provided such that GND potential is applied when active and Vcc potential is applied during standby. Thus, a large ON current can be implemented while maintaining a small OFF current of a TFT, even when the power supply voltage is made lower due to reduction in voltage.

Abstract: A memory device of the present invention allows high integration, improved operational speed, larger capacitance, improved isolation and/or reduced leakage current. The memory device includes a plurality of transistors parallel to each other and formed above a substrate. A bit line is perpendicular to each of the plurality of transistors, and is coupled to the transistors. A predetermined portion of each transistor is a storage node for a capacitor, and a plate surrounds the predetermined portion through a dielectric film.

Abstract: The MOSFET has a stacked gate structure which has a first silicon layer, a second silicon layer, and a spacer structure. The first silicon layer is formed over the semiconductor substrate. The second silicon layer contains second type dopants and is formed on the first silicon layer. The spacer structure containing first type dopants is formed on the sidewall of the first silicon layer and the second silicon layer. A gate insulator layer is formed between the first silicon layer and the semiconductor substrate. The second silicon layer is also formed on the semiconductor substrate at a region uncovered by the stacked gate structure. A junction region is formed in the semiconductor substrate under the second silicon layer but not under the stacked gate structure. An extended junction is formed in the semiconductor substrate under the spacer structure.

Abstract: SRAM memory cells is provided with high resistance to soft error and no parasitic capacitance due to PN junction. SRAM memory cells comprises the load resister is a thin film transistor having a same conductive type as that of the driver transistor.

Abstract: The present invention relates to a contact structure not only for a semiconductor device having a hetero-junction bipolar transistor or a hetero-insulated gate field effect transistor but also for semiconductor devices at large. In a semiconductor layer of a polycrystalline or amorphous undoped III-V compound semiconductor or an alloy thereof, a through hole is formed for contact. The size of the through hole is set to permit exposure of at least part of a first conductor layer and a dielectric layer, such as an Si compound, present around the first conductor layer, and a second conductor layer is formed within the through hole so as to contact the first conductor layer. Since the semiconductor layer can be subjected to a selective dry etching for the dielectric layer, the dielectric layer is not etched at the time of forming the above through hole in the semiconductor layer.

Abstract: A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer.

Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.

Abstract: In an active matrix display unit, a plurality of thin-film transistors are connected in series for one pixel electrode as a switching element, and at least one of the thin-film transistors connected in series except for thin-film transistors at both ends thereof is always made in an on-state, to thereby constitute a resistance component and a capacitance component between the thin-film transistors connected in series with the result that a leak current when the switching element is off is reduced.

Abstract: A compact, integrated semiconductor device includes a first transistor and a second transistor. The first transistor has a gate formed by a first portion of a gate material. A second portion of the gate material provides the bulk material for a second transistor. The device can be utilized in a six-transistor SRAM cell. The two-transistor structure can include a p-channel transistor and an n-channel transistor of such a cell.

Abstract: A semiconductor device having areas that are semiconductor on insulator ("SOI") and areas that are bulk, single crystalline semiconductive areas is provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not be selectively grown, because a sacrificial polishing layer is deposited, is also provided.

Abstract: The source-to-drain gap in a TFT is formed by exposing a positive photoresist from the back side of the substrate, using the gate as an optical mask. The resulting photoresist mask then protects the underlying amorphous silicon while the structure is exposed to a gaseous plasma that includes dopant material. Heavily doped regions are thus formed, leaving a gap that is in perfect alignment with the gate. After removal of the photoresist, the structure is given a laser anneal which results both in the crystallization of the amorphous silicon into polysilicon as well as a more even distribution of the dopant material. The structure is completed in the usual way by providing a passivation layer.

Abstract: The present invention is directed to a thin film transistor (TFT) structure having a channel region formed of a crystallized SiGe and is to provide a thin film transistor having a large carrier mobility. In this case, a channel region (4) is formed of a crystallized SiGe thin film.

Abstract: A semiconductor device comprises: a first semiconductor layer 6 having a first conductivity formed on a substrate having a surface of an insulating material 4; a source region 16a and a drain region 16b, which are formed on the first semiconductor layer so as to be separated from each other and which have a second conductivity different from the first conductivity; a channel region 6 formed on the first semiconductor layer between the source region and the drain region; a gate electrode 10 formed on the channel region a gate sidewall 14 of an insulating material formed on a side of the gate electrode; and a second semiconductor layer 18 having the first conductivity formed on at least the source region. This semiconductor device can effectively suppress the floating-body effect with a simple structure.

Abstract: A field-effect transistor has a covering electrode overlying at least part of the transistor's channel. The covering electrode is formed on an insulating layer that covers the source, gate, and drain of the transistor. One voltage is applied to the covering electrode when the field-effect transistor is switched on. Another voltage is applied when the field-effect transistor is switched off, creating an electric field that hinders current flow in the channel. In an antenna switch, this type of transistor couples an antenna to a receiving circuit, and another transistor couples the antenna to a transmitting circuit.

Abstract: A substrate transistor is formed, including a gate insulation region formed on a substrate, spaced apart source/drain regions formed in the substrate, and a gate electrode formed on the gate insulation region, disposed between the spaced apart source/drain regions, the gate electrode having a sidewall portion. A lateral thin film transistor is formed, including a sidewall gate insulation region on the sidewall portion of the gate electrode and a lateral channel region on the sidewall gate insulation region such that the gate electrode controls the current in the lateral channel region. A first one of the spaced apart source/drain regions of the substrate transistor preferably includes a lightly-doped inner portion disposed adjacent the gate electrode and a heavily-doped outer portion disposed adjacent the lightly-outer portion, opposite the gate electrode. The lateral channel region preferably is electrically connected to a second one of the spaced-apart source/drain regions of the substrate transistor.

Abstract: A semiconductor device is an SRAM cell having a pair of access transistors, a pair of driver transistors and a pair of load transistors. A gate electrode of the load transistor is electrically connected to a region of a semiconductor substrate which is surrounded by a gate electrode of the driver transistor, a channel region of the load transistor is formed opposite to the gate electrode of the load transistor with an insulating film therebetween, and a pair of source/drain regions of the load transistor are formed to sandwich the channel region.

Abstract: A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels.

Abstract: A semiconductor device includes a groove formed in a surface of a first semiconductor substrate of one conductivity type in order to partition and isolate first and second device regions. A first insulating film on the first semiconductor substrate of the first device region also contacts the groove. A second insulating film covers an inner wall of the groove. The first insulating film is thicker than the second film in order to increase the breakdown voltage and facilitate carrying a higher current. This thickness relationship also aids manufacturing.