Abstract: A depletion mode power MOSFET has a gate electrode formed of material that is refractory, or resistant, to high temperature encountered during device fabrication. A depletion channel region which is formed in a base region of a MOSFET and which interconnects the source and drain regions is formed after a high temperature drive to form the base region, but before a gate oxide and gate and source electrodes are formed at lower temperatures. The depletion channel region is thus subjected to reduced temperatures and grows only slightly in thickness, so that it can be easily depleted. The gate oxide, similarly, is subjected to reduced temperatures, and, particularly when made thin, exhibits high insensitivity to radiation exposure.

Abstract: A method of fabricating a transistor on a wafer including: forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.

Abstract: A non-crystalline silicon--preferably a-Si:H--active device for use in a large-scale hardware implementation of an artificial neural network system having an analog and digital mixed morphology. A plurality of a-Si:H thin-film transistors (TFTs) implement addition, multiplication and weighting functionality and are arranged in a highly-connected morphology with other active and passive semiconductor elements. Electrical signals are selectively applied to metal plates and light-emitting devices in order to locally or globally alter the threshold characteristics of the TFTs.

Abstract: A BiCMOS structure in which the bipolar transistor is preferably arranged vertically and the MOS transistors are formed on insulator. SIMOX techniques may be used to form a starting substrate.

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.

Abstract: A thin-film transistor having a thin-film channel region (20) inlaid in a recess (29) along the wall of a multi-layered insulating structure (14), and a gate electrode (12) electrically controlling current conduction in the thin-film channel (20) and separated therefrom by a gate dielectric layer (32). The multi-layered insulating structure (14) includes a spacing layer (28) which is withdrawn from the wall of the multi-layered insulating structure (14) and forms an inner wall of the recess (29). By residing in the recess (29), the thin-film channel region (20) is aligned to the multi-layered insulating structure (14) and the gate dielectric layer (32) separates exposed portions of the thin-film channel region (20) from the gate electrode (12). Thin-film source and drain regions (16, 18) are integral with the thin-film channel region (20) and are self-aligned to the multi-layered insulating structure (14).

Abstract: A new and improved static random access memory (SRAM) cell wherein separate regions of polysilicon are formed over a silicon substrate and are separated by defined openings therein into which oxide filler material is introduced to render the regions of polysilicon and oxide substantially co-planar at their upper surfaces. An access transistor and a thin film load transistor are formed within and adjacent to first and second regions of the polysilicon, respectively, and yet a third, pull down transistor is formed within and adjacent to a third polysilicon region. The thin film transistor includes a thin second layer of polysilicon which is electrically isolated from the second one of the polysilicon regions and is doped to form therein source, drain and channel regions. Advantageously, the thin film transistor is formed on this substantially planar surface, thereby improving process yields and device performance.

Abstract: An SOI-type thin film transistor having a transparent insulating substrate a first gate electrode, a first gate insulating film, a semiconductor layer, a second gate electrode and a second gate insulating film which are respectively formed on the transparent insulating substrate, wherein the width of the first gate electrode and that of the second gate electrode are different from each other and as well as the thickness of the first gate insulating film and that of the second gate insulating film are different from each other.

Abstract: A charge transfer device includes: a transfer channel for transferring a charge in a charge transfer direction; a charge detecting section having a diffusion layer for storing the charge transferred through the transfer channel and for inducing a voltage corresponding to the amount of the stored charge; and a transistor for detecting the induced voltage, the transistor having: a gate electrode formed on the diffusion layer, the gate electrode being in direct contact with the diffusion layer; a gate insulating film formed on the gate electrode; and a channel region formed above the gate electrode.

Abstract: An integrated power switch structure comprises a lateral MOS transistor (3) and a lateral or vertical thyristor (2). The drain-source path of the lateral MOS transistor (3) is in series with the cathode-anode path of the thyristor (2). In order to ensure that the power switch structure reliably switches on and off with great dielectric strength and low switch-on resistance, at least the source electrode of the lateral MOS transistor (3) is insulated against the substrate (7) by means of a buried oxide layer (8) in accordance with the present invention.

Abstract: A thin film transistor includes a semiconductor thin film formed with a source region and a drain region at opposite end portions thereof and having an offset region near at the drain region, a gate electrode formed above the region between the source region and the offset region of the semiconductor thin film, with a gate insulating film being interposed, and a conductive layer formed above the gate electrode or under the semiconductor thin film, with an insulating film being interposed, the conductive layer being applied with generally the same potential as the gate electrode, wherein the resistance value of the offset region is controlled by the potential of the conductive layer. The gate electrode may be formed under the semiconductor thin film. In this case, the conductive layer is formed above the semiconductor thin film or under the gate electrode, with an insulating film being interposed. An SRAM is also provided which uses a thin film transistor constructed as above.

Abstract: A method of fabricating a transistor on a wafer including; forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.

Abstract: An improved static random access memory device of the CMOS load memory cell type for storing one-bit information is capable of 4M bit or greater memory capacity. Each memory cell includes two transfer transistors, two driving transistors, and two load transistor elements. Each load transistor element is a PMOS thin film transistor and comprises a source formed of first and second conductive layers and connected to a constant power source line, and a drain also formed of the first and second conductive layers and connected to the drain of a corresponding one of the driving transistors. A channel region of each load transistor element is composed only along the region defined by the second conductive layer and a respective gate is formed of a third conductive layer which is separated from the channel region by a gate insulating layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, and first and second word lines extending generally parallel to each other along a predetermined direction and respectively coupled to gate electrodes of the first and second transfer transistors. Each of the first and second thin film transistor loads include first and second impurity regions which sandwich a channel region formed by a semiconductor layer provided on the semiconductor substrate, and a gate electrode formed by confronting conductor layers and isolated from the channel region.

Abstract: An SRAM memory cell structure, wherein a word line is disposed near the center of a cell, each one of driver transistors is disposed on both sides thereof substantially in parallel with each other, a contact portion for a gate electrode of said driver transistor is formed being laminated on a word transistor formed together with said word line, and a semiconductor, wherein an upper transistor and a lower transistor are disposed, an overlapped portion in which at least three layers each having a diffusion region for forming each of said transistors are overlapped is formed, and a contact is taken at said overlapped portion.

Abstract: A semiconductor device which is excellent in reliability and electrical characteristics. The semiconductor device is formed on an insulating substrate. A channel region is formed between a source and a drain by the voltage applied to a gate electrode. The channel region, the source, and the drain are fabricated from a semiconductor having a large mobility. The other regions including the portion located under the channel region are fabricated from a semiconductor having a small mobility.

Abstract: A semiconductor device and a method for forming the same. The semiconductor device comprises an insulating or semiconductor substrate, a thermally-contractive insulating film which is formed on said substrate and provided with grooves, and a semiconductor film which is formed on the thermally-contractive insulating film and divided in an islandish form through the grooves. The thermally-contractive insulating film is contracted in a heat process after the semiconductor film is formed.

Abstract: A method for manufacture of a full CMOS type SRAM, comprising the steps of forming a first mask layer on a semiconductor layer, and patterning the first mask layer by photolithography to form semiconductor island layers where a driver MOS transistor and a load MOS transistor are formable with a slight space therebetween; forming a second mask layer on the semiconductor layer, and patterning the second mask layer by photolithography in such a manner as to overlap the region with one of the driver and load MOS transistors, but not to overlap the isolating region between the transistors; masking, with a resist film, the region with the other of the driver and load MOS transistors, and etching the first mask layer while masking the same with the resist film and the second mask layer; and etching the semiconductor layer while masking the same with the first mask layer, thereby forming mutually isolated semiconductor island layers where the driver and load MOS transistors are formed respectively.

Abstract: An integrated circuit RESURF LDMOS power transistor employs a source isolated, embedded gate MOS transistor with RESURF LDMOS technology to provide a source isolated high voltage power transistor with low "on" resistance for use in applications requiring electrical isolation between the source and substrate.

Abstract: An integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits.

Abstract: The present invention is intended to relax restrictions on threshold voltage for a nonvolatile storage device, such as a flash EEPROM and to enable a nonvolatile storage device to be constructed in a higher degree of integration. A plurality of nonvolatile memory cells (4) having floating gates (14) and control gates (17) formed over the floating gates (14) are connected in series through source-drain regions (22) between the data output terminal and the reference voltage terminal of data lines (38, 39). Channel forming regions (33) are formed on a gate insulating film (31) formed over the control gates (17) . The source-drain regions 34 of thin-film transistors are connected to the opposite sides of the channel forming regions (33) and the source-drain regions (22) , respectively.

Abstract: A semiconductor memory cell (10) including cross coupled CMOS transistors (12, 14) wherein an N-channel transistor (20) overlies a central portion of each of a first and second active regions (13, 13') at a position intermediate to two word lines (40, 42) which overlie end portions of the active regions (13, 13'). P-channel pull-up transistors (18, 22) overlie the N-channel transistors (16, 20) and share common intermediate gate electrodes (27, 29). Staggered bit line contacts (48, 50) are formed to each active region (13, 13') adjacent to each word line (40, 42) and opposite to the N-type transistors (16, 20). Staggered Vss contacts (52, 54) are provided to each active region (13, 13') adjacent to the word lines (40, 42) and opposite to the bit line contacts (48, 50). A Vss signal is electrically coupled to the N-channel transistors (16, 20) by a doped region (21) formed in the first and second active regions (13, 13' ) which cross under the word lines (40, 42).

Abstract: The invention is directed to a thin film transistor (TFT) fabricated by using a recessed planarized poly plug as the bottom gate and a recessed planarized poly plug for the TFT drain connecting region. The TFT of the present invention can be used in any integrated circuit that uses such devices and in particular as a pullup device in a static random access memory (SRAM). The invention is directed to a process to fabricate a thin film transistor (TFT) having LDDs and/or high resistive regions (loads) that are self-aligned to a recessed plug that is used as the bottom gate for the TFT.

Abstract: A thin film integrated circuit resistor is disclosed that is substantially linear at applied voltages greater than 100 volts. The integrated circuit resistor comprises a substrate, a plurality of resistive blocks electrically connected in series, a shield associated with each resistive block, and passivation means for isolating the substrate from the resistive blocks and the shields, and for isolating the shields from the resistive blocks except where they are electrically connected. Each shield substantially surrounds its associated resistive block with conductive material, and each shield is electrically connected to its resistive block such that each shield is at a potential of some point along the length of its associated resistive block.

Abstract: A thin film transistor is used as a load transistor in a memory cell in a SRAM. A load thin film transistor is arranged on an interlayer insulating layer on the surface of a silicon substrate. A silicon layer in which source/drain regions of the thin film transistor are formed is covered with an oxidation preventing film. An interlayer insulating layer which is to be subject to high temperature reflow processing is formed on the surface of the oxidation preventing film. The oxidation preventing film is formed of polycrystalline silicon, amorphous silicon, silicon nitride, or the like and formed on the silicon layer in the thin film transistor directly or through an insulating layer to cover the surface of the silicon layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, where each of the first and second transfer transistors, the first and second driver transistors and the first and second thin film transistor loads have a source, a drain and a gate electrode, and a connecting region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are connected.

Abstract: A semiconductor device is manufactured by forming an epitaxial layer (22) insulated from a silicon substrate (2), and forming a device in the epitaxial layer (22). On the semiconductor substrate (2), a silicon dioxide layer (4) is formed (FIG. 2A). Then the silicon dioxide layer (4) is provided with openings (14) (FIG. 2D). Silicon carbide is grown until it protrudes from the openings (14) to thereby form a silicon carbide seed crystal layer (16) (FIG. 2E). Next, oxidation is carried out, allowing a field oxide layer (20) to be connected at the portion under the openings (14) and the silicon carbide seed crystal layer (16) to be insulated from the silicon substrate (2). Thereafter, epitaxial growth is effected from the silicon carbide seed crystal layer (16). The growth is stopped before silicon carbide grown layers (22) connect to one another, thus obtaining epitaxially grown layers (22) having regions which are separate from one another. The MOS device is formed in this epitaxially grown layer (22).

Abstract: A transistor structure (10) has a substrate (12). A first transistor is formed within the substrate (12) having a source region (38), a drain region (30), and a gate electrode formed by a first spacer (26a). A second transistor is formed within the substrate (12) by the source region (38), a drain region (28), and a gate electrode formed by a second spacer (26a). A third transistor is formed overlying the first transistor. The third transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the first spacer (26a). A fourth transistor is formed overlying the second transistor. The fourth transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the second spacer (26a). The first, second, third, and fourth transistors may be interconnected to form a portion of a compact static random access memory (SRAM) cell.

Abstract: A electrically erasable and programmable read only memory device has a memory cell array implemented by a plurality of floating gate type memory transistors, and each of the floating gate type memory transistors is implemented by a thin film field effect transistor with a floating gate electrode formed on a relatively thick insulating film covering a major surface of a semiconductor substrate so that the biasing conditions and crystal defects do not have any influence on the floating gate type memory transistor.

Abstract: In a semiconductor device and, in particular, a semiconductor memory device in which a channel region formed in a polycrystalline film of a first channel conductivity type insulated gate field effect transistor is divided into a first channel region, which is in contact with a drain region, and a second channel region and the second channel region contains a second conductivity type impurity or a first conductivity type impurity whose density is higher than the impurity density of the first channel region, the threshold voltage can be controlled and the leakage current can be made small.

Abstract: A CMOS SRAM memory cell, and a method of making the same, is disclosed. The disclosed cell is configured as cross-coupled CMOS inverters, with the n-channel pull-down transistors in bulk, and with the p-channel load devices being accumulation mode p-channel transistors in a thin polysilicon film. The cross-coupling connection is made by way of an intermediate layer, which may include polysilicon at its top surface for performance enhancement, each of which makes contact to the drain region of an n-channel transistor, and to the opposite gate electrode, via a buried contact. The intermediate layer also serves as the gate for the thin-film p-channel transistor, which has its channel region overlying the intermediate layer. The p-channel transistors may be formed so as to overlie part of the n-channel transistor in its inverter, thus reducing active chip area required for implementation of the memory cell.

Abstract: Disclosed is a TFT for a semiconductor memory device and the fabricating method thereof, comprising a first conductive layer formed on a first insulating layer of a semiconductor substrate and doped with a first conductive type impurity, a second insulating layer formed on the first conductive layer, a contact hole formed in the second insulating layer above the first conductive layer, a semiconductor layer formed on a predetermined portion of the first conductive layer exposed in the contact hole, the inner walls of the contact hole and the second insulating layer, a thin-film gate insulating layer covering the semiconductor layer, a second conductive layer formed on a gate insulating layer to overlap the contact hole and its periphery, a first impurity region formed while upwardly dispersing the impurity of the first conductive layer into the semiconductor layer in contact with the first conductive layer of the contact hole, a second impurity region placed in the semiconductor layer of the second insulating

Abstract: A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25). The thin film transistor has a second gate electrode (55), and drain and source electrodes (56, 57) wherein the drain and source electrodes (56, 57) contact different portions of the first island of polysilicon (29). Preferably, the first gate electrode (58) is coupled to the second gate electrode (55).

Abstract: A plurality of strip shaped first polysilicon layers 3 are formed on a monocrystalline silicon substrate 1, a plurality of strip shaped second polysilicon layers 5 are formed thereon crossing the first polysilicon layers 3, and a plurality of strip shaped third polysilicon layers 8 are further formed thereon crossing the second polysilicon layers 5. The first and second polysilicon layers 3 and 5 are laser-annealed and monocrystallined. Contact holes 4 and 7 are selectively formed at the crossing points of the first polysilicon layers 3 and the second polysilicon layers 5, and the crossing points of the second polysilicon layers 5 and the third polysilicon layers 8. A PN junction is formed on each surface layer of the first polysilicon layers 3 and the second polysilicon layers 5 in the portions corresponding to these contact holes 4 and 7. Two layers of memory cell arrays using diode elements as memory cells are piled upon each other.

Abstract: A semiconductor device having a thin-film transistor (22) and a process for making the device. The semiconductor device includes a substrate (11) having a principal surface. A gate electrode (29) overlies the principal surface and a gate dielectric layer (23) overlies the gate electrode (29). A conductive channel interface layer (25) overlies the upper surface of the gate electrode (29) and is spaced apart from the gate electrode (29) by the gate dielectric layer (23). A conductive thin-film layer (57) overlies the gate electrode (29) and forms a metallurgical contact to the channel interface layer (25). Remaining portions of the thin-film overlie the principal surface and form source and drain regions (63, 65) of the thin-film transistor (22). The thin-film source and drain regions (63, 65) are formed by placing a diffusion barrier cap (60) over the channel portion (61) of the thin-film layer (57) and introducing conductivity determining dopant into the thin-film layer (57).

Abstract: A semiconductor device comprising an electrode or wiring layer formed over a semiconductor substrate, a circuit element provided adjacent the electrode or wiring layer, and a conductive layer formed on a side wall, or a side wall and top surface, of the electrode or wiring layer with an insulating film provided therebetween, and supplied with a fixed potential or a variable potential different from a potential on the electrode or wiring layer.

Abstract: A semiconductor memory device includes a memory cell formed in a trench. The trench is formed by a bottom wall formed of a semiconductor substrate and a sidewall extending from the bottom wall and formed of the semiconductor substrate and an insulation layer thereon. A capacitor includes a first electrode formed in the semiconductor substrate, a dielectric film being in contact with the first electrode and formed on the bottom wall and the sidewall portion formed of the semiconductor substrate, and a second electrode formed on the dielectric film. A field effect transistor includes, a gate electrode, and second conductivity type first and second impurity regions formed in a semiconductor sidewall layer. The semiconductor sidewall layer is formed on the sidewall portion formed of the insulation layer. The gate electrode is formed on a side surface of the semiconductor sidewall layer in the trench with an insulating film interposed therebetween.

Abstract: Disclosed herein is a thin film field effect transistor and a method for producing such a thin film transistor. The thin film transistor has a transistor gate and thin film active and channel regions. The transistor gate has a top surface and sidewalls which are coated with a thin gate insulating layer. A thin semiconductor film is provided over the transistor gate and thin gate insulating layer to form a conductively doped thin film channel region and conductively doped thin film active regions. The thin film channel region contacts the thin gate insulating layer opposite the transistor gate top surface and opposite the sidewalls. The transistor gate sidewalls in operation gate the opposite thin film channel region through the thin gate insulating layer. The thin film field effect transistor can be fabricated over an underlying MOSFET to form a CMOS inverter with the transistor gate being common to both the thin film transistor and the MOSFET.

Abstract: A static RAM cell including first and second bulk transistors having gate electrodes extended over an element isolation region and forming a flip-flop, third and fourth bulk transistors having source and drain regions and formed adjacently to the element isolation region, a first conductive strap layer for self-aligning the gate electrode of the first bulk transistor with the source or drain region of the third bulk transistor, and a second conductive strap layer for self-aligning the gate electrode of the second bulk transistor with the source or drain region of the fourth bulk transistor.

Abstract: A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.

Abstract: A polycrystalline silicon layer is used to allow simultaneous fabrication of both N- and P-type MOSFET's on a common channel layer during integrated circuit fabrication. The polysilicon layer is between 20 .ANG. and 750 .ANG. thick, and preferably between 200 .ANG. and 500 .ANG. thick. These dimensions afford the polysilicon layer the high effective mobility, low threshold voltage and low leakage current characteristics, especially if the vapor-deposited polysilicon layer is annealed and/or ion implanted with Si.sup.+ or Ge.sup.+ after deposition. Application of the polysilicon layer over adjoining insulating and P-type semicondcuting areas allows the single polysilicon layer to serve as active terminals and channels of both conductivity types of MOS transistors without intervening insulating or semiconducting layers.

Abstract: A method for producing a mask ROM having an array of memory cells in which pn junctions obtained by introducing P-type impurities by ion implantation onto the surface of an N-type electrically conductive layers obtained in turn by introducing N-type impurities into the polysilicon layers are formed as memory cells in a matrix configuration. The polysilicon layers that are to be rendered into the N-type electrically conductive layers are previously monocrystallized by laser annealing. In this manner, the N-type electrically conductive layers into which P-type impurities are introduced by ion implantation at the time of formation of the pn junction are turned into a monocrystalline layer so that the surface of the N-type electrically conductive layers may be uniformly and easily converted into the P-type by this ion implantation. In short, the junction surface of the pn junction used as the memory cell becomes uniform.