Axial Leads Patents (Class 257/694)
  • Patent number: 9761558
    Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: September 12, 2017
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Patent number: 9252122
    Abstract: A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: February 2, 2016
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Patent number: 9245830
    Abstract: A circuit package having an inner lead, an outer lead and a circuit element is provided, in which the circuit element is connected a first surface of the inner lead. The circuit package has a first molded resin portion and second molded resin portions. The first molded resin portion is formed from a second surface, opposite to the first surface, of the inner lead toward the first surface inner lead embedding the inner lead and the circuit element. And the second molded resin portions are formed on side portions of the outer lead excluding the first and second surfaces of the outer lead.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 26, 2016
    Assignee: NEW JAPAN RADIO CO., LTD.
    Inventors: Yoshio Fujii, Eisuke Mori, Hideki Muto, Shinji Hara
  • Patent number: 9041188
    Abstract: An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component.
    Type: Grant
    Filed: November 10, 2012
    Date of Patent: May 26, 2015
    Assignee: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Wan-Lan Chiang, Chih-Ping Peng, Hui-Ying Ding
  • Patent number: 9006036
    Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoko Higashino, Yuichi Morinaga, Kazuya Tsuboi, Tamaki Wada
  • Patent number: 8796843
    Abstract: High-power and high-frequency semiconductor devices require high signal integrity and high thermal conductance assembly technologies and packages. In particular, wide-gap-semiconductor devices on diamond benefit from spatially separate electrical and thermal connections. This application discloses assembly and package architectures that offer high signal integrity and high thermal conductance.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: August 5, 2014
    Assignee: Element Six Technologies US Corporation
    Inventors: Dubravko I. Babic, Quentin E. Diduck, Alex Schreiber
  • Patent number: 8648450
    Abstract: In accordance with the present invention, there is provided a semiconductor package or device including a uniquely configured leadframe sized and configured to maximize the available number of exposed lands in the semiconductor device. More particularly, the semiconductor device of the present invention includes a die pad (or die paddle) defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: February 11, 2014
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Min Bae, Byong Jin Kim, Won Bae Bang
  • Patent number: 8455915
    Abstract: The light emitting device according to the present invention includes a resin molded body having a recess, a first electrically conductive member and a second electrically conductive member each having terminal portions respectively exposed from a first outer side surface and second outer side surface which are opposite outer side surfaces among the outer side surfaces of the resin molded body, and a light emitting element mounted on the first electrically conductive member exposed at a bottom surface of the recess. The recess has a first bottom surface on which the light emitting element is mounted and a second bottom surface arranged at a higher position of the outer periphery of the first bottom surface.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 4, 2013
    Assignee: Nichia Corporation
    Inventor: Masaki Hayashi
  • Patent number: 8395246
    Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 12, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Cheemen Yu, Vani Verma, Hem Takiar
  • Patent number: 8357931
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 22, 2013
    Assignee: Nvidia Corporation
    Inventors: Brian S. Schieck, Howard Lee Marks
  • Patent number: 8283663
    Abstract: A multichip device, which achieves a normal operation and a testing operation without the needs for terminals dedicated for the testing and/or an interposer substrate, is provided. The peripheral chip also includes a switching unit for providing a switching between a normal mode that provides a first connection condition and a testing mode that provides a second coupling connection condition. The switching unit, in turn, provides connections of at least some of a plurality of outside terminals to the functional circuits, respectively, in the normal mode, and connects at least some of a plurality of outside terminals to the inside terminals in the testing mode. Thus, the normal operation and the testing operation can be carried out without the needs for the external terminals and/or the interposer substrate, which are employed for the purpose of only the testing.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: October 9, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuyuki Kobayashi
  • Patent number: 8233127
    Abstract: An object of the present invention is to reduce a lateral width of an FPC also with evenly aligned and arranged plurality of ICs. The liquid crystal display device according to the present invention includes a glass substrate, a plurality of ICs of COG (Chip On Glass) configuration aligned on a glass substrate along a side thereof, and an FPC (Flexible Printed Circuit) that is arranged to extend along the side of the glass substrate and that is connected to the plurality of ICs. Specified ICs from among the plurality of ICs are arranged in that extending directions of their longer sides are inclined with respect to an extending direction of the side of the glass substrate such that the longer sides face towards a central side of the FPC.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: July 31, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tomohiro Tashiro
  • Patent number: 8188582
    Abstract: Provided are a lead frame, semiconductor device, and methods of manufacturing the same. The lead frame may include a die pad having at least three pair of sides parallel with each other, and a plurality of inner leads spaced apart from a circumference of the die pad, arranged in a radial shape with respect to a center of the die pad, and having the ends form inner lead connection surfaces parallel with at least one pair of sides of the die pad. In addition, there may be provided a semiconductor device having the lead frame. Accordingly, a semiconductor chip may be positioned on a die pad. The plurality of inner leads may be electrically connected to the semiconductor chip through wires. The semiconductor device may further include a molding resin for surrounding top and bottom surfaces of the lead frame and filling in an interior thereof.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: May 29, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jang-Mee Seo
  • Patent number: 8159063
    Abstract: A substrate of a micro-BGA package is revealed, primarily comprising a substrate core, a first trace, and a second trace where the substrate core has a slot formed between a first board part and a second board part. The first trace is disposed on the first board part and has a suspended inner lead extended into the slot where the inner lead has an assumed broken point. The second trace is disposed on the second board part and is integrally connected to the inner lead at the assumed broken point. More particularly, a non-circular through hole is formed at the assumed broken point and has two symmetric V-notches away from each other and facing toward two opposing external sides of the inner lead so that the inner lead at two opposing external sides does not have the conventional V-notches cutting into the inner lead from outside. Moreover, the inner lead will not unexpectedly be broken and the inner lead can easily and accurately be broken at the assumed broken point during thermal compression processes.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: April 17, 2012
    Assignee: Powertech Technology Inc.
    Inventor: Ching-Wei Hung
  • Patent number: 8159055
    Abstract: A semiconductor device includes a semiconductor element; a group of back-inner terminals coupled with the semiconductor element through bonding wires and arranged in an area array shape so as to be exposed inside of the bottom; a group of back-outer terminals arranged outside the group of back-inner terminals; a group of front-outer terminals located immediately above the back-outer terminals to be exposed from the front surface, which are electrically coupled with the back-outer terminals located immediately therebelow through coupling conductors, respectively; and a sealing resin which seals the semiconductor element and bonding wires and non-exposed portions of said back-inner terminals, back-outer terminals and front-outer terminals. On at least the respective terminal faces of said back-inner terminals, back-outer terminals and front-outer terminals, noble-metal plated layers are formed.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: April 17, 2012
    Assignee: Mitsui High-Tec, Inc.
    Inventors: Kiyoshi Matsunaga, Takao Shioyama, Tetsuyuki Hirashima
  • Patent number: 8125072
    Abstract: A device includes a semiconductor chip with a ring-shaped metal structure extending along the contour of a first main surface of the semiconductor chip. An encapsulation body encapsulates the semiconductor chip and defines a second main surface. An array of external contact pads attaches to the second main surface of the encapsulation body, and at least one external contact pad of the array of external contact pads electrically couples to the ring-shaped metal structure.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: February 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Josef Boeck, Klaus Aufinger, Herbert Knapp
  • Patent number: 7964956
    Abstract: The present disclosure describes a unique pin configuration for mounting of circuit packages to corresponding host circuit boards. For example, an apparatus according to embodiments herein comprises a circuit, a substrate, and multiple conductive leads. The substrate has a surface on which the circuit (e.g., an integrated circuit) is mounted. The multiple conductive leads extend, in an orthogonal manner relative to the surface, through the substrate to electrically connect the circuit to a host circuit board. According to one embodiment, each respective conductive lead of the multiple conductive leads has been altered to produce a contact element (e.g., an L-shaped bend, J-shaped bend, etc.) at an axial end of the respective conductive lead opposite the substrate to solder the axial end of the respective conductive lead (i.e., contact element) to a surface mount pad of the host circuit board.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: June 21, 2011
    Assignee: Oracle America, Inc.
    Inventor: Ashur S. Bet-Shliemoun
  • Patent number: 7884010
    Abstract: A wiring structure has a silicon layer, a backing layer provided on the silicon layer, the backing layer comprising a copper alloy containing a manganese, and a copper layer provided on the backing layer, and a diffusion barrier layer having an electrical conductivity, the diffusion barrier layer being provided at a region including an interface between the silicon layer and the backing layer, in which a manganese in the diffusion barrier layer is enriched compared with the backing layer.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: February 8, 2011
    Assignee: Hitachi Cable, Ltd.
    Inventors: Noriyuki Tatsumi, Tatsuya Tonogi
  • Patent number: 7855480
    Abstract: An AC generator, referred to as an alternator, is mounted on an automotive vehicle for supplying electric power to an on-board battery and other electric loads. The alternator includes a rectifier device for rectifying alternating current to direct current. The rectifier is composed of a minus-side heat-radiating plate on which six minus-side rectifier elements are mounted and a plus-side heat-radiating plate on which six plus-side rectifier elements are mounted. Each rectifier is mounted on the heat-radiating plate in the same manner, i.e., by forcibly inserting the rectifier element into a mounting hole formed in the heat-radiating plate. A disc portion of the rectifier element has an outer peripheral surface on which knurls are formed. The outer peripheral surface having the knurls is tapered so that the disc portion is easily inserted into the mounting hole while establishing a firm grip and a good heat-conductive contact between the rectifier element and the heat-radiating surface.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: December 21, 2010
    Assignee: Denso Corporation
    Inventors: Yuji Ito, Shigenobu Nakamura
  • Patent number: 7842948
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: November 30, 2010
    Assignee: NVIDIA Corporation
    Inventors: Brian S. Schieck, Howard Lee Marks
  • Patent number: 7838395
    Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Through hole vias (THV) are formed in the die extension region. A conductive plane or ring is formed in a center area on the active surface of the semiconductor die. The conductive plane or ring is coupled to a first contact pad for providing a first power supply potential to the active circuits. The conductive plane or ring is electrically connected to a first THV. A conductive ring is formed partially around a perimeter of the conduction plane or ring. The conductive ring is coupled to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: November 23, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Guruprasad G. Badakere, Zigmund R. Camacho, Lionel Chien Hui Tay
  • Patent number: 7821115
    Abstract: A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns 25 to 27 are formed. The heat dissipation patterns have a surface area broader than that of the lead patterns and have the heat dissipating electrode patterns disposed thereon.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Chihiro Sasaki, Yasuaki Iwata
  • Patent number: 7696631
    Abstract: Inner wire bond pads are formed within a peripheral region of a semiconductor chip and at least one bonding wire is attached to the inner wire bond pads. The semiconductor chip may be customized for a specific configuration of choice by wiring inner wire bond pads. Alternately, the bonding wires may be employed to reinforce a power network or a ground network. Further, the bonding wire may serve as a passive radio frequency (RF) component. In addition, the bonding wire may be used a heat conduction path to transfer heat from the semiconductor chip to the upper package housing.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Frederic Beaulieu, Mukta G. Farooq, Kevin S. Petrarca
  • Patent number: 7638872
    Abstract: A power semiconductor module is presented. The power semiconductor module has a substrate, a composite film, and a power semiconductor component between the substrate and the composite film. The composite film has a thin circuit-structured logic metal layer and a thick circuit-structured power metal layer and between them a thin electrically insulating plastic film. The composite film includes contact nubs, which provide bonding to the power semiconductor component. Feedthrough holes are provided between the logic metal layer and the power metal layer. The plastic film in the region of the respective through-plated hole includes a recess in a region that is free of the logic metal layer. A segment of a flexible thin wire extends through the free region of the logic metal layer and through the recess in the plastic film and is bonded to the logic metal layer and the power metal layer by means of bonding sites.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: December 29, 2009
    Assignee: Semikron Elektronik GmbH & Co. KG
    Inventors: Christian Goebl, Karlheinz Augustin
  • Patent number: 7602052
    Abstract: To prevent a semiconductor device which can be made to be small even though a big-sized chip is used and in which a MOSFET having a low on-resistance can be formed, a semiconductor device according to the invention includes a resin package; at least two main leads that are integrated within the resin package so as to constitute a chip mounting portion; a semiconductor chip mounted on the chip mounting portion; and first and second surface leads each electrically connected to an electrode formed on a surface of the semiconductor chip. The main leads and the first and second surface leads protrude outward along a bottom surface of the resin package, respectively.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: October 13, 2009
    Assignee: Panasonic Corporation
    Inventors: Satoshi Utsunomiya, Yoshihiro Takano
  • Patent number: 7598119
    Abstract: System and method for preventing resin-based adhesive from contacting a substrate to minimize resin bleed-out and contamination. A preferred embodiment comprises a semiconductor device having a die mounted on a substrate, first and second gold surfaces formed on the substrate, a trench formed between the first and second gold surfaces, resin-based adhesive applied to the first gold surface, and a heat sink bonded to the resin-based adhesive.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: October 6, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Sergio V. Martinez, Boon Hor Lee, Karen Lynne Robinson
  • Publication number: 20090243082
    Abstract: An integrated circuit package system includes: mounting an integrated circuit die adjacent to a lead; forming a first encapsulation around and exposing the integrated circuit die and the lead; and forming a planar interconnect between the integrated circuit die and the lead with the planar interconnect on the first encapsulation.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 1, 2009
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Abelardo Jr. Advincula
  • Patent number: 7595550
    Abstract: A form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design that is disposed about the form. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: September 29, 2009
    Assignee: Entorian Technologies, LP
    Inventors: James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr.
  • Patent number: 7579680
    Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: August 25, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: David Chong, Hun Kwang Lee
  • Patent number: 7563648
    Abstract: A lead frame (52, 100, 112) for a semiconductor device (die) package (50, 102, 110) is described. Each of the leads (60) in the lead frame (52, 100, 112) includes an interposer (64) having one end (66) disposed proximate the outer face (58) of the package (50, 102, 110) and another end (68) disposed proximate the die (14). Extending from opposite ends of the interposer (64) are a board connecting post (70) and a support post (74). A bond site (78) is formed on a surface of the interposer (64) opposite the support post (74). Each of the leads (60) is electrically connected to an associated input/output (I/O) pad (80) on the die (14) via wirebonding, tape bonding, or flip-chip attachment to the bond site (78). Where wirebonding is used, a wire electrically connecting the I/O pad (80) to the bond site (78) may be wedge bonded to both the I/O pad (80) and the bond site (78). The support post (74) provides support to the end (68) of the interposer (64) during the bonding and coating processes.(FIG. 3).
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: July 21, 2009
    Assignee: Unisem (Mauritius) Holdings Limited
    Inventors: Shafidul Islam, Daniel K. Lau, Romarico S. San Antonio, Anang Subagio, Michael H. McKerreghan, Edmunda G-O. Litilit
  • Patent number: 7554136
    Abstract: A micro device that is manufactured by semiconductor process and is electrically connected to outside for its operation. The micro device includes a circuit board, an electrode pad being provided on the circuit board, a lead substrate being provided substantially parallel to the circuit board, and a lead of conductive member being electrically connected to the electrode pad by being bent in a direction away from a surface of the lead substrate, one end of the lead being adhered to the lead substrate and the other end being a free end.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: June 30, 2009
    Assignee: Advantest Corporation
    Inventors: Fumikazu Takayanagi, Yoshiaki Moro, Hirokazu Sanpei
  • Patent number: 7504670
    Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 17, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Satoshi Shiraishi, Yoichi Kazama
  • Patent number: 7439612
    Abstract: In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars adapted to receive a die associated with an integrated circuit at one or more of the lead bars such that the one or more lead bars extend from opposite sides of the die. The leadframe structure also includes one or more support structures (e.g. lead support bars 26) adapted to help hold the lead bars together.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: October 21, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Patent number: 7420271
    Abstract: A heat conductivity and brightness enhancing structure for light-emitting diode, including a bracket having a cathode leg support. A bowl structure is formed on upper end of the cathode leg support for resting a light-emitting chip therein. At least one depression is formed on a bottommost section of the bowl for receiving an adhesive therein. The depression has a diameter or area smaller than the bottom face of the chip. The adhesive is filled into the depression for adhering one or more chip. The other portions of the bottom face of the bowl, which contact with the chip is free from the adhesive and can achieve good heat conduction and radiation effect. At least one column hole is formed in the cathode leg support from a hollow section of the bottom of the bracket to the depression of the bowl. During manufacturing procedure, the adhesive can be heated, molten and exhausted from the column hole. The column hole serves as a passage for air convection, whereby the heat generated by the chip can be dissipated.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: September 2, 2008
    Inventor: Hsin Fen Hsu
  • Patent number: 7323776
    Abstract: The elevated heat dissipating device of the present invention comprises a thermal substrate connecting onto a heat source and at least one heat conductive pipe connecting to the thermal substrate. The heat conductive pipe further comprises a connecting part connected to a top portion of the thermal substrate, and a bending part which is bended and extended upward away from the thermal substrate. A plurality of sets of heat fins connecting to end portions of the bending part of the heat conductive pipe are supported and elevated by the heat conductive pipe so that an air space is formed between the thermal substrate and the sets of heat fins. A fan locating on a top part of the heat fins, wherein a plurality of air passages are formed in between those heat fins so that cool air ventilates from the fan through the air passages of the heat fins to the thermal substrate.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: January 29, 2008
    Assignee: Thermaltake Technology Co., Ltd.
    Inventor: Pei-His Lin
  • Patent number: 7239008
    Abstract: A semiconductor apparatus includes a semiconductor pellet having electrodes thereon; a plurality of lead terminals, which electrically connect the electrodes of the semiconductor pellet to terminals formed on a substrate; and a molding member, which is filled around the semiconductor pellet and upper parts of the lead terminals. The plurality of lead terminals are shaped to be elongated strips and are arranged to extend out of the molding member toward the substrate.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: July 3, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Patent number: 7205658
    Abstract: A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 17, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jun Hong Lee, Hyung Jun Park, Hyeong No Kim, Kun A Kang
  • Patent number: 7190065
    Abstract: To enhance bonding accuracy to a lead electrode, while coping with narrowing pitch of the lead electrodes, a lead electrode, whose bonding surface is sharpened, is provided to a film substrate, and a protruding electrode is bonded to the lead electrode, while having a bonding surface of the lead electrode bite into the protruding electrode.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: March 13, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Munehide Saimen
  • Patent number: 7173328
    Abstract: A semiconductor package having a substrate mounted die. The die configured having active circuit components and a top surface having bond pads electrically connected with circuitry of the die. The bond pads commonly being formed above active circuit components. The bond pads being electrically interconnected with wire bonds to establish intra-chip electrical connection between circuitry of the die. Methods of forming such packages are also disclosed.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: February 6, 2007
    Assignee: LSI Logic Corporation
    Inventor: Ivor Barber
  • Patent number: 7151042
    Abstract: A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: December 19, 2006
    Assignee: Macronix International Co., Ltd.
    Inventors: Pei-Ren Jeng, Hsuan-Ling Kao
  • Patent number: 7151027
    Abstract: A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: December 19, 2006
    Assignee: Spansion LLC
    Inventors: Hiroyuki Ogawa, Yider Wu, Kuo-Tung Chang, Yu Sun
  • Patent number: 7119423
    Abstract: A semiconductor chip is mounted on the substrate so that the first group of electrodes faces the first group of leads and the second group of electrodes faces the second group of leads. The first group of leads extends in a direction away from the second group of electrodes. Each of the second group of leads extends so as to pass between the first group of electrodes and is formed to be bent in the region between first and second straight lines.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: October 10, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuhiro Urushido
  • Patent number: 7091545
    Abstract: A memory device and fabricating method thereof. In the memory device of the present invention, a substrate has a plurality of deep trenches, wherein the deep trenches formed in the adjacent rows are staggered. A deep trench capacitor and a control gate are disposed in each deep trench successively. Word lines are disposed on the control gates respectively, and each word line is electrically coupled to the control gate thereunder. Diffusion regions are disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors. Each diffusion region is electrically connected to the surrounding deep trench capacitor. Active areas are disposed on the rows of the control gates respectively along a second direction. The regions where each active area overlaps the control gates have at least one indentation.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: August 15, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Tieh Chiang Wu, Chien-Chang Huang, Chin-Ling Huang, Bo Ching Jiang, Yu-Wei Ting
  • Patent number: 7061084
    Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: June 13, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kun-Ching Chen, Yung I Yeh
  • Patent number: 6984884
    Abstract: A main lead (2) is a single body comprised of an inner lead (2a) and an outer lead (2b) which are integrally formed, the bonding wires are arranged in parallel and fixed onto the inner lead (2a) by the wire bonding portions (3b), and the outer lead are exposed from the mold resin to the outside for electrical connection, and a plurality of through holes (8) penetrating the main terminal lead are formed in the outer vicinity of the wire bonding portions (3b) within the inner lead (2a), and the through holes are arranged substantially in parallel to the arrangement direction of the wire bonding portions (3b) so as to correspond to the entire wire bonding portions (3b).
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: January 10, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masao Kikuchi, Dai Nakajima, Koichi Tsurusako, Kunihiro Yoshihara
  • Patent number: 6953989
    Abstract: A film carrier tape for mounting electronic devices thereon having a mounting unit in which a wiring pattern is formed by etching on a base material, wherein the mounting unit has a target mark to be a reference of an alignment for carrying out final defect marking in a target position on the mounting unit by marking means as a pattern formed on the base material by the etching, and a defect marking method using the same are provided.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: October 11, 2005
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventor: Tatsuya Kiriyama
  • Patent number: 6946726
    Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 20, 2005
    Assignee: Actel Corporation
    Inventor: Raymond Kuang
  • Patent number: 6919625
    Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: July 19, 2005
    Assignee: General Semiconductor, Inc.
    Inventors: Paddy O'Shea, Eamonn Medley, Finbarr O'Donoghue, Gary Horsman
  • Patent number: 6836010
    Abstract: Disposal and replacement of bonding pads is conducted easily and accurately. A semiconductor chip that includes bonding pads is fixed on a die pad. A relay chip is fixed on the semiconductor chip via an insulating material. The relay chip includes bonding pads that are interconnected via a wiring pattern, which includes a single-layer or multi-layer interconnection structure, and convert the disposition of the bonding pads of the semiconductor chip to a different direction. The bonding pads of the semiconductor chip are connected to the bonding pads of the relay chip via wires, and the bonding pads of the relay chip are connected to bonding pads of a lead frame via wires.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: December 28, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoshihiro Saeki
  • Patent number: 6835004
    Abstract: An opto-electronic package is provided for mounting on a module base. The package comprises a generally rectangular package. An optical connector extends from a first side of the package body along an optical axis, generally parallel to the module base. A radio frequency connector extends from a second side of the package body along a RF axis, generally parallel to the module base. A plurality of electronic leads and mounting tabs each extend from at least one of the second side and a third side of the package body. A fourth side of the package body is adjacent the first side and free of connectors, leads, and mounting tabs for mounting the package in a corner of the module formed by first and second module walls. The fourth wall of the package body is positioned adjacent the first module wall and the optical connector extends through the second module wall.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: December 28, 2004
    Assignee: T-Networks, Inc.
    Inventors: Jason T. Iceman, Walter Jeffery Shakespeare, John Kai Andersen