Abstract: A circuit board utilizing thermocouples for improved heat dissipation performance from circuit boards includes a heat dissipation module which itself includes a first circuit substrate, a thermocouple, and a second circuit substrate. The first circuit substrate includes a first wiring layer comprising first and second wiring portions. The thermocouple includes a P-type and an N-type semiconductor. The second circuit substrate includes a second wiring layer with a third wiring portion. Conductive members electrically connect the P-type semiconductor with the first wiring portion, connect the P-type semiconductor with the third wiring portion, connect the N-type semiconductor with the second wiring portion, and connect the N-type semiconductor with the third wiring portion, to transfer away heat generated by working elements mounted on the board.

Abstract: A method for forming packaged electronic device structure includes providing a conductive leadframe. The leadframe can include a die pad and a plurality of conductive leads. The method can include coupling an electronic device to the plurality of conductive leads. The method can include providing an antenna structure, which can include a conductive pillar structure and an elongated conductive beam structure. The method can include providing a package body encapsulating the electronic device, at least portions of each conductive lead, and at least portions of the die pad. In an example, the conductive pillar structure can extend from the first package body surface to the second package body surface, the elongated conductive beam structure can be disposed adjoining the first package body surface and can be electrically connected to the conductive pillar structure, and a portion of the elongated conductive beam structure can be exposed outside of the package body.

Abstract: A printed circuit board including a dielectric insulation layer having a top side facing a first side and a bottom side opposite the first side that faces a second side of the dielectric insulation layer, at least one conducting track formed on the dielectric insulation layer, and one or more conductor rails, wherein each of the one or more conductor rails is mechanically coupled to the dielectric insulation layer, and a first portion of each of the one or more conductor rails is arranged on the first side and a second portion of each of the one or more conductor rails is arranged on the second side of the dielectric insulation layer.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.

Abstract: A power semiconductor device includes an insulating substrate on which a first conductor layer is arranged on one surface, a first conductor that is connected to the first conductor layer via a first connecting material, and a semiconductor element that is connected to the first conductor via a first connecting material. When viewed from a direction perpendicular to an electrode surface of the semiconductor element, the first conductor includes a peripheral portion formed larger than the semiconductor element. A first recess is formed in the peripheral portion so that a thickness of the first connecting material becomes thicker than other portions.

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

Abstract: The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

Abstract: Electronic packages and modules are described. In an embodiment, a hybrid thermal interface material including materials with different thermal conductivities is used to attach a lid to a device. In an embodiment, a low temperature solder material is included as part of an adhesion layer for attachment with a stiffener structure.

Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.

Abstract: A coil component is capable of suppressing occurrence of peeling at an interface between a coil conductor and resin in a magnetic portion due to heating during mounting. The coil component includes an element body that includes a coil conductor formed by winding a conductive wire coated with an insulating film, and a magnetic portion that contains metal magnetic particles and resin, and external electrodes that are electrically connected to exposed surfaces of extended portions of the coil conductor exposed on a surface of the element body, and are arranged on the surface of the element body. The metal magnetic particles are arranged in recesses formed in a surface of the conductive wire in the extended portions of the coil conductor.

Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.

Abstract: A multi-feed packaged antenna based on fan-out package, which relates to packaged antennas. A first passivation layer is arranged under a packaging layer, and first and second redistribution layers are arranged on the first passivation layer to build the multi-feed packaged antenna. Connecting ends of multiple channels of a chip are connected to a feed structure of a packaged antenna. A metal layer of the feed structure is achieved by the first redistribution layer, and the second redistribution layer is mainly configured to package an antenna. The coaxial feed is adopted herein, in which two redistribution layers are provided, by which a multi-port power combining can be achieved on the antenna, providing a wide-beam performance.

Abstract: An object is to provide a technique capable of improving heat dissipation while maintaining the workability of a product in a semiconductor device. A semiconductor device includes power chips, control chips configured to control the power chips, power side terminals, control side terminals, and a mold resin covering the power chips, the control chips, one ends side of the power side terminals, and one ends side of the control side terminals. An other ends side of the power side terminals and an other ends side of the control side terminals protrude horizontally from a side surface of the mold resin and bend downward at middle parts thereof. Of the power side terminals and the control side terminals, only on the other ends side of the power side terminals, heat dissipation portions protruding in a direction approaching or away from the mold resin from portions bent downward are formed.

Abstract: A semiconductor package for double sided cooling includes a first and a second carrier facing each other, at least one power semiconductor chip arranged between the first and second carriers, external contacts arranged at least partially between the first and second carriers, and spring elements arranged between the first and second carriers and configured to keep the first and second carriers at a predefined distance from each other.

Abstract: A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

Abstract: Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.

Abstract: An anti-tamper layer is applied to a blank wafer. The layered wafer is then diced into shield dies. A shield die is oxide-to-oxide bonded to the top of an active die such that removing the shield die will damage the active die. The shield die may be sized and positioned such that wirebond pads along one or more edges of the active die remain exposed. The exposed wirebond pads may be used to electrically connect, via wirebonds, the active die to a substrate. A second shield die may be attached to the bottom of the active die to help protect against the use of bottom-to-top delayering.

Abstract: A semiconductor device includes: a first semiconductor element having a first electrode on a main surface side thereof and a second electrode on a back surface side thereof; a base material provided with a connection conductor connected to the first electrode; a sealing resin provided on the base material to seal the first semiconductor element; and a first via provided in the sealing resin and electrically connected to the second electrode of the first semiconductor element.

Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.

Abstract: The semiconductor device includes a semiconductor element, a plurality of terminal electrodes, internal wiring, and a sealing material. The semiconductor element is mounted on a circuit pattern provided on an insulating substrate. The plurality of terminal electrodes are provided on a case in which the insulating substrate and the semiconductor element are contained. The internal wiring connects the semiconductor element and the plurality of terminal electrodes. The sealing material fills a space in the case. The internal wiring includes a plurality of circuit patterns, a plurality of metal blocks, and metal wire. The plurality of metal blocks are electrically connected to the respective circuit patterns. The metal wire connects the plurality of metal blocks and is bonded to the plurality of metal blocks at positions closer to an upper surface of the sealing material than surfaces of the plurality of circuit patterns.

Abstract: A multilayer electronic component includes an element body including a plurality of base layers stacked in a first direction, an inner conductor disposed in the element body, and a mounting terminal connected to the inner conductor. The multilayer electronic component has a mount surface positioned on a mounted side when the multilayer electronic component is mounted. The mount surface is disposed so as not to intersect an axis along the first direction. The mounting terminal is disposed on the mount surface and embedded from the mount surface into the element body.

Abstract: An electronic component module includes a first board comprising a component insertion portion, at least one heat-generating component mounted on a first surface of the first board and in which at least a portion of an active surface is exposed through the component insertion portion, a radiating component inserted into the component insertion portion and mounted on the active surface of the heat-generating component, a second board mounted on a second surface of the first board and configured to electrically connect the first board to an external source, and a connection conductor disposed on an inactive surface of the radiating component and configured to allow contact between the inactive surface of the radiating component and a main board.

Abstract: An antenna module includes: an antenna substrate including an antenna pattern; a semiconductor package disposed on a lower surface of the antenna substrate, electrically connected to the antenna substrate, and having at least one semiconductor chip embedded therein; and an electronic component disposed on the lower surface or a side surface of the antenna substrate, electrically connected to the antenna substrate, and spaced apart from the semiconductor package by a predetermined distance. The electronic component has a thickness greater than that of the semiconductor chip.

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

Abstract: A display panel (300) equipped with a display region (301) in which a plurality of switching elements (303) are positioned, a plurality of supply circuits (10) which supply a scanning signal the switching elements (303) and are arranged in a first direction in the periphery of the display region (301), a plurality of first signal lines (11, 12, 13, 14) which supply a prescribed signal to the supply circuits (10), extend in the first direction, and are arranged in a second direction which intersects the first direction, and a plurality of second signal lines (40, 41) which supply the prescribed signal to the supply circuits (10) and connect the first signal lines (11, 12, 13, 14) and the supply circuits (10) to one another, the display panel (300) being characterized in that some of the second signal lines (40, 41) have a meandering section (4a) that meanders in the portion thereof that overlaps the connected first signal lines (12, 13, 14).

Abstract: There is disclosed herein a contactor for production testing of an electrical product, where the contactor includes an integrated circuit with memory. The integrated circuit may store information related to the contactor in the memory that may be useful for the production testing. For example, the memory may store information that that can be used for identifying the contactor and/or determining whether maintenance of the contactor should be performed to achieve proper results of the production testing.

Abstract: A method includes placing a device die and a pre-formed dielectric block over a first carrier, encapsulating the device die and the pre-formed dielectric block in an encapsulating material, grinding a top side of the encapsulating material to expose the top side of the pre-formed dielectric block, removing the carrier from the encapsulating material, the pre-formed dielectric block, and the device die to reveal a bottom side of the pre-formed dielectric block, and forming a ground panel, a feeding line, and a patch on the encapsulating material. The ground panel, the feeding line, the patch, and the pre-formed dielectric block form a patch antenna.

Abstract: A receiver module includes: a photodiode; a carrier configured to mount the photodiode; a base having a surface on which the carrier is mounted; a conductive pattern provided on the carrier, being conductively joined to a cathode electrode of the photodiode; a transimpedance amplifier having a first terminal connected to the conductive pattern through a bonding wire and a second terminal electrically connected to an anode electrode of the photodiode; and a capacitor having a first end electrically connected to the conductive pattern through a conductor having inductance smaller than inductance of the bonding wire and a second end electrically connected to the surface of the base.

Abstract: A semiconductor device package includes a transparent substrate, a photo detector and a first conductive layer. The transparent substrate has a first surface and a first cavity underneath the first surface. The photo detector is disposed within the first cavity. The photo detector has a sensing area facing toward a bottom surface of the first cavity of the transparent substrate. The first conductive layer is disposed over the transparent substrate and electrically connected to the photo detector.

Abstract: A busbar includes an opening, a first terminal, and a second terminal. The first terminal includes a first terminal piece with a step-like bent shape, in which the first terminal piece is bent from a conductor along a bending line, and a plurality of hole portions formed on the first terminal piece and arrayed in a direction parallel to the bending line. The second terminal includes a second terminal piece with a step-like bent shape, in which the second terminal piece is bent from a conductor along a bending line, and a plurality of hole portions formed on the second terminal piece and arrayed in a direction parallel to the bending line. The busbar balances the current sharing in a current that flows through a plurality of fastening points.

Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.

Abstract: A support substrate has first electric contacts in a front face. An electronic component is located above the front face of the support substrate and has second electric contacts facing the first electric contacts of the support substrate. An electric connection structure is interposed between corresponding first and second electric contacts of the support substrate and the electronic component, respectively. Each electric connection structure is formed by: a shim that is made of a first electrically conducting material, and a coating that is made of a second electrically conducting material (different from the first electrically conducting material). The coating surrounds the shim and is in contact with the corresponding first and second electric contacts of the support substrate and the electronic component.

Abstract: A semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The antenna structure is disposed within the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.

Abstract: The present disclosure provides a semiconductor structure including a first insulation, a second insulation over the first insulation, a third insulation over the second insulation, a first conductor proximal to a boundary between the first insulation and the second insulation, and an electronic device electrically connected to the first conductor and at least partially surrounded by the second insulation. A coefficient of thermal expansion (CTE) of the second insulation is larger than a CTE of the first insulation and larger than a CTE of the third insulation.

Abstract: A circuit board includes a circuit substrate, a heat dissipation dielectric film and a ground circuit board stacked orderly. At least one conductive structure passes through the heat dissipation dielectric film to electrically connect the circuit substrate and the ground circuit board. An insulating layer is disposed on a side of the circuit substrate facing away from the heat dissipation dielectric film. The circuit board further includes at least one connecting unit. Each connecting unit passes through the insulating layer to be electrically connected to the circuit substrate. A height of each connecting unit is gradually increased from a center of the connecting unit to a periphery of the connecting unit. A method for manufacturing a circuit board is provided.

Abstract: A reverse-conducting semiconductor device includes a semiconductor chip having a top surface, a first side and a second side orthogonal to the first side in a plan view, in which a plurality of transistor regions and a plurality of diode regions are alternately arranged and an upper-electrode is provided on top surface-sides of the transistor regions and the diode regions; and a wiring member having a flat-plate portion having a rectangular-shape which is metallurgically jointed to the upper-electrode via a joint member above the diode regions. The wiring member has a conductive wall rising from a bending edge of the flat-plate portion in a direction opposite to the upper-electrode, and the bending edge of the flat-plate portion is arranged parallel to the first side.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize at least one modular core dice to reduce the cost of manufacture. The modular core dice include at least two die disposed on a wafer segment that are separated by a scribe lane. In one example, a chip package assembly is provided that includes an interconnect substrate stacked below a first wafer segment. The first wafer segment has a first die spaced from a second die by a first scribe lane. The interconnect substrate has conductive routing that is electrically connected to the first die and the second die through die connections.

Abstract: A semiconductor package includes a package substrate including a die attachment region, a semiconductor die attached to the die attachment region, and a die over-shift indicating pattern disposed on or in the package substrate and spaced apart from the die attachment region. The die over-shift indicating pattern is used as a reference pattern for obtaining a shifted distance of the semiconductor die.

Abstract: Disclosed are a display panel and a display device including the same, in which each of non-display area lines, provided in an outer side among a plurality of non-display area lines connecting a driving driver to a plurality of display area lines provided in a display area, includes two electrodes electrically connected to each other with an insulation layer therebetween.

Abstract: The implementations described herein generally relate to a sensing device for use in the semiconducting industry, which sense process parameters to control semiconductor processes. More specifically, the implementations relate to packaging for a surface acoustic wave (SAW) based devices or wireless or RF-responsive sensors for use in the harsh processing environments of a semiconductor processing chamber such that the neither the sensor and its components nor the chamber components interfere with or contaminate one another. The sensor packaging may include various packaging layers with or without protective coatings and a waveguide. The packaging may have a thickness chosen such that the thickness is less than the electromagnetic wavelength of a SAW sensor radio wave. The sensing devices may be disposed in cavities of the chamber, the processing volume, on chamber components, and/or on the substrate.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RthJC) compared to a conventional IPM.

Abstract: A substrate packaging structure includes: a first substrate and a second substrate that are electrically connected; a plurality of conductive blocks arranged on each one of the first substrate and the second substrate, and electrically connected to each other; first and second conductive areas respectively formed on upper and side surfaces of the first substrate; a first reference conductive area formed below the upper surface of the first substrate and electrically connected to the first and second conductive areas; third and fourth conductive areas respectively formed on upper and side surfaces of the second substrate; and a second reference conductive area formed below the upper surface of the second substrate and electrically connected to the third and fourth conductive areas. The first conductive area on the first substrate is electrically connected to the third conductive area on the second substrate.

Abstract: An electronic device includes a component carrier with a component carrier body, an electrically conductive layer, and an adhesive structure. The electronic device further includes an electronic component which is arranged within the component carrier body. The adhesive structure is formed between a surface of the electronic component and the electrically conductive layer and covers only a part of the surface of the electronic component. A remaining part of the surface of the electronic component is covered with the component carrier body.

Abstract: A fan-out line component, a display device comprising the same, and a fan-out line wiring method are disclosed. The fan-out line component is used for signal connection between a first functional region and a second functional region. A channel in an intermediate section of a channel wire outlet end of the first functional region is a dummy channel. A first wiring from an effective signal channel in the first functional region which is closest to the dummy channel to the second functional region extends to a central normal region of the dummy channel, and then extends in the central normal region along a direction of a central normal.

Abstract: In a semiconductor device, first to fourth circuit patterns are formed on an insulating substrate in a case. A first end of a first lead frame is connected via solder to the first circuit pattern and another end of the first lead frame extends outside from the case. In the same way, a first end of a second lead frame is connected via solder to the fourth circuit pattern and another end extends outside from a case. Portions of the second and third circuit patterns are covered by the first lead frame and are respectively buried by insulating layers. In addition, a semiconductor element is provided via solder on a region of the first lead frame above the first circuit pattern. Wires electrically connect the semiconductor element and a region of the second lead frame above the fourth circuit pattern.

Abstract: Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assist in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assist in impedance matching.

Abstract: Lithium silicate-diopside glass ceramics are described which are characterized by a controllable translucence and can be satisfactorily processed mechanically and therefore can be used in particular as restoration material in dentistry.

Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.