With Particular Lead Geometry Patents (Class 257/692)
  • Patent number: 10804191
    Abstract: A printed wiring board includes a first build-up layer having first insulating layer, conductor layer and via conductor, a second build-up layer formed on the first build-up layer and having second insulating layer, conductor layer and via conductor, a third build-up layer formed on the second build-up layer and having third insulating layer, conductor layer and via conductor, and a fourth build-up layer formed on the third build-up layer and having fourth insulating layer, conductor layer and via conductor. The first insulating layer has a thickness that is larger than a thickness of the second insulating layer, the thickness of the second insulating layer is larger than a thickness of the third insulating layer, the thickness of the second insulating layer is larger than a thickness of the fourth insulating layer, and the thickness of the fourth insulating layer is larger than the thickness of the third insulating layer.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: October 13, 2020
    Assignee: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Yoji Sawada
  • Patent number: 10790257
    Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Juan Eduardo Dominguez, Hyoung Il Kim
  • Patent number: 10777498
    Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: September 15, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chiao-Ling Huang, Tai-Hung Lin
  • Patent number: 10756015
    Abstract: A semiconductor package including a package substrate, a semiconductor chip on a first surface of the package substrate, a connection substrate on the package substrate and spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the semiconductor chip and the package substrate and electrically connecting the semiconductor chip to the package substrate, a plurality of second connecting elements between the connection substrate and the package substrate and electrically connecting the connection substrate to package substrate, a mold layer encapsulating the semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the semiconductor chip and electrically connected to a corresponding one of the plurality of conductive connection structures may be provided.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokhyun Lee, Kyung Suk Oh
  • Patent number: 10748830
    Abstract: A wiring board (2) is provided on a heat radiation plate (1). A semiconductor chip (8) is provided on the wiring board (2). A case housing (10) is provided on the heat radiation plate (1) and surrounds the wiring board (2) and the semiconductor chip (8). Adhesive agent (11) bonds a lower surface of the case housing (10) and an upper surface peripheral portion of the heat radiation plate (1). A sealing material (13) is filled in the case housing (10) and covers the wiring board (2) and the semiconductor chip (8). A step portion (16,17) is provided to at least one of the lower surface of the case housing (10) and the upper surface peripheral portion of the heat radiation plate (1). A side surface of the heat radiation plate (1) and an outer side surface of the case housing (10) are flush with each other.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: August 18, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukimasa Hayashida, Daisuke Oya, Takayuki Matsumoto, Ryutaro Date
  • Patent number: 10734300
    Abstract: A semiconductor device according to the present invention includes the following: a conductive layer disposed on an insulating substrate; a first semiconductor element and a second semiconductor element that are joined on an opposite surface of the conductive layer opposite from the insulating substrate, with a gap the first semiconductor element and the second semiconductor element; an electrode joined on an opposite surface of the first semiconductor element opposite from the conductive layer, and an opposite surface of the second semiconductor element opposite from the conductive layer, so as to extend over the gap; and resin sealing the conductive layer, the first semiconductor element, the second semiconductor element, and the electrode. The conductive layer has a recess pattern that is disposed on a surface being opposite from the insulating substrate and facing the gap, the recess pattern extending along the gap.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: August 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mitsugu Tanaka, Yusuke Ishiyama, Akitoshi Shirao
  • Patent number: 10720340
    Abstract: The invention relates to a mould for encapsulating electronic components mounted on a carrier, with at least two mould parts which are displaceable relative to each other for engaging with a mould cavity round electronic components, and at least one feed for encapsulating material recessed into the mould parts and connecting to the mould cavity. The invention also relates to a carrier with encapsulated electronic components. The invention further relates to a method for encapsulating electronic components and to the thus manufactured encapsulated separated components.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 21, 2020
    Assignee: Besi Netherlands B.V.
    Inventor: Michel Hendrikus Lambertus Teunissen
  • Patent number: 10700027
    Abstract: Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yusheng Lin
  • Patent number: 10685909
    Abstract: A semiconductor device package includes a lead frame, a first power semiconductor device mounted on a first part of the lead frame and a second power semiconductor device mounted on a second part of the lead frame. The first power semiconductor device is encapsulated by a first mold compound. The second power semiconductor device is encapsulated by a second mold compound. The first mold compound and the second mold compound are substantially separate from each other. The lead frame includes an intermediate part arranged between the first part and the second part. The intermediate part is not covered by the first mold compound or by the second mold compound.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: June 16, 2020
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Martin Gruber
  • Patent number: 10658324
    Abstract: A semiconductor device includes: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate; a plating formed on a surface of the aluminum pattern; and a semiconductor element joined to the plating, wherein a thickness of the plating is 10 ?m or more.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Murata, Yuji Imoto
  • Patent number: 10658257
    Abstract: A semiconductor package structure includes a semiconductor die, at least one wiring structure, an encapsulant and a plurality of conductive elements. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The encapsulant surrounds the semiconductor die. The encapsulant is formed from an encapsulating material, and a Young's Modulus of the encapsulant is from 0.001 GPa to 1 GPa. The conductive elements are embedded in the encapsulant, and are electrically connected to the at least one wiring structure.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 19, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Dao-Long Chen, Chih-Pin Hung, Ming-Hung Chen
  • Patent number: 10658320
    Abstract: A semiconductor device is provided and includes a first pad and a second pad, a first conductive connector and a second conductive connector, a first conductive structure and a second conductive structure. The first conductive connector and the second conductive connector are disposed over the first pad and the second pad. The first conductive structure is electrically connected to the first pad and the first conductive connector, and includes a first portion, a second portion and a connecting portion connecting the first and second portions. The first portion and the second portion are not overlapped in a vertical direction, and the first portion, the connecting portion and the second portion are integrally formed. The second conductive structure is electrically connected to the second pad and the second conductive connector, wherein a portion of the second conductive structure is overlapped with the first conductive structure therebeneath in the vertical direction.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 19, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chun-Hung Lin, Yen-Jui Chu, Kao-Tsair Tsai
  • Patent number: 10647570
    Abstract: A process for fabricating a symmetrical MEMS accelerometer.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: May 12, 2020
    Assignee: Chinese Academy of Sciences Institute of Geology and Geophysics
    Inventors: Lianzhong Yu, Chen Sun, Leiyang Yi
  • Patent number: 10643945
    Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Andrew Collins, Bharat P. Penmecha, Rajasekaran Swaminathan, Ram Viswanath
  • Patent number: 10638633
    Abstract: A power module includes a heat-dissipating substrate, a first planar power device and a second planar power device. The first planar power device includes a plurality of electrodes disposed on an upper surface of the first planar power device. The second planar power device includes a plurality of electrodes disposed on an upper surface of the second planar power device. Lower surfaces of the first planar power device and the second planar power device are disposed on the heat-dissipating substrate.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 28, 2020
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventor: Jian-Hong Zeng
  • Patent number: 10629555
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Wei Chen, Jie Chen
  • Patent number: 10617005
    Abstract: A display device includes: a substrate including a display area positioned on a first surface and displaying an image and a peripheral area positioned around the display area; a first pad portion disposed on a second surface of the substrate as a surface opposite to the first surface of the substrate; a plurality of through-holes disposed on the peripheral area and penetrating the substrate; a plurality of connection wires disposed on the peripheral area and connecting the display area and the first pad portion through the plurality of through-holes; and a printed circuit board including a second pad portion coupled with the first pad portion.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Young Hoon Lee
  • Patent number: 10607856
    Abstract: A manufacturing method of a redistribution layer is provided. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier. Another manufacturing method of a redistribution layer is also provided.
    Type: Grant
    Filed: June 18, 2017
    Date of Patent: March 31, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Kun-Yung Huang, Chih-Fu Lung, Shih-Chi Li, Mei-Chen Lee, Chung-Hao Tsai, Chi-Liang Wang
  • Patent number: 10600741
    Abstract: Methods of manufacturing semiconductor packages with metal-plated shields include roughening surfaces of a molding compound by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. In one embodiment, the method includes obtaining a molded array including a plurality of dies coupled to a substrate and a molding compound encapsulating the plurality of dies, coating all exposed surfaces of the molding compound with an adhesion promoter material, heating the molded array with an adhesion promoter material such that the adhesion promoter material reacts with a portion of the molding compound, resulting in a baked film, and etching away the baked film, resulting in the molding compound having the roughened surfaces. Preferably, the method also includes depositing a catalyst material on the roughened surfaces before a metal layer is coated on the roughened surfaces to speed up the time for the metal layer to adhere to the roughened surfaces.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 24, 2020
    Assignee: Utac Headquarters PTE. LTD.
    Inventors: Suebphong Yenrudee, Chanapat Kongpoung, Sant Hongsongkiat, Siriwanna Ounkaew, Chatchawan Injan, Saravuth Sirinorakul
  • Patent number: 10600679
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member, the first semiconductor chip, and the second semiconductor chip, and a second connection member disposed on the first connection member and on active surfaces of the first semiconductor chip and the second semiconductor chip. A redistribution layer of the second connection member is respectively connected to both the first and second connection pads through first and second conductors, and the second conductor has a height greater than that of the first conductor.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Kim, Mi Ja Han, Dae Hyun Park
  • Patent number: 10599603
    Abstract: Some embodiments of the invention provide a novel method and chip design for a forwarding chip, that decouples input-output (IO) technology requirements from the technology used in a high bandwidth switching ASIC. In some embodiments, a main die including a latest generation switching chip is coupled to a set of IO dies (e.g., SerDes dies). The main die, in some embodiments, uses a latest technology (e.g., 7 nm nodes) while the IO dies, in some embodiments, use a more mature technology (e.g., 16 nm nodes). Some embodiments provide multiple IO dies that each provide connectivity to external components to the high bandwidth switching ASIC (e.g., a core ASIC die). The multiple dies are mounted on a silicon interposer, in some embodiments, using microbumps to make the connections between the dies and the silicon interposer. Additional connections to the pad are made from each die including to general purpose input-output (GPIO) connections.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: March 24, 2020
    Assignee: Barefoot Networks, Inc.
    Inventors: Anurag Agrawal, Alain Loge
  • Patent number: 10593643
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 17, 2020
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Patent number: 10593846
    Abstract: A semiconductor light-emitting device (101) includes an LED chip (4), a lead (1) having a main surface (11) on which the LED chip (4) is mounted, and a resin package (5) covering the LED chip (4). The main surface (11) is roughened, and the main surface (11) is held in contact with the resin package (5). These configurations contribute to the downsizing of the semiconductor light-emitting device (101).
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: March 17, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kentaro Mineshita
  • Patent number: 10566255
    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
  • Patent number: 10546808
    Abstract: The wiring substrate includes a cavity and a plurality of metal leads disposed around the cavity. The metal leads are bonded with a resin compound and provide horizontal and vertical routing for a semiconductor device to be disposed in the cavity. The resin compound fills in spaces between the metal leads and surrounds the cavity and provides a dielectric platform for a re-distribution layer or a build-up circuitry optionally deposited thereon.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: January 28, 2020
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10546803
    Abstract: A semiconductor device includes an insulating circuit-substrate on which a semiconductor chip is mounted, a casing accommodating the insulating circuit-substrate, and a plate-shaped terminal-connecting member having both ends suspended so that the terminal-connecting member extends between two opposite side-walls of the casing, the terminal-connecting member having a connection-terminal and load-absorbing portions, the connection-terminal being provided in a central region between the both ends so as to be connected to the semiconductor chip, the load-absorbing portions being provided between fixing points to the casing and the central region, the rigidity of the load-absorbing portions in a longitudinal direction being equal to or less than 50% of the rigidity of the central region so that the load-absorbing portions absorb load applied from the two side-walls and are deformed.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: January 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tomonori Katano
  • Patent number: 10546800
    Abstract: A semiconductor module includes: a semiconductor device having an upper surface electrode; a conductor plate joined to the upper surface electrode via a bonding member; and a wire bonded to the conductor plate, wherein the wire is a metal thread or a ribbon bond, and the bonding member is a porous sintered metal material impregnated with resin.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasunari Hino, Yuji Sato
  • Patent number: 10541194
    Abstract: A semiconductor package includes a semiconductor die and a ceramic package body covering the semiconductor die. The ceramic package body includes a plurality of contact pads. Each of a first plurality of leads includes a top portion and a bottom portion. The top portion of each of the first plurality of leads is electrically connected to a contact pad of the plurality of contact pads. Each of a second plurality of leads includes a top portion and a bottom portion and an interconnection portion between the top portion and the bottom portion. The top portion of each of the second plurality of leads includes separate finger portions that are electrically connected to at least two of the plurality of contact pads.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Gail Holloway, Andy Quang Tran
  • Patent number: 10535812
    Abstract: A semiconductor device includes a semiconductor element, a conductive layer, terminals, and a sealing resin. The conductive layer, containing metal particles, is in contact with the reverse surface and the side surface of the semiconductor element. The terminals are spaced apart from and electrically connected to the semiconductor element. The sealing resin covers the semiconductor element. The conductive layer has an edge located outside of the semiconductor element as viewed in plan. Each terminal includes a top surface, a bottom surface, an inner side surface held in contact with the sealing resin, and the terminal is formed with a dent portion recessed from the bottom surface and the inner side surface. The conductive layer and the bottom surface of each terminal are exposed from a bottom surface of the sealing resin.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: January 14, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Yuya Hasegawa, Satohiro Kigoshi
  • Patent number: 10529593
    Abstract: A semiconductor package manufacturing method thereof are provided. The semiconductor package includes a high-power device die, a redistribution structure, a heat dissipation module and a molding compound. The high-power device die has a front side and a back side opposite to the front side. The redistribution structure is disposed at the front side. The heat dissipation module is in direct contact with the back side. The molding compound is disposed between the redistribution structure and the heat dissipation module, and surrounding the high-power device die. The molding compound has a body portion and an extended portion. An interface between the body portion and the heat dissipation module is substantially parallel to the back side of the high-power device die. A thickness of the extended portion is greater than a thickness of the body portion.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10510670
    Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen
  • Patent number: 10508027
    Abstract: The present disclosure provides a CMOS structure, including a substrate, a metallization layer over the substrate, a sensing structure over the metallization layer, and a signal transmitting structure adjacent to the sensing structure. The sensing structure includes an outgassing layer over the metallization layer, a patterned outgassing barrier over the outgassing layer; and an electrode over the patterned outgassing barrier. The signal transmitting structure electrically couples the electrode and the metallization layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jung-Huei Peng, Chia-Hua Chu, Fei-Lung Lai, Shiang-Chi Lin
  • Patent number: 10510716
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 10497657
    Abstract: A semiconductor package device is provided that includes a first circuit layer having a first conductive layer and a first stud bump and a second circuit layer having a second conductive layer and a second stud bump. The first stud bump has a first portion and a second portion, and the second portion of the first stud bump is electrically connected to the second conductive layer. The second stud bump has a first portion and a second portion, and the second portion of the second stud bump is electrically connected to the first conductive layer. The first stud bump partially overlaps the second stud bump in a direction substantially perpendicular to the first circuit layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 3, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10490478
    Abstract: A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 26, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Kuo-Shu Kao, Jing-Yao Chang, Tao-Chih Chang
  • Patent number: 10483182
    Abstract: An intermediate connector includes a power source bus bar as an elongated thin plate to be connected to each power source pad of a semiconductor integrated circuit, a ground bus bar as an elongated thin plate to be connected to each ground pad of the semiconductor integrated circuit, a thin film insulator layer formed between the power source bus bar and the ground bus bar, and a conductive path portion as an elongated thin plate including a plurality of conductive paths to be connected to each signal pad of the semiconductor integrated circuit. The power source bus bar, the ground bus bar, and the conductive path portion are arranged in parallel correspondingly to a parallel arrangement of a power source pad row, a ground pad row, and a signal pad row of the semiconductor integrated circuit.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: November 19, 2019
    Assignee: NODA SCREEN CO., LTD.
    Inventor: Seisei Oyamada
  • Patent number: 10468338
    Abstract: Performance of a semiconductor device is enhanced. A semiconductor device is a semiconductor device obtained by sealing in a sealing portion first, second, and third semiconductor chips each incorporating a power transistor for high-side switch, fourth, fifth, and sixth semiconductor chips each incorporating a power transistor for low-side switch, and a semiconductor chip incorporating a control circuit controlling these chips. The source pads of the fourth, fifth, and sixth semiconductor chips are electrically coupled to a plurality of leads LD9 and a plurality of leads LD10 via a metal plate. As viewed in a plane, the leads LD9 intersect with a side MRd4 of the sealing portion and the leads LD10 intersect with a side MRd2 of the sealing portion.
    Type: Grant
    Filed: July 29, 2018
    Date of Patent: November 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroya Shimoyama, Hiroyuki Nakamura
  • Patent number: 10462923
    Abstract: A power module includes a heat-dissipating substrate, a first planar power device and a second planar power device. The first planar power device includes a plurality of electrodes disposed on an upper surface of the first planar power device. The second planar power device includes a plurality of electrodes disposed on an upper surface of the second planar power device. Lower surfaces of the first planar power device and the second planar power device are disposed on the heat-dissipating substrate.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 29, 2019
    Assignee: DELTA ELECTRONICS (SHANGHAI( CO., LTD.
    Inventor: Jian-Hong Zeng
  • Patent number: 10461150
    Abstract: A semiconductor device includes a first transistor formed on a substrate and including first and second impurity regions, a second transistor formed on the substrate and including a third impurity region electrically connected to the second impurity region, and a fourth impurity region, a power supply terminal electrically connected to the first impurity region, a ground terminal electrically connected to the fourth impurity region, a first guard ring surrounding the first transistor in a plan view and electrically connected to the ground terminal, and a second guard ring surrounding the second transistor in a plan view and electrically connected to the ground terminal. A conductivity type of the first through fourth impurity regions is different from a conductivity type of the first and second guard rings. The second guard ring has a width narrower than a width of the first guard ring in a plan view.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: October 29, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Hidetoshi Tanaka
  • Patent number: 10438863
    Abstract: A chip package assembly, a package substrate and methods for fabricating the same are disclosed herein. In one example, a chip package assembly includes a package substrate, an IC die and a stiffener. The package substrate includes a first dam projecting from a top surface of the package substrate. The IC die and the stiffener are mounted to the top surface of the package substrate. The stiffener includes a bottom surface that is disposed adjacent to the first dam. At least one surface mounted component is mounted to a region of the package substrate defined between the stiffener and the IC die. An adhesive coupling the stiffener to the package substrate is in contact with the first dam.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 8, 2019
    Assignee: XILINX, INC.
    Inventors: Ronilo Boja, Inderjit Singh
  • Patent number: 10407298
    Abstract: The present disclosure relates to an electronic device. The electronic device comprises a substrate, a micro-electromechanical systems (MEMS) device and an attachment element. The substrate defines an opening penetrating the substrate. The MEMS device has an active surface facing away from the substrate and a sensing region facing toward the opening. The attachment element is disposed on the substrate and surrounding the opening and the sensing region of the MEMS device.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: September 10, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.
    Inventors: Soonheung Bae, Hoguen Yoon, Kyunghwan Sul, Dukyung Kim
  • Patent number: 10390435
    Abstract: A method for encasing an electrical unit includes connecting the electrical unit to a leadframe and encasing the electrical unit with a first plastic material to form an inner molded body, so that a plurality of contacts of the electrical unit project from the inner molded body. The inner molded body is punched out of the lead frame. The method also includes connecting at least one first contact and one second contact to a shunt resistor. The inner molded body is encased with a second plastic material to form an outer molded body.
    Type: Grant
    Filed: February 18, 2018
    Date of Patent: August 20, 2019
    Assignee: CONTINENTAL TEVES AG & CO. OHG
    Inventors: Jakob Schillinger, Dietmar Huber, Svenja Raukopf, Lothar Biebricher
  • Patent number: 10361174
    Abstract: An improvement is achieved in the heat dissipation property of an electronic device including power transistors. A semiconductor module includes first and second packages included in an inverter circuit. In the first package, a semiconductor chip having a high-side power transistor is embedded. In the second package, a semiconductor chip having a low-side power transistor is embedded. At the both wide surfaces of the first and second packages, first metal electrodes electrically coupled to respective collector electrodes of the power transistors and second metal electrodes electrically coupled to respective emitter electrodes of the power transistors are exposed. To the first and second metal electrodes of the first and second packages, four respective bus bar plates having areas larger than those of the first and second metal electrodes are joined.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Bando, Tomohiro Nishiyama
  • Patent number: 10361170
    Abstract: A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungeun Pyo, Jongbo Shim, Ji Hwang Kim, Chajea Jo, Sang-Uk Han
  • Patent number: 10355103
    Abstract: A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Choonghyun Lee, Heng Wu, Chun Wing Yeung, Jingyun Zhang
  • Patent number: 10340210
    Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yien Sien Khoo, Siew Kee Lee
  • Patent number: 10340245
    Abstract: A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 2, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Jin Seol, Yong Koon Lee
  • Patent number: 10325988
    Abstract: A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of dielectric regions disposed in the semiconductor layer. The dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Each dielectric region has a rounded-square cross-section in a horizontal plane perpendicular to the vertical direction. Adjacent ones of the dielectric regions are laterally separated by a narrow region of the semiconductor layer. Each dielectric region has a cylindrical field plate member centrally disposed therein. The cylindrical field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrical field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 18, 2019
    Assignee: Power Integrations, Inc.
    Inventors: Sorin Stefan Georgescu, Kamal Raj Varadarajan, Alexei Ankoudinov
  • Patent number: 10321582
    Abstract: A method of manufacturing a wiring board includes a stacking process in which N (N is an integer equal to or greater than 2) wiring layers, end portions of which include linear conductor patterns, are stacked, with the end portions superimposed, via substrates (insulating layers) provided among the wiring layers and a laminated plate is manufactured and a removing process in which the insulating layers around the end portions of the conductor patterns of the laminated plate are removed to machine the end portions into N flying leads projecting from an end face.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: June 11, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Jumpei Yoneyama
  • Patent number: 10290560
    Abstract: A semiconductor device according to the present disclosure includes an electrically conductive first electrode block, an electrically conductive submount, an insulating layer, a semiconductor element, an electrically conductive bump, and an electrically conductive second electrode block. The submount is provided in a first region of the upper surface of the first electrode block, and electrically connected to the first electrode block. The semiconductor element is provided on the submount, and has a first electrode electrically connected to the submount. The bump is provided on the upper surface of a second electrode, opposite the first electrode, of the semiconductor element, and electrically connected to the second electrode. A third region of the lower surface of the second electrode block is electrically connected to the bump via an electrically conductive metal layer. An electrically conductive metal sheet is provided between the metal layer and the bump.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: May 14, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoto Ueda, Kouji Oomori, Takayuki Yoshida, Takuma Motofuji