Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

Abstract: The invention relates to a lead frame assembly comprising a plurality of regularly arranged lead frames, each of which is suitable for electrically contacting components, comprises at least two lead frame elements distanced laterally by a recess and which are provided as electrical connections of different polarity, and has at least one anchoring element, which is suitable for anchoring a housing body of the component, the lead frame elements being thinned, flat regions of the lead frame, and the at least one anchoring element protrudes from a plane of the lead frame elements in the form of a pillar, and a plurality of connection elements, which in each case connects two lead frame elements of adjacent lead frames to one another, the two connected lead frame elements being provided as terminals of different polarity.

Abstract: The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

Abstract: A circuit board includes a core portion including a first cavity formed in one surface, and a second cavity formed in the other surface opposing the one surface and having a diameter different from a diameter of the first cavity; a first metal layer disposed on the one surface of the core portion; a second metal layer buried in the core portion; and a third metal layer disposed on the other surface of the core portion, wherein each of the first and second cavities of the core portion exposes at least a portion of the second metal layer.

Abstract: A power module includes: a first substrate having metal plates formed on one surface thereof; a second substrate spaced apart from the first substrate and having metal plates formed on one surface thereof facing the metal plates of the first substrate; a plurality of power elements disposed between the first substrate and the second substrate; a first electrode formed on the first substrate of each of the plurality of power elements; and a second electrode formed on the second surface of each of the plurality of power elements, where the plurality of power elements comprise a first power element in which the first electrode is bonded to the metal plates of the second substrate; and a second power element in which the first electrode is bonded to the metal plates of the first substrate.

Abstract: An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.

Abstract: A Microelectromechanical Systems (MEMS) device combining a MEMS layer and a Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuit (IC), and its fabrication method is provided. The fabrication method includes: processing the MEMS layer on a first semiconductor substrate, the MEMS layer including one or more movable structures and one or more anchor structures; processing one or more first contacts on the first semiconductor substrate, each first contact being processed into one of the anchor structures and being configured to bias that anchor structure; processing the CMOS IC on a second semiconductor substrate; processing one or more second contacts on the second semiconductor substrate, each second contact being connected to the CMOS IC; and bonding the first semiconductor substrate to the second semiconductor substrate such that each first contact directly contacts one of the second contacts. The method can allow fabricating the MEMS device without vapor HF etching.

Abstract: A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area.

Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.

Abstract: An electrical feedback barrier is configured to safely interconnect an intrinsically safe power supply to a non-intrinsically safe electrical load device in a hazardous environment. Electrical feedback from the non-intrinsically electrical load device is blocked by the electrical feedback barrier to protect the intrinsically safe power supply from adverse operating conditions. The electrical feedback barrier and the electrical load device are enclosed in an explosion-proof or flameproof enclosure for compliance with electrical equipment safety standards in the hazardous environment.

Abstract: An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.

Abstract: A compact inverter system includes a bus bar. The bus bar includes a terminal for connection to a positive terminal of a DC voltage supply. The compact inverter also includes a heat sink, a first transistor, and a second transistor. The first transistor has first and second terminals between which current is transmitted when the first transistor is activated, and a first gate terminal controlling the first transistor. The first terminal of the first transistor is thermally and electrically connected to the bus bar. The second transistor has first and second terminals between which current is transmitted when the second transistor is activated, and a second gate terminal controlling the second transistor. The first terminal of the second transistor is thermally and electrically connected to the heat sink. The first and second transistors are positioned between the bus bar and the heat sink. The first transistor is positioned between the second transistor and the bus bar.

Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.

Abstract: A wiring substrate includes: an insulating substrate including a base portion comprising a through hole having a first opening and a second opening, and a frame portion located on the base portion; and a heat dissipator disposed on a side of the base portion that is opposite to the frame portion so as to block the second opening, wherein an inner surface of the through hole faces a side surface of the heat dissipator with a clearance being provided between the inner surface of the through hole and the side surface of the heat dissipator.

Abstract: An integrated circuit with a fault reporting structure. The integrated circuit has at least one power MOSFET having a plurality of MOSFET cells with each MOSFET cell having a drain metal and a source metal, and the integrated circuit has a power MOSFET area for routing the drain metals and the source metals of the plurality of MOSFET cells. The fault reporting structure has a metal net routed in the power MOSFET area or in an area above or below the power MOSFET area.

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.

Abstract: A semiconductor device includes a semiconductor element, a first lead electrically connected to the semiconductor element, a sealing resin that covers the semiconductor element and a part of the first lead, and a recess formed in a surface flush with a back surface of the sealing resin. The sealing resin also has a front surface opposite to the back surface in a thickness direction, and a side surface connecting the front surface and the back surface to each other. The recess is formed, in part, by a part of the first lead that is exposed from the back surface of the sealing resin. The recess has an outer edge that forms a closed shape, as viewed in the thickness direction, within a region that includes the back surface of the sealing resin and the first lead.

Abstract: Disclosed are semiconductor package structure and semiconductor modules including the same. The semiconductor module includes a circuit board, a first semiconductor package over the circuit board, and a connection structure on the circuit board and connecting the circuit board and the first semiconductor package. The first semiconductor package includes a first package substrate. A difference in coefficient of thermal expansion between the connection structure and the circuit board may be less than a difference in coefficient of thermal expansion between the circuit board and the first package substrate.

Abstract: A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and an electronic component disposed on the substrate, and the first package component is mounted to the substrate. The package structure further includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot, the first foot and the second foot extend toward the substrate, the electronic component is covered by the ring structure and located between the first foot and the second foot, and the first package component is exposed from the ring structure.

Abstract: An integrated circuit (IC) package structure includes a chip, a redistribution layer (RDL) structure, a molding compound structure and an electromagnetic interference (EMI) shielding structure. The RDL structure is formed on the chip and electrically connected thereto. The molding compound layer is provided on outer surfaces of the chip and the RDL structure. The EMI shielding structure is provided on outer surfaces of the molding compound structure. The molding compound structure layer provided on outer surfaces of the chip and the RDL structure provide protection and reinforcement to multiple faces of the IC package structure; and the EMI shielding structure provided on outer surfaces of the molding compound structure provides EMI protection to multiple faces of the chip and the RDL structure. The IC package structure has upgraded structural strength, reliability and stability in use. A method of manufacturing the above IC package structure is also introduced.

Abstract: A method for making light emitting device LED arrays includes the steps of providing a plurality of LEDs having a desired configuration (e.g., VLED, FCLED, PLED); attaching the LEDs to a carrier substrate and to a temporary substrate; forming one or more metal layers and one or more insulator layers configured to electrically connect the LEDs to form a desired circuitry; and separating the LEDs along with the layered metal layers and insulator layers that form the desired circuitry from the carrier substrate and the temporary substrate.

Abstract: A power module includes a first substrate including a first metal plate, a second substrate spaced apart from the first substrate and having a second metal facing the first substrate, a plurality of power elements that are disposed between the first substrate and the second substrate and include a first electrode and a second electrode. The plurality of power elements include a first power element having the first electrode bonded to the second metal plate, and a second power element having the first electrode bonded to the first metal plate.

Abstract: A half-bridge module having two switching units, each of which includes multiple transistors connected in parallel and/or in series, in particular IGBTs or MOSFETs. The transistors are arranged on a first substrate. The half-bridge module has a temperature sensor matrix having a plurality of temperature sensors, and the temperature sensors are thermally connected to the transistors at least in some regions. A temperature sensor matrix is also provided.

Abstract: A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate.

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.

Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

Abstract: A semiconductor package includes a terminal pad having at least one first terminal lead structurally connected to the terminal pad, a semiconductor chip attached to an upper surface of the terminal pad by using a first adhesive, a heat radiation board attached to a lower surface of the terminal pad by using a second adhesive, and at least one second terminal lead electrically connected to the semiconductor chip. The second terminal lead is spaced apart from the terminal pad and is separated from the radiation board. The package further includes a metal clip electrically connecting the semiconductor chip to the second terminal lead, and a package housing covering parts of the first terminal lead, the second terminal lead, and the terminal pad. The package housing includes an adhesive spread space to expose the lower surface of the terminal pad.

Abstract: An electronic system includes a plurality of heat sources. At least two of the plurality of heat sources vary in height and each of the plurality of heat sources includes a first side and a second side. The electronic system also includes a substrate having a first side and a second side. The second side of each of the plurality of heat sources is positioned adjacent to the first side of the substrate. The electronic system further includes a cover member provided above the plurality of heat sources and a sintering thermal interface material provided between the cover member and the first side of one of the at least two heat sources that vary in height.

Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.

Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

Abstract: A display device includes a touch panel including touch and pad areas, and a touch printed circuit board including a contact portion in the pad area. The touch panel includes a touch signal line in the pad area, and the touch printed circuit board includes a touch lead signal line in the contact portion and connected to the touch signal line through an anisotropic conductive film. The touch lead signal line includes a first portion having a first width, a second portion having a second width smaller than the first width and a third portion between the first and second portions and having a third width between the first and second widths. An end of the touch signal line is on the first and third portions, and the third portion has a side profile having two or more different slopes.

Abstract: A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.

Abstract: A heat dissipation structure includes a heat dissipation portion and a heat storage portion. The heat dissipation portion has the heat receiving surface including the contact surface in contact with the semiconductor generating the heat, and dissipates the heat of the semiconductor in contact with the contact surface. The heat storage portion is arranged to sandwich the semiconductor. The heat storage portion has, for example, the heat storage opening portion in which the semiconductor is positioned, and surrounds the semiconductor. The heat storage portion is provided to he in contact with the heat receiving surface, and stores the heat of the semiconductor conducted through the heat dissipation portion.

Abstract: An ultrasonic probe includes a semiconductor chip in which an ultrasonic transducer is formed and an electrode pad electrically connected to an upper electrode or a lower electrode of the ultrasonic transducer is provided and a flexible substrate in which a bump electrically connected to the electrode pad is provided and the bump is disposed in a portion overlapping with a stepped portion of the semiconductor chip. Further, a height of a connection surface of the electrode pad of the semiconductor chip connected to the bump is lower than a height of a lower surface of the lower electrode.

Abstract: A method of manufacturing a package structure includes: forming a backside RDL structure on a carrier; forming TIVs on the backside RDL structure; mounting at least one passive device on the backside RDL structure, so that the at least one passive device is disposed between the TIVs; placing a die on the at least one passive device, so that the at least one passive device is vertically sandwiched between the die and the backside RDL structure; forming an encapsulant laterally encapsulating the die, the TIVs, and the at least one passive device; forming a front side RDL structure on a front side of the die, the TIVs, and the encapsulant; releasing the backside RDL structure from the carrier; and mounting a package on the backside RDL structure, wherein the package is electrically connected to the at least one passive device by conductive connectors and solders.

Abstract: An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack.

Abstract: According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.

Abstract: The present invention relates to a semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series.

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

Abstract: Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

Abstract: The present disclosure provides a method for fabricating a semiconductor device including providing a first semiconductor die, forming a connection dielectric layer above the first semiconductor die, forming a first bottom protection layer in the connection dielectric layer, forming a first conductive plate on the first bottom protection layer, and forming a first top protection layer on the first conductive plate. The first bottom protection layer and the first top protection layer are formed of manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, strontium ferrite, barium ferrite, lithium ferrite, lithium-zinc ferrite, single crystal yttrium iron garnet, or gallium substituted single crystal yttrium iron garnet.

Abstract: A semiconductor device includes a first electrode; a second electrode; a resin case surrounding the first electrode and the second electrode; and a resin insulating part made of a material the same as a material of the resin case and covering part of the first electrode and part of the second electrode inside the resin case. The resin insulating part contacts an inner wall of the resin case or is separated from the inner wall of the resin case. A move positioned between the first electrode and the second electrode is formed at the resin insulating part, and thus a space in which the resin insulating part does not exist or a material different from the resin insulating part is provided between the first electrode and the second electrode.

Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

Abstract: A production method for a micromechanical device having inclined optical windows. First and second substrates are provided. A plurality of through-holes is produced in the first and second substrate such that for each through-hole in the first substrate a congruent through-hole is produced in the second substrate, which overlap when the first substrate is placed over the second substrate. A slanted edge region is produced around a respective through-hole in the first and second substrate, the edge region being inclined at a window angle, two slanted edge regions situated on top of each other being congruent in a top view and being inclined at the same window angle. A window foil is provided having a structured window region, which covers the through-hole in a top view of the window foil in each case, the window foil forming an optical window slanted at the window angle above the respective through-hole.

Abstract: A vehicle and a network system are provided to operate the air conditioning apparatus of the vehicle when a passenger within the vehicle is left unattended. The vehicle transmits a signal via a vehicle network to rescue the rear passenger, thereby ensuring passenger safety. The vehicle includes an output device and a communicator configured to communicate with a user terminal, an air conditioner, a sensor. The sensor obtains a movement of the passenger and a controller outputs an identification image through the output device when a movement signal of the passenger exceeds a reference signal after the vehicle doors are closed.

Abstract: A microwave or radio frequency (RF) device includes an insulating substrate having a first surface and a second surface opposing the first surface. The device also includes a crossover conductor disposed on the first surface extending between a first edge of the first surface and a second edge of the first surface. The device also includes a depression in the second surface defined at least in part by (i) a third surface recessed in relation to the second surface, and (ii) at least one sidewall that extends between the second surface and the third surface. The device further includes a conductive coating formed over at least a portion of the second surface, the third surface, and the at least one sidewall, where the conductive coating is insulated from the crossover conductor by the insulating substrate.

Abstract: A power semiconductor is provided. The power semiconductor includes a gate, a source, a silicon chip and a drain. The source includes a first copper particle layer and a first metal layer. The first copper particle layer covers the upper surface of the first metal layer. The silicon chip is bonded to the lower surface of the first metal layer. The drain is bonded to the lower surface of the silicon chip. The thickness of the first copper particle layer is greater than the thickness of the first metal layer. All copper mentioned are of large grain copper with size greater than 0.25 um.

Abstract: An embedded package structure having a shielding cavity according to an embodiment of the present disclosure includes a device embedded in an insulating layer, and a shielding cavity enclosing the device, wherein the shielding cavity is defined by a shielding wall embedded in the insulating layer and surrounding the device on four sides, and first and second wiring layers which cover first and second end faces of the shielding wall and are electrically connected with the shielding wall; wherein a signal line leading-out opening is to formed between the first end face of the shielding wall and the first wiring layer, and a signal line connected with a terminal of the device is led, from the signal line leading-out opening, out of the shielding cavity.