With Particular Lead Geometry Patents (Class 257/692)
  • Patent number: 11232992
    Abstract: A power device package structure including a first substrate, a second substrate, at least one power device, and a package is provided. A heat conductivity of the first substrate is greater than 200 Wm?1K?1. The power device is disposed on the first substrate, and the second substrate is disposed under the first substrate. A heat capacity of the second substrate is greater than that of the first substrate. The package encapsulates the first substrate, the second substrate, and the power device.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: January 25, 2022
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventors: Hsin-Chang Tsai, Ching-Wen Liu
  • Patent number: 11222883
    Abstract: Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a first passive device, a plurality of through insulator vias (TIVs), an encapsulant, and a plurality of conductive connectors. The die has a front side and a backside opposite to each other. The first passive device is disposed aside the die. The TIVs are disposed between the die and the first passive device. The encapsulant laterally encapsulates the TIVs, the first passive device, and the die. The conductive connectors are disposed on the backside of the die, wherein the conductive connectors are electrically connected to the die and the first passive device by a plurality of solders.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 11201173
    Abstract: Provided are an array substrate, a display panel and a display device. The array substrate includes a display region and a peripheral region. The peripheral region includes a chip-on-film bonding region, and the peripheral region has a recessed structure configured to fill a bonding material. The recessed structure is between the chip-on-film bonding region and a lateral side of the array substrate. The chip-on-film bonding region is between the display region and the lateral side. By disposing a recessed structure configured to fill the bonding material in the peripheral region, a gap is difficult to occur between the chip-on-film in the chip-on-film bonding region and the array substrate, preventing entry of water vapor to cause corrosion of lead wires and short circuits of lead wires. The defect ratio of the array substrate, the display panel, and the display device is reduced, and the product quality is improved.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: December 14, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mookeun Shin, Hui Dong, Haifeng Xu, Guangying Mou, Wei Zhang, Kaiwen Wang
  • Patent number: 11195817
    Abstract: A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Chih-Yuan Chang
  • Patent number: 11195269
    Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: December 7, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Reynaldo Corpuz Javier, Alok Kumar Lohia, Andy Quang Tran
  • Patent number: 11183453
    Abstract: A method of manufacturing an electronic-component-embedded substrate includes forming a power-supplying metal layer on a base, forming through electrodes that are to be connected to the power-supplying metal layer on the power-supplying metal layer by an electrolytic plating method, forming a first wiring line by patterning the power-supplying metal layer, forming an interlayer insulating layer such that the interlayer insulating layer covers a portion of the first wiring line, and forming a second wiring line on at least a portion of the first wiring line and a portion of the interlayer insulating layer such that the second wiring line crosses, on the interlayer insulating layer, a portion of the first wiring line.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: November 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Iwamoto
  • Patent number: 11174157
    Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Yu-Hsuan Tsai, Yin-Hao Chen, Hsin Lin Wu, San-Kuei Yu
  • Patent number: 11177235
    Abstract: The semiconductor device includes a solder ball connected to a pad, and located below the pad, a first wiring electrically connected to the pad, and located above the pad, and a second wiring electrically connected to the first wiring. At this time, a width of the first wiring is greater than a width of the second wiring. Accordingly, high-frequency noise can be reduced while improving signal transmission characteristics.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Oikawa
  • Patent number: 11171111
    Abstract: An integrated circuit device comprises: a resin film that is flexible; a plurality of traces bonded on a surface of the resin film and arrayed in a specific direction; an IC chip bonded on the surface of the resin film, located offset to the traces in a direction perpendicular to the specific direction, and connected to the traces; and a protection pattern formed on the surface of the resin film, located in the specific direction with respect to a disposition region in which the IC chip and/or the traces are disposed, and formed of the same material as that of the traces.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: November 9, 2021
    Assignee: Synaptics Incorporated
    Inventors: Kazuhiro Okamura, Takeshi Okubo, Yuichi Nakagomi, Takefumi Seno
  • Patent number: 11169940
    Abstract: A wireline communications system is described. The wireline communications system includes a printed circuit board (PCB). The wireline communications system also includes a system on chip (SoC) die on the PCB. The wireline communications system further includes an external memory device coupled to a memory interface of the SoC die. The external memory device is coupled to the memory interface of the SoC die through a PCB trace. A length of the PCB trace is configured according to an operating speed of the memory interface.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Sunil Gupta, Scott Powers
  • Patent number: 11131689
    Abstract: Embodiments herein describe structures of low-force wafer test probes and formation thereof. Structures of low-force wafer test probes and their formation via gray scale etch or electroplating is described. Structures are described that include a lower base structure on top of a substrate and an upper blade structure on top of the lower base structure. In various embodiments, a crown of a C4 bump is accommodated by one or both of: i) a cavity present in the lower base structure; and ii) a height of the upper blade structure. Processes for fabricating probe structures are described that include forming lower base structures upon a substrate and forming upper blade structures on top of the lower base structures. The upper blade structures include at least one blade. Each of the blade(s) include a cutting edge that points toward a center point within the probe structure.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: David M. Audette, S J. Chey, Doreen D. DiMilia, Sankeerth Rajalingam, Grant Wagner
  • Patent number: 11114400
    Abstract: A semiconductor device includes a semiconductor die, a redistribution structure, a interconnection structure, and a thermal path structure. The redistribution structure includes an insulation layer over a first surface of the semiconductor die and a conductive trace separated from the first surface by the insulation layer. The conductive trace extends laterally over the first surface from a first end toward a second end that is electrically coupled to a bond pad on the first surface of the semiconductor die. The interconnection structure is coupled to the first end of the conductive trace. The thermal path structure provides a thermal path between the semiconductor die and the interconnection structure. In some embodiment, the thermal path structure comprises a thermal pad that passes through the insulation layer. In other embodiments, the thermal path structure comprises a dummy pad on the first surface of the semiconductor die.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 7, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD.
    Inventor: Cameron Nelson
  • Patent number: 11101191
    Abstract: The present invention includes embodiments of a semiconductor package designed to transfer heat from one or more bridges within the package to ambient external to the package in addition to conducting the heat through any semiconductor chips encapsulated within the package. A laminated substrate has one or more horizontal layer heat conduction paths and one or more vertical substrate heat conduction paths. The vertical substrate heat conduction paths collect heat from one or more of the horizontal layer heat conduction paths, and eventually conduct the heat out of the semiconductor package, e.g. into a lid or heat sink.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kamal K. Sikka, Hiroyuki Mori
  • Patent number: 11088075
    Abstract: Back-end-of-line layout structures and methods of forming a back-end-of-line layout structure. A metallization level includes a plurality of interconnects positioned over a plurality of active device regions. The plurality of interconnects have a triangular-shaped layout and a plurality of lengths within the triangular-shaped layout.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 10, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Souvick Mitra, Rainer Thoma, Harsh Shah, Anindya Nath, Robert J. Gauthier, Jr.
  • Patent number: 11081419
    Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: August 3, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Dong Seong Oh, Si Hyeon Go
  • Patent number: 11075168
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 11063200
    Abstract: A device for guiding charge carriers and uses of the device are proposed, wherein the charge carriers are guided by means of a magnetic field along a curved or angled main path in a two-dimensional electron gas or in a thin superconducting layer, so that a different presence density is produced at electrical connections.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 13, 2021
    Inventor: Helmut Weidlich
  • Patent number: 11056456
    Abstract: A semiconductor apparatus includes a base plate, a metal plate disposed on the base plate, a bonding material disposed between the base plate and the metal plate to be in surface-to-surface contact with the base plate and the metal plate to bond the metal plate to the base plate, an insulating plate disposed on the metal plate, a circuit member disposed on the insulating plate to be in surface-to-surface contact with the insulating plate, a semiconductor device mounted on the circuit member, and an encapsulating material covering the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor device to encapsulate an area over the base plate, wherein a bottom face area of the metal plate along the outer perimeter of the metal plate is not covered with the bonding material, wherein the base plate has a groove-shape recess that is disposed along the outer perimeter of the metal plate to face the bottom surface area, wherein the recess has an area having a first depth and a
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 6, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hirotaka Oomori, Takashi Tsuno
  • Patent number: 11049894
    Abstract: An image sensor package includes a transparent material, and a substrate adhered to the transparent material. An image sensor is disposed on or within the substrate so that the image sensor is disposed between the substrate and the transparent material to receive light from an optical side of the image sensor package through the transparent material. A solder mask dam is disposed between the substrate and the transparent material to form a gap between the image sensor and the transparent material, and the solder mask dam is structured to indicate an orientation of the image sensor, when the image sensor is viewed from the optical side.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 29, 2021
    Assignee: OmniVision Technologies, Inc.
    Inventor: Chien-Chan Yeh
  • Patent number: 11037915
    Abstract: An IC chip comprises LED devices exposed on a front side of the IC chip, I/O bumps on a back side of the IC chip, a first die forming a stack with the LED devices and comprising driver circuits electrically connected to the LED devices, a first circuit that extends along the vertical direction from the front side of the IC chip towards a back side of the IC chip and across at least a thickness of the first die to provide electrical connections between the LED devices and at least some of the I/O bumps, a second die including pipelining circuits and control circuits for the driver circuits, a second circuit that extends from the second die, and a circuit board electrically connected to the I/O bumps and to a power system.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 15, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 11031345
    Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: June 8, 2021
    Assignee: Medtronic, Inc.
    Inventors: Chunho Kim, Mark R. Boone, Randolph E. Crutchfield
  • Patent number: 11018135
    Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 11004818
    Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 10971297
    Abstract: In an exemplary embodiment, a passive component which is a surface mounting component, includes: a substrate body 10 having insulation property; an internal conductor 50 embedded in the substrate body 10; and an external electrode 70 provided on the bottom face 12, which is the mounting surface, of the substrate body 10 and electrically connected to the internal conductor 50; wherein the external electrode 70 has a face 86 roughly parallel with the bottom face 12 of the substrate body 10, and a dome-shaped projection 80 that bulges, with reference to the roughly parallel face 86, away from the bottom face 12 of the substrate body 10. The passive component can prevent misalignment problems at mounting.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: April 6, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Takayuki Arai, Masanori Nagano
  • Patent number: 10957673
    Abstract: A semiconductor device of an embodiment includes a metal layer; a semiconductor chip on the metal layer and having an upper electrode and a lower electrode; a first wiring board electrically connected to the upper electrode, and includes a first, a second, a third plate-shaped portion, the first plate-shaped portion being parallel to the second plate-shaped portion, and the third plate-shaped portion being connected to the first and the second plate-shaped portion; a second wiring board electrically connected to the metal layer, and includes a fifth, a sixth, and a seventh plate-shaped portion, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to the fifth and the sixth plate-shaped portion. The first and the second plate-shaped portion are provided between the fifth and the sixth plate-shaped portion, and the semiconductor chip is positioned between the fifth and the sixth plate-shaped portion.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 23, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroshi Matsuyama
  • Patent number: 10937725
    Abstract: A semiconductor device comprises: a ceramic substrate having conductor layers on both surfaces thereof; a semiconductor element joined to the upper surface conductor layer of the ceramic substrate; a frame member arranged on the upper surface conductor layer so as to surround a side surface of the semiconductor element; and an electrode, which is joined to an upper portion of the semiconductor element via a second fixing layer, and has fitting portions on a side surface of the electrode. On an inner wall of the frame member, fitting portions to be fitted to the fitting portions of the electrode and four positioning portions extending from the inner wall of the frame member to the side surfaces of the electrode are formed.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: March 2, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuya Muramatsu, Noriyuki Besshi, Ryuichi Ishii
  • Patent number: 10935403
    Abstract: The present invention has been made to improve measurement accuracy of a thermal flow meter. In the thermal flow meter according to the invention, a circuit package (400) that measures a flow rate is molded in a first resin molding process. In a second resin molding process, a housing (302) having an inlet trench (351), a bypass passage trench on frontside (332), an outlet trench (353), and the like are formed through resin molding, and an outer circumferential surface of the circuit package (400) produced in the first resin molding process is enveloped by a resin in the second resin molding process to fix the circuit package (400) to the housing (302).
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 2, 2021
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Noboru Tokuyasu, Shinobu Tashiro, Keiji Hanzawa, Takeshi Morino, Ryosuke Doi, Akira Uenodan
  • Patent number: 10916429
    Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang
  • Patent number: 10916487
    Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bradley R. Bitz, Xiao Li, Jaspreet S. Gandhi
  • Patent number: 10910347
    Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Yong She, John G. Meyers, Zhicheng Ding, Richard Patten
  • Patent number: 10903146
    Abstract: [Problem] To provide an electrode connection structure and the like in which a plurality of elongated leads are arranged in parallel and a longitudinal side surface of each lead is connected to an electrode by plating treatment with high quality. [Solution] An electrode connection structure in which a semiconductor chip 12 electrode and/or a substrate electrode is connected to a plurality of elongated leads 11 of a lead frame 10 by plating. The plurality of elongated leads 11 of the lead frame 10 are arranged in parallel, and a longitudinal side surface of each lead 11 is connected to the semiconductor chip 12 electrode and/or the substrate electrode by plating.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 26, 2021
    Assignees: WASEDA UNIVERSITY, MITSUI HIGH-TEC, INC.
    Inventors: Kohei Tatsumi, Kazutoshi Ueda, Nobuaki Sato, Koji Shimizu
  • Patent number: 10892246
    Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 12, 2021
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10879162
    Abstract: An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.
    Type: Grant
    Filed: July 7, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung, Po-Yao Chuang
  • Patent number: 10879166
    Abstract: A semiconductor package including a substrate and a redistribution structure is provided. The substrate has at least one contact. The redistribution structure is disposed on the substrate and electrically connected to the at least one contact. The redistribution structure includes a plurality of redistribution layers, and each of the redistribution layers includes a conductive material layer, a first dielectric material layer and a second dielectric material layer. The conductive material layer has via portions and body portions located on the via portions. The first dielectric material layer is surrounding the via portions of the conductive material layer. The second dielectric material layer is disposed on the first dielectric material layer and surrounding the body portions of the conductive material layer, wherein a material of the second dielectric material layer is different than a material of the first dielectric material layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Hung-Jui Kuo, Ming-Tan Lee
  • Patent number: 10879155
    Abstract: A packaged electronic device includes a package structure that encloses first and second semiconductor dies, a die attach pad with a first side attached to one of the dies, and a second side exposed along a side of the package structure, and a substrate that includes a first metal layer exposed along another side of the package structure, a second metal layer soldered to contacts of the dies, and an isolator layer that extends between and separates the first and second metal layers.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Anindya Poddar, Vivek Kishorechand Arora
  • Patent number: 10867932
    Abstract: Package structures and methods for forming the same are provided. The method includes forming a redistribution structure embedded in a passivation layer over a carrier substrate and bonding an integrated circuit die to the redistribution structure through first connectors. The method further includes removing the carrier substrate to expose a bottom portion of the redistribution structure and removing the bottom portion of the redistribution structure to form an opening in the passivation layer. The method further includes forming a second connector over the redistribution structure. In addition, the second connector includes an extending portion extending into the opening in the passivation layer.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 10865100
    Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a substrate over a micro-electro-mechanical system (MEMS) substrate. The substrate includes a semiconductor via. The method also includes forming a dielectric layer over a top surface of the substrate, and forming a polymer layer over the dielectric layer. The method further includes patterning the polymer layer to form an opening, and the semiconductor via is exposed by the opening. The method includes forming a conductive layer in the opening and over the polymer layer, and forming an under bump metallization (UBM) layer on the conductive layer. The method further includes forming an electrical connector over the UBM layer, wherein the electrical connector is electrically connected to the semiconductor via through the UBM layer.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Fung Chang, Lien-Yao Tsai, Len-Yi Leu
  • Patent number: 10868421
    Abstract: An on-chip multiple-stage electrical overstress (EOS) protection device is disclosed. The protection device includes a surge protector having a first clamping voltage and a first electrostatic discharge (ESD) protector having a second clamping voltage lower than the first clamping voltage. The surge protector is electrically connected to the first ESD protector in parallel. The surge protector and the first ESD protector are electrically connected between a receiving terminal and a voltage terminal, and the receiving terminal is electrically connected to an internal circuit. When an electrical overstress (EOS) signal including an electrostatic discharge (ESD) signal and a surge signal appears at the receiving terminal, the first ESD protector and the surge protector are triggered on in turn to clamp a voltage received by the internal circuit.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: December 15, 2020
    Assignee: Amazing Microelectronic Corp.
    Inventors: James Jeng-Jie Peng, Woei-Lin Wu, Ryan Hsin-Chin Jiang
  • Patent number: 10847473
    Abstract: A semiconductor package can include a substrate and a semiconductor chip on the substrate. A first molding portion can cover the semiconductor chip and can include a first sidewall and a second sidewall opposite each other. A second molding portion can extend on the substrate along the first sidewall and along the second sidewall, where the first molding portion can include a nonconductive material, and the second molding portion can include a conductive material.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Han Ko, Bo Ram Kang, Dong Kwan Kim
  • Patent number: 10847680
    Abstract: A light emitting device including a package body having a first cavity; an electrode having a first electrode and a second electrode in the package body; at least one light emitting chip on the first electrode; a resin material in the first cavity; and a lens on the package body and the at least one light emitting chip. Further, the first electrode and the second electrode are separated by the package body, the package body comprises a first stepped portion exposed between the first electrode and the second electrode, the first electrode comprises a second cavity, and the at least one light emitting chip is disposed on the second cavity of the first electrode.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: November 24, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jun Seok Park, Wan Ho Kim
  • Patent number: 10832986
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole and including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a second connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the semiconductor chip, and an encapsulant encapsulating the semiconductor chip and having a cavity disposed above the inactive surface of the semiconductor chip.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hyun Cho, Young Sik Hur, Yong Ho Baek
  • Patent number: 10833070
    Abstract: A fan-out semiconductor package module that is easily manufactured includes a first connection member including a wiring layer, a first passive component mounted on the first connection member, a first encapsulation portion encapsulating at least a portion of the first connection member and the first passive component, a semiconductor chip having an active surface with a connection pad disposed thereon and an inactive surface opposing the active surface and disposed in a first through-hole penetrating through the first connection member and the first encapsulation portion, a second encapsulation portion covering at least a portion of the semiconductor chip and encapsulating at least a portion of the first encapsulation portion and the first connection member, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad and the first passive component.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Chul Gong, Yong Ho Baek, Young Sik Hur, Joo Hwan Jung, Yoo Rim Cha
  • Patent number: 10834818
    Abstract: A wiring board includes: an insulator layer composed mainly of ceramic; a conductor extending through the insulator layer in a thickness direction thereof; and an electrode pad disposed on a first surface of the insulator layer and connected electrically with the conductor, wherein: the electrode pad includes through holes extending through the electrode pad in a thickness direction thereof; and each of the through holes is positioned to avoid overlapping with the conductor in the thickness direction of the insulator layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 10, 2020
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Takakuni Nasu, Kengo Tanimori, Yousuke Kondo, Masahiro Kamegai, Kouta Kimata, Junya Matsura, Fumio Shiraki, Guangzhu Jin
  • Patent number: 10804191
    Abstract: A printed wiring board includes a first build-up layer having first insulating layer, conductor layer and via conductor, a second build-up layer formed on the first build-up layer and having second insulating layer, conductor layer and via conductor, a third build-up layer formed on the second build-up layer and having third insulating layer, conductor layer and via conductor, and a fourth build-up layer formed on the third build-up layer and having fourth insulating layer, conductor layer and via conductor. The first insulating layer has a thickness that is larger than a thickness of the second insulating layer, the thickness of the second insulating layer is larger than a thickness of the third insulating layer, the thickness of the second insulating layer is larger than a thickness of the fourth insulating layer, and the thickness of the fourth insulating layer is larger than the thickness of the third insulating layer.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: October 13, 2020
    Assignee: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Yoji Sawada
  • Patent number: 10790257
    Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Juan Eduardo Dominguez, Hyoung Il Kim
  • Patent number: 10777498
    Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: September 15, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chiao-Ling Huang, Tai-Hung Lin
  • Patent number: 10756015
    Abstract: A semiconductor package including a package substrate, a semiconductor chip on a first surface of the package substrate, a connection substrate on the package substrate and spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the semiconductor chip and the package substrate and electrically connecting the semiconductor chip to the package substrate, a plurality of second connecting elements between the connection substrate and the package substrate and electrically connecting the connection substrate to package substrate, a mold layer encapsulating the semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the semiconductor chip and electrically connected to a corresponding one of the plurality of conductive connection structures may be provided.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokhyun Lee, Kyung Suk Oh
  • Patent number: 10748830
    Abstract: A wiring board (2) is provided on a heat radiation plate (1). A semiconductor chip (8) is provided on the wiring board (2). A case housing (10) is provided on the heat radiation plate (1) and surrounds the wiring board (2) and the semiconductor chip (8). Adhesive agent (11) bonds a lower surface of the case housing (10) and an upper surface peripheral portion of the heat radiation plate (1). A sealing material (13) is filled in the case housing (10) and covers the wiring board (2) and the semiconductor chip (8). A step portion (16,17) is provided to at least one of the lower surface of the case housing (10) and the upper surface peripheral portion of the heat radiation plate (1). A side surface of the heat radiation plate (1) and an outer side surface of the case housing (10) are flush with each other.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: August 18, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukimasa Hayashida, Daisuke Oya, Takayuki Matsumoto, Ryutaro Date
  • Patent number: 10734300
    Abstract: A semiconductor device according to the present invention includes the following: a conductive layer disposed on an insulating substrate; a first semiconductor element and a second semiconductor element that are joined on an opposite surface of the conductive layer opposite from the insulating substrate, with a gap the first semiconductor element and the second semiconductor element; an electrode joined on an opposite surface of the first semiconductor element opposite from the conductive layer, and an opposite surface of the second semiconductor element opposite from the conductive layer, so as to extend over the gap; and resin sealing the conductive layer, the first semiconductor element, the second semiconductor element, and the electrode. The conductive layer has a recess pattern that is disposed on a surface being opposite from the insulating substrate and facing the gap, the recess pattern extending along the gap.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: August 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mitsugu Tanaka, Yusuke Ishiyama, Akitoshi Shirao
  • Patent number: 10720340
    Abstract: The invention relates to a mould for encapsulating electronic components mounted on a carrier, with at least two mould parts which are displaceable relative to each other for engaging with a mould cavity round electronic components, and at least one feed for encapsulating material recessed into the mould parts and connecting to the mould cavity. The invention also relates to a carrier with encapsulated electronic components. The invention further relates to a method for encapsulating electronic components and to the thus manufactured encapsulated separated components.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 21, 2020
    Assignee: Besi Netherlands B.V.
    Inventor: Michel Hendrikus Lambertus Teunissen