With Particular Lead Geometry Patents (Class 257/692)
  • Patent number: 11990381
    Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
  • Patent number: 11990373
    Abstract: A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: May 21, 2024
    Assignee: SOCIONEXT INC.
    Inventor: Toyoji Sawada
  • Patent number: 11978980
    Abstract: An electrical feedback barrier is configured to safely interconnect an intrinsically safe power supply to a non-intrinsically safe electrical load device in a hazardous environment. Electrical feedback from the non-intrinsically electrical load device is blocked by the electrical feedback barrier to protect the intrinsically safe power supply from adverse operating conditions. The electrical feedback barrier and the electrical load device are enclosed in an explosion-proof or flameproof enclosure for compliance with electrical equipment safety standards in the hazardous environment.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: May 7, 2024
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventor: Paul R. York
  • Patent number: 11973052
    Abstract: An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: April 30, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chien-Chang Li, Hung-Yu Chou, Sheng-Wen Huang, Zi-Xian Zhan, Byron Lovell Williams
  • Patent number: 11967899
    Abstract: A compact inverter system includes a bus bar. The bus bar includes a terminal for connection to a positive terminal of a DC voltage supply. The compact inverter also includes a heat sink, a first transistor, and a second transistor. The first transistor has first and second terminals between which current is transmitted when the first transistor is activated, and a first gate terminal controlling the first transistor. The first terminal of the first transistor is thermally and electrically connected to the bus bar. The second transistor has first and second terminals between which current is transmitted when the second transistor is activated, and a second gate terminal controlling the second transistor. The first terminal of the second transistor is thermally and electrically connected to the heat sink. The first and second transistors are positioned between the bus bar and the heat sink. The first transistor is positioned between the second transistor and the bus bar.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: April 23, 2024
    Inventor: Jean-Claude Harel
  • Patent number: 11955405
    Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen Yu Wang, Chung-Jung Wu, Sheng-Tsung Hsiao, Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 11930586
    Abstract: A wiring substrate includes: an insulating substrate including a base portion comprising a through hole having a first opening and a second opening, and a frame portion located on the base portion; and a heat dissipator disposed on a side of the base portion that is opposite to the frame portion so as to block the second opening, wherein an inner surface of the through hole faces a side surface of the heat dissipator with a clearance being provided between the inner surface of the through hole and the side surface of the heat dissipator.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: March 12, 2024
    Assignee: KYOCERA Corporation
    Inventor: Toshiyuki Hamachi
  • Patent number: 11916064
    Abstract: An integrated circuit with a fault reporting structure. The integrated circuit has at least one power MOSFET having a plurality of MOSFET cells with each MOSFET cell having a drain metal and a source metal, and the integrated circuit has a power MOSFET area for routing the drain metals and the source metals of the plurality of MOSFET cells. The fault reporting structure has a metal net routed in the power MOSFET area or in an area above or below the power MOSFET area.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: February 27, 2024
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Chiahsin Chang, Tao Zhao, Xintong Lyu
  • Patent number: 11908767
    Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 20, 2024
    Assignee: MEDIATEK INC.
    Inventors: Che-Hung Kuo, Hsing-Chih Liu, Chia-Hao Hsu
  • Patent number: 11908793
    Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Jiun Hann Sir, Poh Boon Khoo, Eng Huat Goh, Amruthavalli Pallavi Alur, Debendra Mallik
  • Patent number: 11894281
    Abstract: A semiconductor device includes a semiconductor element, a first lead electrically connected to the semiconductor element, a sealing resin that covers the semiconductor element and a part of the first lead, and a recess formed in a surface flush with a back surface of the sealing resin. The sealing resin also has a front surface opposite to the back surface in a thickness direction, and a side surface connecting the front surface and the back surface to each other. The recess is formed, in part, by a part of the first lead that is exposed from the back surface of the sealing resin. The recess has an outer edge that forms a closed shape, as viewed in the thickness direction, within a region that includes the back surface of the sealing resin and the first lead.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 6, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Ryota Majima, Koshun Saito
  • Patent number: 11848255
    Abstract: Disclosed are semiconductor package structure and semiconductor modules including the same. The semiconductor module includes a circuit board, a first semiconductor package over the circuit board, and a connection structure on the circuit board and connecting the circuit board and the first semiconductor package. The first semiconductor package includes a first package substrate. A difference in coefficient of thermal expansion between the connection structure and the circuit board may be less than a difference in coefficient of thermal expansion between the circuit board and the first package substrate.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: YoungJoon Lee, Sunwon Kang
  • Patent number: 11830859
    Abstract: A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and an electronic component disposed on the substrate, and the first package component is mounted to the substrate. The package structure further includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot, the first foot and the second foot extend toward the substrate, the electronic component is covered by the ring structure and located between the first foot and the second foot, and the first package component is exposed from the ring structure.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11824012
    Abstract: An integrated circuit (IC) package structure includes a chip, a redistribution layer (RDL) structure, a molding compound structure and an electromagnetic interference (EMI) shielding structure. The RDL structure is formed on the chip and electrically connected thereto. The molding compound layer is provided on outer surfaces of the chip and the RDL structure. The EMI shielding structure is provided on outer surfaces of the molding compound structure. The molding compound structure layer provided on outer surfaces of the chip and the RDL structure provide protection and reinforcement to multiple faces of the IC package structure; and the EMI shielding structure provided on outer surfaces of the molding compound structure provides EMI protection to multiple faces of the chip and the RDL structure. The IC package structure has upgraded structural strength, reliability and stability in use. A method of manufacturing the above IC package structure is also introduced.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: November 21, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chia-Yu Peng, John Hon-Shing Lau
  • Patent number: 11817536
    Abstract: A method for making light emitting device LED arrays includes the steps of providing a plurality of LEDs having a desired configuration (e.g., VLED, FCLED, PLED); attaching the LEDs to a carrier substrate and to a temporary substrate; forming one or more metal layers and one or more insulator layers configured to electrically connect the LEDs to form a desired circuitry; and separating the LEDs along with the layered metal layers and insulator layers that form the desired circuitry from the carrier substrate and the temporary substrate.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: November 14, 2023
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: David Trung Doan, Trung Tri Doan
  • Patent number: 11810887
    Abstract: A power module includes a first substrate including a first metal plate, a second substrate spaced apart from the first substrate and having a second metal facing the first substrate, a plurality of power elements that are disposed between the first substrate and the second substrate and include a first electrode and a second electrode. The plurality of power elements include a first power element having the first electrode bonded to the second metal plate, and a second power element having the first electrode bonded to the first metal plate.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 7, 2023
    Assignee: LG Electronics Inc.
    Inventors: Heoncheol Oh, Jaesang Min, Yonghee Park, Jinwoo Lee, Heejin Cho
  • Patent number: 11791727
    Abstract: A half-bridge module having two switching units, each of which includes multiple transistors connected in parallel and/or in series, in particular IGBTs or MOSFETs. The transistors are arranged on a first substrate. The half-bridge module has a temperature sensor matrix having a plurality of temperature sensors, and the temperature sensors are thermally connected to the transistors at least in some regions. A temperature sensor matrix is also provided.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: October 17, 2023
    Assignee: AUDI AG
    Inventor: Daniel Ruppert
  • Patent number: 11756932
    Abstract: A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: September 12, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xianlu Cui, Junrong Yan, Cheekeong Chin, Zhonghua Qian
  • Patent number: 11749666
    Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Bradley R. Bitz, Xiao Li
  • Patent number: 11742293
    Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 29, 2023
    Assignee: Intel Corporation
    Inventors: Yidnekachew S. Mekonnen, Kemel Aygun, Ravindranath V. Mahajan, Christopher S. Baldwin, Rajasekaran Swaminathan
  • Patent number: 11721641
    Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: August 8, 2023
    Assignee: Google LLC
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Emad Samadiani, Yuan Li
  • Patent number: 11682603
    Abstract: An electronic system includes a plurality of heat sources. At least two of the plurality of heat sources vary in height and each of the plurality of heat sources includes a first side and a second side. The electronic system also includes a substrate having a first side and a second side. The second side of each of the plurality of heat sources is positioned adjacent to the first side of the substrate. The electronic system further includes a cover member provided above the plurality of heat sources and a sintering thermal interface material provided between the cover member and the first side of one of the at least two heat sources that vary in height.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: June 20, 2023
    Assignee: Flex Ltd.
    Inventors: Cheng Yang, Dongkai Shangguan
  • Patent number: 11682610
    Abstract: A semiconductor package includes a terminal pad having at least one first terminal lead structurally connected to the terminal pad, a semiconductor chip attached to an upper surface of the terminal pad by using a first adhesive, a heat radiation board attached to a lower surface of the terminal pad by using a second adhesive, and at least one second terminal lead electrically connected to the semiconductor chip. The second terminal lead is spaced apart from the terminal pad and is separated from the radiation board. The package further includes a metal clip electrically connecting the semiconductor chip to the second terminal lead, and a package housing covering parts of the first terminal lead, the second terminal lead, and the terminal pad. The package housing includes an adhesive spread space to expose the lower surface of the terminal pad.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: June 20, 2023
    Assignee: JMJ Korea Co., Ltd.
    Inventors: Yun Hwa Choi, Younghun Kim, Jeonghun Cho
  • Patent number: 11670563
    Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: June 6, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: KyungOe Kim, Wagno Alves Braganca, Jr., DongSam Park
  • Patent number: 11662870
    Abstract: A display device includes a touch panel including touch and pad areas, and a touch printed circuit board including a contact portion in the pad area. The touch panel includes a touch signal line in the pad area, and the touch printed circuit board includes a touch lead signal line in the contact portion and connected to the touch signal line through an anisotropic conductive film. The touch lead signal line includes a first portion having a first width, a second portion having a second width smaller than the first width and a third portion between the first and second portions and having a third width between the first and second widths. An end of the touch signal line is on the first and third portions, and the third portion has a side profile having two or more different slopes.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: May 30, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sang Won Jeong, Tae Young Koo, Min Chul Song, In Young Yoon
  • Patent number: 11664329
    Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: May 30, 2023
    Assignee: Google LLC
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Emad Samadiani, Yuan Li
  • Patent number: 11658100
    Abstract: A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 23, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Katsuhiro Iwai
  • Patent number: 11652019
    Abstract: A heat dissipation structure includes a heat dissipation portion and a heat storage portion. The heat dissipation portion has the heat receiving surface including the contact surface in contact with the semiconductor generating the heat, and dissipates the heat of the semiconductor in contact with the contact surface. The heat storage portion is arranged to sandwich the semiconductor. The heat storage portion has, for example, the heat storage opening portion in which the semiconductor is positioned, and surrounds the semiconductor. The heat storage portion is provided to he in contact with the heat receiving surface, and stores the heat of the semiconductor conducted through the heat dissipation portion.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: May 16, 2023
    Assignee: YAZAKI CORPORATION
    Inventors: Mitsuaki Morimoto, Kazuo Sugimura, Kazuya Tsubaki, Eiichiro Oishi
  • Patent number: 11642695
    Abstract: An ultrasonic probe includes a semiconductor chip in which an ultrasonic transducer is formed and an electrode pad electrically connected to an upper electrode or a lower electrode of the ultrasonic transducer is provided and a flexible substrate in which a bump electrically connected to the electrode pad is provided and the bump is disposed in a portion overlapping with a stepped portion of the semiconductor chip. Further, a height of a connection surface of the electrode pad of the semiconductor chip connected to the bump is lower than a height of a lower surface of the lower electrode.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 9, 2023
    Assignee: FUJIFILM HEALTHCARE CORPORATION
    Inventors: Shuntaro Machida, Akifumi Sako, Yasuhiro Yoshimura
  • Patent number: 11637097
    Abstract: A method of manufacturing a package structure includes: forming a backside RDL structure on a carrier; forming TIVs on the backside RDL structure; mounting at least one passive device on the backside RDL structure, so that the at least one passive device is disposed between the TIVs; placing a die on the at least one passive device, so that the at least one passive device is vertically sandwiched between the die and the backside RDL structure; forming an encapsulant laterally encapsulating the die, the TIVs, and the at least one passive device; forming a front side RDL structure on a front side of the die, the TIVs, and the encapsulant; releasing the backside RDL structure from the carrier; and mounting a package on the backside RDL structure, wherein the package is electrically connected to the at least one passive device by conductive connectors and solders.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 11621219
    Abstract: An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: April 4, 2023
    Assignee: Rockwell Collins, Inc.
    Inventors: Reginald D. Bean, Bret W. Simon
  • Patent number: 11611009
    Abstract: According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: March 21, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Masahiko Hori, Tatsuo Tonedachi, Yoshinari Tamura, Mami Fujihara
  • Patent number: 11600610
    Abstract: The present invention relates to a semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: March 7, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Yaobin Guan, Jianjian Sheng
  • Patent number: 11594508
    Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu, Kai-Di Wu, Su-Fei Lin
  • Patent number: 11587885
    Abstract: The present disclosure provides a method for fabricating a semiconductor device including providing a first semiconductor die, forming a connection dielectric layer above the first semiconductor die, forming a first bottom protection layer in the connection dielectric layer, forming a first conductive plate on the first bottom protection layer, and forming a first top protection layer on the first conductive plate. The first bottom protection layer and the first top protection layer are formed of manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, strontium ferrite, barium ferrite, lithium ferrite, lithium-zinc ferrite, single crystal yttrium iron garnet, or gallium substituted single crystal yttrium iron garnet.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: February 21, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Te Kuo
  • Patent number: 11587923
    Abstract: Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 21, 2023
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventor: Po-Chuan Lin
  • Patent number: 11569141
    Abstract: A semiconductor device includes a first electrode; a second electrode; a resin case surrounding the first electrode and the second electrode; and a resin insulating part made of a material the same as a material of the resin case and covering part of the first electrode and part of the second electrode inside the resin case. The resin insulating part contacts an inner wall of the resin case or is separated from the inner wall of the resin case. A move positioned between the first electrode and the second electrode is formed at the resin insulating part, and thus a space in which the resin insulating part does not exist or a material different from the resin insulating part is provided between the first electrode and the second electrode.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 31, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Oya, Yukimasa Hayashida, Tetsuo Motomiya
  • Patent number: 11532539
    Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: December 20, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hui Min Ler, Soon Wei Wang, Chee Hiong Chew
  • Patent number: 11479461
    Abstract: A production method for a micromechanical device having inclined optical windows. First and second substrates are provided. A plurality of through-holes is produced in the first and second substrate such that for each through-hole in the first substrate a congruent through-hole is produced in the second substrate, which overlap when the first substrate is placed over the second substrate. A slanted edge region is produced around a respective through-hole in the first and second substrate, the edge region being inclined at a window angle, two slanted edge regions situated on top of each other being congruent in a top view and being inclined at the same window angle. A window foil is provided having a structured window region, which covers the through-hole in a top view of the window foil in each case, the window foil forming an optical window slanted at the window angle above the respective through-hole.
    Type: Grant
    Filed: May 11, 2019
    Date of Patent: October 25, 2022
    Assignee: Robert Bosch GmbH
    Inventor: Stefan Pinter
  • Patent number: 11475752
    Abstract: A vehicle and a network system are provided to operate the air conditioning apparatus of the vehicle when a passenger within the vehicle is left unattended. The vehicle transmits a signal via a vehicle network to rescue the rear passenger, thereby ensuring passenger safety. The vehicle includes an output device and a communicator configured to communicate with a user terminal, an air conditioner, a sensor. The sensor obtains a movement of the passenger and a controller outputs an identification image through the output device when a movement signal of the passenger exceeds a reference signal after the vehicle doors are closed.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 18, 2022
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Dae Young Kim
  • Patent number: 11469486
    Abstract: A microwave or radio frequency (RF) device includes an insulating substrate having a first surface and a second surface opposing the first surface. The device also includes a crossover conductor disposed on the first surface extending between a first edge of the first surface and a second edge of the first surface. The device also includes a depression in the second surface defined at least in part by (i) a third surface recessed in relation to the second surface, and (ii) at least one sidewall that extends between the second surface and the third surface. The device further includes a conductive coating formed over at least a portion of the second surface, the third surface, and the at least one sidewall, where the conductive coating is insulated from the crossover conductor by the insulating substrate.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: October 11, 2022
    Assignee: KNOWLES CAZENOVIA, INC.
    Inventor: Pierre Nadeau
  • Patent number: 11462617
    Abstract: A power semiconductor is provided. The power semiconductor includes a gate, a source, a silicon chip and a drain. The source includes a first copper particle layer and a first metal layer. The first copper particle layer covers the upper surface of the first metal layer. The silicon chip is bonded to the lower surface of the first metal layer. The drain is bonded to the lower surface of the silicon chip. The thickness of the first copper particle layer is greater than the thickness of the first metal layer. All copper mentioned are of large grain copper with size greater than 0.25 um.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: October 4, 2022
    Inventors: Tso-Tung Ko, Brian Cinray Ko, Kuang-Ming Liao, Chen-Yu Liao
  • Patent number: 11450619
    Abstract: An embedded package structure having a shielding cavity according to an embodiment of the present disclosure includes a device embedded in an insulating layer, and a shielding cavity enclosing the device, wherein the shielding cavity is defined by a shielding wall embedded in the insulating layer and surrounding the device on four sides, and first and second wiring layers which cover first and second end faces of the shielding wall and are electrically connected with the shielding wall; wherein a signal line leading-out opening is to formed between the first end face of the shielding wall and the first wiring layer, and a signal line connected with a terminal of the device is led, from the signal line leading-out opening, out of the shielding cavity.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 20, 2022
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd
    Inventors: Xianming Chen, Min Gu, Lei Feng, Lina Jiang, Benxia Huang, Wenshi Wang
  • Patent number: 11444054
    Abstract: Provided is a semiconductor element mounting structure, including: a semiconductor element including an element electrode, and a substrate including a substrate electrode that is provided on a surface facing the semiconductor element at a position facing the element electrode, the semiconductor element and the substrate being connected via the element electrode and the substrate electrode, in which: one of the element electrode or the substrate electrode is a first protruding electrode including a solder layer at a tip portion thereof, the other of the element electrode or the substrate electrode is a first electrode pad including one or more metal protrusions on a surface thereof, the one or more metal protrusions of the first electrode pad extend into the solder layer of the first protruding electrode, and a bottom area of each of the one or more metal protrusions of the first electrode pad is 70% or less with respect to an area of the first electrode pad, or 75% or less with respect to a maximum cross-sect
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 13, 2022
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Hitoshi Onozeki, Shizu Fukuzumi, Naoya Suzuki, Toshihisa Nonaka
  • Patent number: 11431146
    Abstract: A chip on submodule includes a submount having a top surface, bottom surface and side surfaces. A positive electrode plate is affixed to a first portion of one side surface, the top surface and a first portion of the bottom surface. The positive electrode plated first portion of the one side surface and the top surface are interconnected. A connector electrically connects the positive electrode plated top surface to the first portion of the bottom surface. A negative electrode plate is affixed to a second portion of the one side surface and a second portion of the bottom surface. The negative electrode plated second portion of the one side surface and second portion of the bottom surface are interconnected. A laser diode is affixed to the positive electrode plated first portion of the one side surface and connected to the negative electrode plated second portion of the one side surface.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: August 30, 2022
    Assignee: Jabil Inc.
    Inventors: Lorito E. Victoria, Lars Runge
  • Patent number: 11421861
    Abstract: A light source module includes a light-emitting device having an upper surface and a lower surface and including: at least one light-emitting element and a plurality of conductive regions on the upper surface of the light-emitting device; a mounting substrate having an upper surface on which a lower surface side of the light-emitting device is located, the mounting substrate including conductive patterns on the upper surface of the mounting substrate, each conductive pattern including a device-side connecting portion and an external side connecting portion; and a plurality of conductive members each having a first end bonded to a respective one of the device-side connecting portion and a second end opposite to the first end, the second end being in contact with a respective one of the conductive region by elasticity to electrically connect the respective one of the conductive regions and a respective one of the conductive patterns.
    Type: Grant
    Filed: May 24, 2020
    Date of Patent: August 23, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Tomohiko Hatano
  • Patent number: 11417638
    Abstract: A semiconductor structure includes a semiconductor package and a connector. The semiconductor package includes a die and a redistribution structure. The redistribution structure is disposed over the die, and includes a plurality of conductive patterns stacking on one another and electrically connected to the die. The connector is disposed on the redistribution structure, and includes a connecting element. The connecting element penetrates the conductive patterns and is electrically connected to the die.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
  • Patent number: 11404363
    Abstract: A connection terminal unit that can be appropriately connected to terminal connection portions of a semiconductor module including a semiconductor element and that can reduce a projection area when seen in a direction orthogonal to a direction along a chip surface is realized. Connection terminal unit includes plurality of connection terminals facing and connected to plurality of terminal connection portions of semiconductor module, and terminal mold portion holding connection terminals. Terminal mold portion has abutment portion that abuts against semiconductor module or base material holding semiconductor module. Abutment portion has vertical abutment portion that abuts against semiconductor module or base material from vertical direction that is a direction in which connection terminals face terminal connection portions, and side abutment portion that abuts against semiconductor module or base material from at least two directions that are different from each other and intersect with vertical direction.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: August 2, 2022
    Assignee: AISIN CORPORATION
    Inventors: Yutaka Hotta, Shinya Osuka, Yasuhiro Kume
  • Patent number: 11348875
    Abstract: Semiconductor devices having an array of flexible connectors configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector can include a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire can have a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 31, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Koustav Sinha, Xiaopeng Qu
  • Patent number: 11342306
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee