With Particular Lead Geometry Patents (Class 257/692)
  • Patent number: 11569141
    Abstract: A semiconductor device includes a first electrode; a second electrode; a resin case surrounding the first electrode and the second electrode; and a resin insulating part made of a material the same as a material of the resin case and covering part of the first electrode and part of the second electrode inside the resin case. The resin insulating part contacts an inner wall of the resin case or is separated from the inner wall of the resin case. A move positioned between the first electrode and the second electrode is formed at the resin insulating part, and thus a space in which the resin insulating part does not exist or a material different from the resin insulating part is provided between the first electrode and the second electrode.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 31, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Oya, Yukimasa Hayashida, Tetsuo Motomiya
  • Patent number: 11532539
    Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: December 20, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hui Min Ler, Soon Wei Wang, Chee Hiong Chew
  • Patent number: 11479461
    Abstract: A production method for a micromechanical device having inclined optical windows. First and second substrates are provided. A plurality of through-holes is produced in the first and second substrate such that for each through-hole in the first substrate a congruent through-hole is produced in the second substrate, which overlap when the first substrate is placed over the second substrate. A slanted edge region is produced around a respective through-hole in the first and second substrate, the edge region being inclined at a window angle, two slanted edge regions situated on top of each other being congruent in a top view and being inclined at the same window angle. A window foil is provided having a structured window region, which covers the through-hole in a top view of the window foil in each case, the window foil forming an optical window slanted at the window angle above the respective through-hole.
    Type: Grant
    Filed: May 11, 2019
    Date of Patent: October 25, 2022
    Assignee: Robert Bosch GmbH
    Inventor: Stefan Pinter
  • Patent number: 11475752
    Abstract: A vehicle and a network system are provided to operate the air conditioning apparatus of the vehicle when a passenger within the vehicle is left unattended. The vehicle transmits a signal via a vehicle network to rescue the rear passenger, thereby ensuring passenger safety. The vehicle includes an output device and a communicator configured to communicate with a user terminal, an air conditioner, a sensor. The sensor obtains a movement of the passenger and a controller outputs an identification image through the output device when a movement signal of the passenger exceeds a reference signal after the vehicle doors are closed.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 18, 2022
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Dae Young Kim
  • Patent number: 11469486
    Abstract: A microwave or radio frequency (RF) device includes an insulating substrate having a first surface and a second surface opposing the first surface. The device also includes a crossover conductor disposed on the first surface extending between a first edge of the first surface and a second edge of the first surface. The device also includes a depression in the second surface defined at least in part by (i) a third surface recessed in relation to the second surface, and (ii) at least one sidewall that extends between the second surface and the third surface. The device further includes a conductive coating formed over at least a portion of the second surface, the third surface, and the at least one sidewall, where the conductive coating is insulated from the crossover conductor by the insulating substrate.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: October 11, 2022
    Assignee: KNOWLES CAZENOVIA, INC.
    Inventor: Pierre Nadeau
  • Patent number: 11462617
    Abstract: A power semiconductor is provided. The power semiconductor includes a gate, a source, a silicon chip and a drain. The source includes a first copper particle layer and a first metal layer. The first copper particle layer covers the upper surface of the first metal layer. The silicon chip is bonded to the lower surface of the first metal layer. The drain is bonded to the lower surface of the silicon chip. The thickness of the first copper particle layer is greater than the thickness of the first metal layer. All copper mentioned are of large grain copper with size greater than 0.25 um.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: October 4, 2022
    Inventors: Tso-Tung Ko, Brian Cinray Ko, Kuang-Ming Liao, Chen-Yu Liao
  • Patent number: 11450619
    Abstract: An embedded package structure having a shielding cavity according to an embodiment of the present disclosure includes a device embedded in an insulating layer, and a shielding cavity enclosing the device, wherein the shielding cavity is defined by a shielding wall embedded in the insulating layer and surrounding the device on four sides, and first and second wiring layers which cover first and second end faces of the shielding wall and are electrically connected with the shielding wall; wherein a signal line leading-out opening is to formed between the first end face of the shielding wall and the first wiring layer, and a signal line connected with a terminal of the device is led, from the signal line leading-out opening, out of the shielding cavity.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 20, 2022
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd
    Inventors: Xianming Chen, Min Gu, Lei Feng, Lina Jiang, Benxia Huang, Wenshi Wang
  • Patent number: 11444054
    Abstract: Provided is a semiconductor element mounting structure, including: a semiconductor element including an element electrode, and a substrate including a substrate electrode that is provided on a surface facing the semiconductor element at a position facing the element electrode, the semiconductor element and the substrate being connected via the element electrode and the substrate electrode, in which: one of the element electrode or the substrate electrode is a first protruding electrode including a solder layer at a tip portion thereof, the other of the element electrode or the substrate electrode is a first electrode pad including one or more metal protrusions on a surface thereof, the one or more metal protrusions of the first electrode pad extend into the solder layer of the first protruding electrode, and a bottom area of each of the one or more metal protrusions of the first electrode pad is 70% or less with respect to an area of the first electrode pad, or 75% or less with respect to a maximum cross-sect
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 13, 2022
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Hitoshi Onozeki, Shizu Fukuzumi, Naoya Suzuki, Toshihisa Nonaka
  • Patent number: 11431146
    Abstract: A chip on submodule includes a submount having a top surface, bottom surface and side surfaces. A positive electrode plate is affixed to a first portion of one side surface, the top surface and a first portion of the bottom surface. The positive electrode plated first portion of the one side surface and the top surface are interconnected. A connector electrically connects the positive electrode plated top surface to the first portion of the bottom surface. A negative electrode plate is affixed to a second portion of the one side surface and a second portion of the bottom surface. The negative electrode plated second portion of the one side surface and second portion of the bottom surface are interconnected. A laser diode is affixed to the positive electrode plated first portion of the one side surface and connected to the negative electrode plated second portion of the one side surface.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: August 30, 2022
    Assignee: Jabil Inc.
    Inventors: Lorito E. Victoria, Lars Runge
  • Patent number: 11421861
    Abstract: A light source module includes a light-emitting device having an upper surface and a lower surface and including: at least one light-emitting element and a plurality of conductive regions on the upper surface of the light-emitting device; a mounting substrate having an upper surface on which a lower surface side of the light-emitting device is located, the mounting substrate including conductive patterns on the upper surface of the mounting substrate, each conductive pattern including a device-side connecting portion and an external side connecting portion; and a plurality of conductive members each having a first end bonded to a respective one of the device-side connecting portion and a second end opposite to the first end, the second end being in contact with a respective one of the conductive region by elasticity to electrically connect the respective one of the conductive regions and a respective one of the conductive patterns.
    Type: Grant
    Filed: May 24, 2020
    Date of Patent: August 23, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Tomohiko Hatano
  • Patent number: 11417638
    Abstract: A semiconductor structure includes a semiconductor package and a connector. The semiconductor package includes a die and a redistribution structure. The redistribution structure is disposed over the die, and includes a plurality of conductive patterns stacking on one another and electrically connected to the die. The connector is disposed on the redistribution structure, and includes a connecting element. The connecting element penetrates the conductive patterns and is electrically connected to the die.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
  • Patent number: 11404363
    Abstract: A connection terminal unit that can be appropriately connected to terminal connection portions of a semiconductor module including a semiconductor element and that can reduce a projection area when seen in a direction orthogonal to a direction along a chip surface is realized. Connection terminal unit includes plurality of connection terminals facing and connected to plurality of terminal connection portions of semiconductor module, and terminal mold portion holding connection terminals. Terminal mold portion has abutment portion that abuts against semiconductor module or base material holding semiconductor module. Abutment portion has vertical abutment portion that abuts against semiconductor module or base material from vertical direction that is a direction in which connection terminals face terminal connection portions, and side abutment portion that abuts against semiconductor module or base material from at least two directions that are different from each other and intersect with vertical direction.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: August 2, 2022
    Assignee: AISIN CORPORATION
    Inventors: Yutaka Hotta, Shinya Osuka, Yasuhiro Kume
  • Patent number: 11348875
    Abstract: Semiconductor devices having an array of flexible connectors configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector can include a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire can have a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 31, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Koustav Sinha, Xiaopeng Qu
  • Patent number: 11342306
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 11315847
    Abstract: The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package comprises: a semiconductor die, comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: April 26, 2022
    Assignee: Nexperia B.V.
    Inventors: Wolfgang Schnitt, Tobias Sprogies
  • Patent number: 11309301
    Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Raghuveer S. Makala, Rahul Sharangpani, Adarsh Rajashekhar
  • Patent number: 11302644
    Abstract: A package structure includes a substrate, a first electronic component, a second electronic component, a third electronic component and a connection component. The substrate includes a first surface and a second surface opposite the first surface. The first electronic component is disposed at the substrate and has a first active surface exposed from the second surface of the substrate. The second electronic component includes a second active surface facing the first active surface of the first electronic component. The second active surface of the second electronic component is electrically connected to the first active surface of the first electronic component. The third electronic component includes a third active surface facing the first active face of the first electronic component. The connection component electrically connects the third active surface of the third electronic component to the first active surface of the first electronic component. The connection component has at least two bendings.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11270920
    Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: March 8, 2022
    Assignee: Medtronic, Inc.
    Inventors: Chunho Kim, Mark E. Henschel
  • Patent number: 11257776
    Abstract: A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Sheng Lin, Chin-Li Kao, Hsu-Nan Fang
  • Patent number: 11239192
    Abstract: Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 1, 2022
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Glenn Rinne, Daniel Richter
  • Patent number: 11232992
    Abstract: A power device package structure including a first substrate, a second substrate, at least one power device, and a package is provided. A heat conductivity of the first substrate is greater than 200 Wm?1K?1. The power device is disposed on the first substrate, and the second substrate is disposed under the first substrate. A heat capacity of the second substrate is greater than that of the first substrate. The package encapsulates the first substrate, the second substrate, and the power device.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: January 25, 2022
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventors: Hsin-Chang Tsai, Ching-Wen Liu
  • Patent number: 11222883
    Abstract: Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a first passive device, a plurality of through insulator vias (TIVs), an encapsulant, and a plurality of conductive connectors. The die has a front side and a backside opposite to each other. The first passive device is disposed aside the die. The TIVs are disposed between the die and the first passive device. The encapsulant laterally encapsulates the TIVs, the first passive device, and the die. The conductive connectors are disposed on the backside of the die, wherein the conductive connectors are electrically connected to the die and the first passive device by a plurality of solders.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 11201173
    Abstract: Provided are an array substrate, a display panel and a display device. The array substrate includes a display region and a peripheral region. The peripheral region includes a chip-on-film bonding region, and the peripheral region has a recessed structure configured to fill a bonding material. The recessed structure is between the chip-on-film bonding region and a lateral side of the array substrate. The chip-on-film bonding region is between the display region and the lateral side. By disposing a recessed structure configured to fill the bonding material in the peripheral region, a gap is difficult to occur between the chip-on-film in the chip-on-film bonding region and the array substrate, preventing entry of water vapor to cause corrosion of lead wires and short circuits of lead wires. The defect ratio of the array substrate, the display panel, and the display device is reduced, and the product quality is improved.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: December 14, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mookeun Shin, Hui Dong, Haifeng Xu, Guangying Mou, Wei Zhang, Kaiwen Wang
  • Patent number: 11195817
    Abstract: A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Chih-Yuan Chang
  • Patent number: 11195269
    Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: December 7, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Reynaldo Corpuz Javier, Alok Kumar Lohia, Andy Quang Tran
  • Patent number: 11183453
    Abstract: A method of manufacturing an electronic-component-embedded substrate includes forming a power-supplying metal layer on a base, forming through electrodes that are to be connected to the power-supplying metal layer on the power-supplying metal layer by an electrolytic plating method, forming a first wiring line by patterning the power-supplying metal layer, forming an interlayer insulating layer such that the interlayer insulating layer covers a portion of the first wiring line, and forming a second wiring line on at least a portion of the first wiring line and a portion of the interlayer insulating layer such that the second wiring line crosses, on the interlayer insulating layer, a portion of the first wiring line.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: November 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Iwamoto
  • Patent number: 11174157
    Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Yu-Hsuan Tsai, Yin-Hao Chen, Hsin Lin Wu, San-Kuei Yu
  • Patent number: 11177235
    Abstract: The semiconductor device includes a solder ball connected to a pad, and located below the pad, a first wiring electrically connected to the pad, and located above the pad, and a second wiring electrically connected to the first wiring. At this time, a width of the first wiring is greater than a width of the second wiring. Accordingly, high-frequency noise can be reduced while improving signal transmission characteristics.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Oikawa
  • Patent number: 11171111
    Abstract: An integrated circuit device comprises: a resin film that is flexible; a plurality of traces bonded on a surface of the resin film and arrayed in a specific direction; an IC chip bonded on the surface of the resin film, located offset to the traces in a direction perpendicular to the specific direction, and connected to the traces; and a protection pattern formed on the surface of the resin film, located in the specific direction with respect to a disposition region in which the IC chip and/or the traces are disposed, and formed of the same material as that of the traces.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: November 9, 2021
    Assignee: Synaptics Incorporated
    Inventors: Kazuhiro Okamura, Takeshi Okubo, Yuichi Nakagomi, Takefumi Seno
  • Patent number: 11169940
    Abstract: A wireline communications system is described. The wireline communications system includes a printed circuit board (PCB). The wireline communications system also includes a system on chip (SoC) die on the PCB. The wireline communications system further includes an external memory device coupled to a memory interface of the SoC die. The external memory device is coupled to the memory interface of the SoC die through a PCB trace. A length of the PCB trace is configured according to an operating speed of the memory interface.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Sunil Gupta, Scott Powers
  • Patent number: 11131689
    Abstract: Embodiments herein describe structures of low-force wafer test probes and formation thereof. Structures of low-force wafer test probes and their formation via gray scale etch or electroplating is described. Structures are described that include a lower base structure on top of a substrate and an upper blade structure on top of the lower base structure. In various embodiments, a crown of a C4 bump is accommodated by one or both of: i) a cavity present in the lower base structure; and ii) a height of the upper blade structure. Processes for fabricating probe structures are described that include forming lower base structures upon a substrate and forming upper blade structures on top of the lower base structures. The upper blade structures include at least one blade. Each of the blade(s) include a cutting edge that points toward a center point within the probe structure.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: David M. Audette, S J. Chey, Doreen D. DiMilia, Sankeerth Rajalingam, Grant Wagner
  • Patent number: 11114400
    Abstract: A semiconductor device includes a semiconductor die, a redistribution structure, a interconnection structure, and a thermal path structure. The redistribution structure includes an insulation layer over a first surface of the semiconductor die and a conductive trace separated from the first surface by the insulation layer. The conductive trace extends laterally over the first surface from a first end toward a second end that is electrically coupled to a bond pad on the first surface of the semiconductor die. The interconnection structure is coupled to the first end of the conductive trace. The thermal path structure provides a thermal path between the semiconductor die and the interconnection structure. In some embodiment, the thermal path structure comprises a thermal pad that passes through the insulation layer. In other embodiments, the thermal path structure comprises a dummy pad on the first surface of the semiconductor die.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 7, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD.
    Inventor: Cameron Nelson
  • Patent number: 11101191
    Abstract: The present invention includes embodiments of a semiconductor package designed to transfer heat from one or more bridges within the package to ambient external to the package in addition to conducting the heat through any semiconductor chips encapsulated within the package. A laminated substrate has one or more horizontal layer heat conduction paths and one or more vertical substrate heat conduction paths. The vertical substrate heat conduction paths collect heat from one or more of the horizontal layer heat conduction paths, and eventually conduct the heat out of the semiconductor package, e.g. into a lid or heat sink.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kamal K. Sikka, Hiroyuki Mori
  • Patent number: 11088075
    Abstract: Back-end-of-line layout structures and methods of forming a back-end-of-line layout structure. A metallization level includes a plurality of interconnects positioned over a plurality of active device regions. The plurality of interconnects have a triangular-shaped layout and a plurality of lengths within the triangular-shaped layout.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 10, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Souvick Mitra, Rainer Thoma, Harsh Shah, Anindya Nath, Robert J. Gauthier, Jr.
  • Patent number: 11081419
    Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: August 3, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Dong Seong Oh, Si Hyeon Go
  • Patent number: 11075168
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 11063200
    Abstract: A device for guiding charge carriers and uses of the device are proposed, wherein the charge carriers are guided by means of a magnetic field along a curved or angled main path in a two-dimensional electron gas or in a thin superconducting layer, so that a different presence density is produced at electrical connections.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 13, 2021
    Inventor: Helmut Weidlich
  • Patent number: 11056456
    Abstract: A semiconductor apparatus includes a base plate, a metal plate disposed on the base plate, a bonding material disposed between the base plate and the metal plate to be in surface-to-surface contact with the base plate and the metal plate to bond the metal plate to the base plate, an insulating plate disposed on the metal plate, a circuit member disposed on the insulating plate to be in surface-to-surface contact with the insulating plate, a semiconductor device mounted on the circuit member, and an encapsulating material covering the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor device to encapsulate an area over the base plate, wherein a bottom face area of the metal plate along the outer perimeter of the metal plate is not covered with the bonding material, wherein the base plate has a groove-shape recess that is disposed along the outer perimeter of the metal plate to face the bottom surface area, wherein the recess has an area having a first depth and a
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 6, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hirotaka Oomori, Takashi Tsuno
  • Patent number: 11049894
    Abstract: An image sensor package includes a transparent material, and a substrate adhered to the transparent material. An image sensor is disposed on or within the substrate so that the image sensor is disposed between the substrate and the transparent material to receive light from an optical side of the image sensor package through the transparent material. A solder mask dam is disposed between the substrate and the transparent material to form a gap between the image sensor and the transparent material, and the solder mask dam is structured to indicate an orientation of the image sensor, when the image sensor is viewed from the optical side.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 29, 2021
    Assignee: OmniVision Technologies, Inc.
    Inventor: Chien-Chan Yeh
  • Patent number: 11037915
    Abstract: An IC chip comprises LED devices exposed on a front side of the IC chip, I/O bumps on a back side of the IC chip, a first die forming a stack with the LED devices and comprising driver circuits electrically connected to the LED devices, a first circuit that extends along the vertical direction from the front side of the IC chip towards a back side of the IC chip and across at least a thickness of the first die to provide electrical connections between the LED devices and at least some of the I/O bumps, a second die including pipelining circuits and control circuits for the driver circuits, a second circuit that extends from the second die, and a circuit board electrically connected to the I/O bumps and to a power system.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 15, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 11031345
    Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: June 8, 2021
    Assignee: Medtronic, Inc.
    Inventors: Chunho Kim, Mark R. Boone, Randolph E. Crutchfield
  • Patent number: 11018135
    Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 11004818
    Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 10971297
    Abstract: In an exemplary embodiment, a passive component which is a surface mounting component, includes: a substrate body 10 having insulation property; an internal conductor 50 embedded in the substrate body 10; and an external electrode 70 provided on the bottom face 12, which is the mounting surface, of the substrate body 10 and electrically connected to the internal conductor 50; wherein the external electrode 70 has a face 86 roughly parallel with the bottom face 12 of the substrate body 10, and a dome-shaped projection 80 that bulges, with reference to the roughly parallel face 86, away from the bottom face 12 of the substrate body 10. The passive component can prevent misalignment problems at mounting.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: April 6, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Takayuki Arai, Masanori Nagano
  • Patent number: 10957673
    Abstract: A semiconductor device of an embodiment includes a metal layer; a semiconductor chip on the metal layer and having an upper electrode and a lower electrode; a first wiring board electrically connected to the upper electrode, and includes a first, a second, a third plate-shaped portion, the first plate-shaped portion being parallel to the second plate-shaped portion, and the third plate-shaped portion being connected to the first and the second plate-shaped portion; a second wiring board electrically connected to the metal layer, and includes a fifth, a sixth, and a seventh plate-shaped portion, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to the fifth and the sixth plate-shaped portion. The first and the second plate-shaped portion are provided between the fifth and the sixth plate-shaped portion, and the semiconductor chip is positioned between the fifth and the sixth plate-shaped portion.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 23, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroshi Matsuyama
  • Patent number: 10935403
    Abstract: The present invention has been made to improve measurement accuracy of a thermal flow meter. In the thermal flow meter according to the invention, a circuit package (400) that measures a flow rate is molded in a first resin molding process. In a second resin molding process, a housing (302) having an inlet trench (351), a bypass passage trench on frontside (332), an outlet trench (353), and the like are formed through resin molding, and an outer circumferential surface of the circuit package (400) produced in the first resin molding process is enveloped by a resin in the second resin molding process to fix the circuit package (400) to the housing (302).
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 2, 2021
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Noboru Tokuyasu, Shinobu Tashiro, Keiji Hanzawa, Takeshi Morino, Ryosuke Doi, Akira Uenodan
  • Patent number: 10937725
    Abstract: A semiconductor device comprises: a ceramic substrate having conductor layers on both surfaces thereof; a semiconductor element joined to the upper surface conductor layer of the ceramic substrate; a frame member arranged on the upper surface conductor layer so as to surround a side surface of the semiconductor element; and an electrode, which is joined to an upper portion of the semiconductor element via a second fixing layer, and has fitting portions on a side surface of the electrode. On an inner wall of the frame member, fitting portions to be fitted to the fitting portions of the electrode and four positioning portions extending from the inner wall of the frame member to the side surfaces of the electrode are formed.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: March 2, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuya Muramatsu, Noriyuki Besshi, Ryuichi Ishii
  • Patent number: 10916429
    Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang
  • Patent number: 10916487
    Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bradley R. Bitz, Xiao Li, Jaspreet S. Gandhi
  • Patent number: 10910347
    Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Yong She, John G. Meyers, Zhicheng Ding, Richard Patten