Abstract: An integrated circuit probing method and apparatus therefor. The apparatus includes a main system controller coupled to a network interface, graphic user interface, and equipment interface. A high speed bus connects the main system controller to a group of subsystems. The subsystems includes subsystems such as input cassettes, input frame handing, frame to align, die align, die probing, die bin and die output, output cassettes subsystem, among others. The integrated circuit probing apparatus allows for probing of each individual die through the die probing subsystem, typically a high speed subsystem.

Abstract: A semiconductor device includes a substrate having a first surface, a second surface and at least one conductor parts which are exposed at both the first and second surfaces of the substrate, a semiconductor chip provided on the first surface of the substrate and having a plurality of electrode pads, a plurality of leads, a plurality of bonding-wires electrically connecting the leads and the conductor parts to corresponding ones of the electrode ads of the semiconductor chip, and a resin package encapsulating the semiconductor chip, part of the leads, and the substrate so that the conductor parts are exposed at the second surface of the substrate.

Abstract: A semiconductor package comprises at least one semiconductor chip; a lead frame having a chip paddle supporting a semiconductor chip, a plurality of inner leads wire-bonded to the chip and a plurality of outer lead extended from the inner leads; and a plastic molding compound sealing the chip and the inner lead of the lead frame, wherein the outer leads of the lead frame being arranged within an area of a bottom surface of the plastic molding compound.A lead frame for use in the semiconductor package comprises a plurality of inner leads to be connected respectively to pads of a semiconductor chip; a plurality of outer leads extended from the inner lead and to be connected to other circuit, and the outer leads being bent to downward from an internal end of the inner lead.

Abstract: A surface mounting type electronic component is provided which includes an electronic element enclosed in a resin package, and a plurality of leads electrically connected to the electronic element. Each of the leads has an inner lead portion inserted in the package and an outer lead portion extending out of the package. The outer lead portion has an end face includes a rounded bottom corner portion continuous with the flat bottom surface, a vertically scored lower portion following the rounded bottom corner portion, and a tear portion above the vertically scored portion.

Abstract: An IC carrier for electric testing of an IC package enables an IC package to be loaded on or unloaded from it smoothly without bending any of closely arranged fine leads, and prevents the leads from being deformed by falling impact when it is dropped. The IC carrier for an IC package, having an array of leads, comprises an array of sockets for mating with the array of leads, wherein selected one of the sockets differs in clearance between a width of each of the sockets and a width of each of the leads to be mated from the other ones in a cross section of an array. For instance, an array of sockets having holes to mate with leads having a single diameter of an IC package are arranged so that inner diameters of the holes in an outer part of the array is larger than those in a central part of the array. The technique is applicable to both a flat IC package (QFP or SOP) and a pin grid array IC package (PGA).

Abstract: A hybrid integrated circuit includes a plurality of metal plates supporting circuit elements and connectable directly to external power/output lines. The direct connection eliminates the need for solder terminals, allowing for reduced size and cost with increased reliability and lifespan. The metal plates can be position to allow for further minimization of the device, and uniform connection of internal wiring to the circuit elements.

Abstract: In a semiconductor device, a semiconductor element is stored in a casing while being held by external electrodes through first and second electrodes. The outer peripheral edge of the first electrode plate is projected outwardly beyond that of the semiconductor element and a ring-shaped groove is provided in the first surface of the first electrode plate along the outer peripheral edge of the semiconductor element such that a line, which is projected along the outer peripheral edge of the semiconductor element on the first surface of the first electrode plate, is located on the ring-shaped groove portion. The adhesive holding member is applied in the groove and the outer peripheral portion of the semiconductor element. Thus, the semiconductor element is fixed to the first electrode plate and is protected by the adhesive holding member which covers its end portion.

Abstract: A low inductance coaxial semiconductor switching module and methods of operating the same. The module can contain high power, high frequency semiconductor switching devices, operated to provide high power at low inductance. The module incorporates compositional, geometrical and electrical symmetry in a coaxial configuration. The module also includes short internal leads, a special circumferential array of substrates, a special circular gate circuit, a special circular kelvin circuit, and special terminal subassembly and special module mounting features.

Abstract: Disclosed is a stacked die carrier assembly and method for packaging and interconnecting silicon chips such as memory chips. The carrier is constructed from a metalized substrate onto which the chip is attached. The chip is wire bonded to the conductor pattern on the substrate. Each conductor then is routed to the edge of the substrate where it is connected to a half-circle of a metalized through hole. A frame is attached on top of this substrate. This frame has also a pattern of half-circle metalized through holes that aligns with the holes on the bottom substrate. The combination of the bottom substrate with the silicon die, and the frame on top, forms a basic stackable unit. Several such units can be stacked and attached on top of each other. The top unit can finally be covered with a ceramic lid that also has a matching half-circle metalized through hole pattern along its edge.

Abstract: A high power semiconductor module has an IMS substrate which carries the semiconductor die to be interconnected within the housing. A terminal board carries the terminals for connection to the substrate with a snap connection, with the terminals positioned above respective solder pads on the IMS board. Integral breakaway pins on the terminal board position the board relative to the IMS during soldering. A central opening in the terminal board allows the loading of a soft silicone into the space between the IMS substrate and bottom of the terminal board. The terminal board has bosses extending upwardly over its top surface adjacent each power terminal, and the bottom of a top housing assembly has ribs which enclose the bosses on the top of the terminal board. A silicone glue is poured onto the top of the terminal board and into the spaces between and around the bosses. The ribs project into this glue to provide a good insulation seal around the power terminals projecting through the terminal board.

Abstract: A semiconductor device comprises a tape member, an IC chip mounted on the tape member, a plurality of leads arranged on the tape member each having one end connected to the IC chip and the other end provided with an area to be used for testing the IC chip and an insulation member for covering said plurality of leads except the one ends and the areas to be used for testing the IC chip, the tape member being provided with one or more one openings that reach the plurality of leads. With such an arrangement, the plurality of leads can be easily accessed and brought into contact with probes for testing the IC chip.

Abstract: An axial lead frame including two side rails arranged opposite to each other and plural pairs of lead terminals separated from each other and located opposite to each other, in which a longer lead terminal and a shorter lead terminal of a pair of the lead terminals are alternately arranged to extend in parallel with each other in the equally spaced relationship between both side rails. And, a buffer member is formed at the substantially central part between both the side rails so as to allow the longer lead terminals extending from both the side rails toward the buffer member to be jointed to each other along the buffer member. A die pad is die-bonded to the foremost end of each of the longer lead terminal, while a pad is placed at the foremost end of each of the shorter lead terminal. Dam bars are bridged between adjacent lead terminals in order to prevent molten resin from flowing out during molding operation.

Abstract: In a semiconductor device comprising a copper lead brazed to a metal member of the device in a thermal process causing annealing and undesirable softening of the lead, the lead is stiffened in a process comprising applying a tensile force along the length of the lead and between it and the member to which it is brazed for stretching the lead beyond its elastic limit. The stretching process causes sitffening of the lead, removes bends in the lead, if present, and serves as a test for defective brazed joints.

Abstract: An integrated bus structure forms a multi-bit, parallel electrical signal bus between a plurality of integrated circuit dies. In one embodiment, the integrated circuit dies are disposed in a spaced, parallel arrangement and have terminal pads mounted at peripheral edges thereof and disposed in a predetermined positional and functional relationship. Electrical conductors interconnect the same positionally arranged terminal pad on each of the plurality of integrated circuit dies to form a parallel, multi-bit, bus arrangement. In another embodiment, at least one integrated circuit is mounted on a support member. The mounting pads on each integrated circuit die are electrically connected to terminal pads formed on the peripheral edge of each support member. Electrical conductors interconnect the same positionally arranged terminal pad on each of a plurality of support members to interconnect the integrated circuit dies on each support member in a parallel bus arrangement.

Abstract: A surface mounted diode comprises a pair of slugs pointed toward each other with a die disposed therebetween, at least one of the slugs being truncated cone shape, and a pair of solder wafers being disposed between the die and each slug to form an electrical connection therebetween. Each slug has a terminal formed at the tail thereof. The largest diameter of the truncated cone shape slug is approximately the same as or greater than the diagonal of the die. The function of the truncated shape of the slug is to protect the die from damage during handling and during curing of the encapsulating resin which occurs during the manufacturing process of the surface mounted diode.

Abstract: A semiconductor device package including a cup-like base having an encircling side wall having at its upper end, a laterally, outwardly extending metal flange. A lid for the package comprises a plate-like member having, at the lower, peripheral edge thereof, an outwardly laterally extending metal flange which overlaps and is bonded to the base flange in a solderless bond. In one embodiment of the invention, the lid has apertures therethrough which are sealed by metal foils bonded to the lower surface of the lid. The metal foils overlie and are bonded to electrodes on the upper surface of the chip within the package. In another embodiment of the invention, in which the lid also has apertures therethrough, a hollow tubing extends into each aperture in hermetic fit with the aperture wall. The chip within the package includes terminal leads extending into the tubings and hermetically bonded to the tubing inner walls.