Abstract: A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.

Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

Abstract: A semiconductor package structure includes a substrate, a chip, bumps, an encapsulation layer and a thermal expansion-matching layer. The chip is located on a top surface of the substrate. The bumps electrically connect the chip and the inner connection pads of the substrate. The encapsulation layer covers the bumps, the chip and the top surface of the substrate. The thermal expansion-matching layer covers the whole top surface of the encapsulation layer, and exposes the side surfaces of the encapsulation layer. The thermal expansion coefficient of the thermal expansion-matching layer is different from that of the encapsulation layer. The side surface of the thermal expansion-matching layer is flush with that of the encapsulation layer. The thermal expansion-matching layer balances the inner stresses caused by the difference of the thermal expansion. Thus, the invention reduces the warpage problem of the formed package.

Abstract: One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate.

Abstract: A semiconductor structure includes a first die including a first surface and a second surface opposite to the first surface; a molding surrounding the first die; a first via extended through the molding; an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed below the first surface of the first die and the molding, and the conductive member is disposed within the dielectric layer; and a second die disposed over the molding, wherein the second die is electrically connected to the first via.

Abstract: An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: There are provided a highly reliable semiconductor device capable of suppressing occurrence of cracks as well as securing flatness and a manufacturing method therefor. The semiconductor device includes: a semiconductor substrate; an element region; and a non-element region. The non-element region includes: a top-layer metal wiring in a top layer of metal wirings formed in the non-element region; a flattening film covering an upper surface of the top-layer metal wiring; and a protecting film formed over the flattening film. A removed part where the protecting film is removed is formed in at least part of the non-element region.

Abstract: A light-emitting device includes a base body; light-emitting elements mounted on an upper surface of the base body; a frame body bonded to the upper surface of the base body, the frame body including inner lateral surfaces, outer lateral surfaces, and first through-holes that extend through the frame body in a lateral direction; lead terminals that extend through the first through-holes, and each of which is electrically connected to the light-emitting elements; a cover bonded to the frame body; plate bodies bonded to an outer lateral surface or inner lateral surface of the frame body, each of the plate bodies having one or more second through-holes, wherein each of the lead terminals extends through a respective through-hole; and fixing members, each of which is disposed in a second through-hole and fixes a respective one of the one or more lead terminals.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.

Abstract: The present disclosure provides an electronic package, including a package substrate and an electronic component formed on the package substrate. The substrate includes an insulating portion, a wiring portion embedded in the insulating portion, and a metal board disposed on the insulating portion and in contact with the wiring portion. The metal board is provided with a plurality of electrical contacts and a heat dissipating portion. The metal board can maintain a predefined heat dissipation area via the heat dissipating portion, and be connected to a circuit board via the electrical contacts.

Abstract: A manufacturing method of a circuit board including the following steps is provided. A carrier substrate is provided. A patterned photoresist layer is formed on the carrier substrate. An adhesive layer is formed on the top surface of the patterned photoresist layer. A dielectric substrate is provided. A circuit pattern and a dielectric layer covering the circuit pattern are formed on the dielectric substrate, wherein the dielectric layer has an opening exposing a portion of the circuit pattern. The adhesive layer is adhered to the dielectric layer in a direction that the adhesive layer faces of the dielectric layer. The carrier substrate is removed. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed. The adhesive layer is removed.

Abstract: A semiconductor device includes a semiconductor substrate having a drift region of a first conductivity type; a base region of a second conductivity type in the semiconductor substrate; an emitter region of the first conductivity type in the semiconductor substrate; a first gate trench portion that is formed in the upper surface of the semiconductor substrate and is in contact with the emitter region and the base region; a second gate trench portion formed in the upper surface of the semiconductor substrate; a first electrical element electrically connected to the first gate trench portion; and a second electrical element electrically connected to the second gate trench portion, wherein a time constant of an RC circuit constituted by the second electrical element and the second gate trench portion is greater than a time constant of an RC circuit constituted by the first electrical element and the first gate trench portion.

Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.

Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.

Abstract: A connection structure includes: a wiring board including a plurality of first electrodes that are arranged on a principal surface; a molded interconnect device (MID) made of a non-electroconductive resin as a base material, the MID including a side surface and a bottom surface, the bottom surface being parallel to the principal surface of the wiring board and including a plurality of arranged second electrodes, and the side surface being perpendicular to the principal surface of the wiring board; and a plurality of electroconductive members each made of an electroconductive paste, each of the electroconductive members electrically connecting each of the plurality of first electrodes to each of the plurality of second electrodes, in which the plurality of electroconductive members are housed in respective reservoir sections formed by the second member and are not in contact with the non-electroconductive resin.

Abstract: An electronic device includes: a substrate that includes a first penetration hole; a first electrode that is located on a first surface of the substrate so as to cover the first penetration hole; and a first penetrating electrode that is located in the first penetration hole and is in contact with or away from the first electrode depending on temperature.

Abstract: Implementations of semiconductor packages may include: a substrate comprising a first side and a second side and a hole in the substrate. The hole extending from the first side to the second side of the substrate and positioned in a center of the substrate. The semiconductor packages may also include a bushing around the hole to the first side of the substrate. The semiconductor packages may also include a plurality of pin holders arranged and coupled on the substrate. The semiconductor package may also include a molding compound at least partially encapsulating the substrate, encapsulating a side surface of the bushing, and encapsulating a plurality of side surfaces of the plurality of pin holders.

Abstract: An adhesive with self-connecting interconnects is provided. The adhesive layer provides automatic 3D joining of microelectronic components with a conductively self-adjusting anisotropic matrix. In an implementation, the adhesive matrix automatically makes electrical connections between two surfaces that have opposing electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces.

Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.

Abstract: A die stack having a second die is stacked vertically on top of a first die. A first plurality of test pads is located along a first edge of the first die. A second plurality of test pads is located along a second edge of the first die. The first edge of the first die is parallel to the second edge of the first die. A third plurality of test pads is located along a first edge of the second die. A fourth plurality of test pads is located along a second edge of the second die. The first edge of the second die is parallel to the second edge of the second die. The first edge of the first die and the second edge of the first die are perpendicular to the first edge of the second die and the second edge of the second die.

Abstract: The invention relates to an electric interface, in particular an interposer, having a first connection plane with at least one first contact surface pair, each of which has a first and second contact surface, and a second connection plane with at least one second contact surface pair, each of which has a third and a fourth contact surface. For each of a first and second contact surface pair, a first electric connection electrically connects the first contact surface of the first connection plane to the third contact surface of the second connection plane, and a second electric connection electrically connects the second contact surface of the first connection plane to the fourth contact surface of the second connection plane.

Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

Abstract: A stretchable film includes a first region including a plurality of first patterns having a concave polygonal shape. The stretchable film also includes a second region including a plurality of second patterns having a concave polygonal shape. The stretchable film further includes a buffer region between the first region and the second region.

Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.

Abstract: Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface of the conductive copper pillars to metallization on the second side of the polymer film; bonding the semiconductor device to the first surface of the polymer film over the conductive pillars with an underfill material; and depositing an encapsulant material over the semiconductor device and polymer film.

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a substrate comprising a dielectric layer and a wiring pattern embedded in and exposed from the dielectric layer.

Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device. The semiconductor device structure includes a second conductive shielding layer under the first device. The first device is between the first conductive shielding layer and the second conductive shielding layer, and the second conductive shielding layer has a plurality of second openings.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.

Abstract: TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average through-hole density of the first region is greater than an average through-hole density of the entire semiconductor substrate. The average through-hole density of the entire semiconductor substrate is less than or equal to about 2%. A metal layer having a planarized surface is filled in the plurality of through-holes in the semiconductor substrate.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.

Abstract: One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

Abstract: A capacitive transducer includes a substrate having a first surface and a second surface opposite the first surface, the substrate including a through wire extending therethrough between the first surface and the second surface, and a cell on the first surface, the cell including a first electrode and a second electrode spaced apart from the first electrode with a gap between the first electrode and the second electrode. Conductive protective films are disposed over surfaces of the through wire on the first surface side and the second surface side of the substrate.

Abstract: In order to restrict cracking or the like in a connection member such as solder, provided is a semiconductor device including a first component; a second component that is arranged on a front surface of the first component; and a connection portion that is provided between the first component and the second component and connects the second component to the first component. A first groove and a second groove having different shapes are formed in the front surface of the first component at positions opposite a first corner and a second corner of the second component, and the connection portion is also formed within the first groove and the second groove.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.

Abstract: A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.

Abstract: In a switching module structure that includes a low-impedance path to ground, such as a parasitic capacitance of an insulating substrate, a further insulating substrate presenting a parasitic capacitance placed in series with the low impedance current path and a connection of a conductive layer to input voltage rails using a single decoupling capacitor or, preferably, a midpoint of the voltage rails formed by a series connection of decoupling capacitors maintains a large portion of common mode (CM) currents which are due to high dV/dt slew rates of SiC and GaN transistors within the switching module.